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b92e5a22 FB |
1 | /* |
2 | * Software MMU support | |
5fafdf24 | 3 | * |
efbf29b6 BS |
4 | * Generate helpers used by TCG for qemu_ld/st ops and code load |
5 | * functions. | |
6 | * | |
7 | * Included from target op helpers and exec.c. | |
8 | * | |
b92e5a22 FB |
9 | * Copyright (c) 2003 Fabrice Bellard |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 22 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
b92e5a22 | 23 | */ |
1de7afc9 | 24 | #include "qemu/timer.h" |
022c62cb | 25 | #include "exec/memory.h" |
29e922b6 | 26 | |
b92e5a22 FB |
27 | #define DATA_SIZE (1 << SHIFT) |
28 | ||
29 | #if DATA_SIZE == 8 | |
30 | #define SUFFIX q | |
61382a50 | 31 | #define USUFFIX q |
b92e5a22 FB |
32 | #define DATA_TYPE uint64_t |
33 | #elif DATA_SIZE == 4 | |
34 | #define SUFFIX l | |
61382a50 | 35 | #define USUFFIX l |
b92e5a22 FB |
36 | #define DATA_TYPE uint32_t |
37 | #elif DATA_SIZE == 2 | |
38 | #define SUFFIX w | |
61382a50 | 39 | #define USUFFIX uw |
b92e5a22 FB |
40 | #define DATA_TYPE uint16_t |
41 | #elif DATA_SIZE == 1 | |
42 | #define SUFFIX b | |
61382a50 | 43 | #define USUFFIX ub |
b92e5a22 FB |
44 | #define DATA_TYPE uint8_t |
45 | #else | |
46 | #error unsupported data size | |
47 | #endif | |
48 | ||
b769d8fe FB |
49 | #ifdef SOFTMMU_CODE_ACCESS |
50 | #define READ_ACCESS_TYPE 2 | |
84b7b8e7 | 51 | #define ADDR_READ addr_code |
b769d8fe FB |
52 | #else |
53 | #define READ_ACCESS_TYPE 0 | |
84b7b8e7 | 54 | #define ADDR_READ addr_read |
b769d8fe FB |
55 | #endif |
56 | ||
89c33337 | 57 | static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, |
a8170e5e | 58 | hwaddr physaddr, |
2e70f6ef | 59 | target_ulong addr, |
20503968 | 60 | uintptr_t retaddr) |
b92e5a22 | 61 | { |
791af8c8 | 62 | uint64_t val; |
37ec01d4 AK |
63 | MemoryRegion *mr = iotlb_to_region(physaddr); |
64 | ||
0f459d16 | 65 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
20503968 | 66 | env->mem_io_pc = retaddr; |
0844e007 | 67 | if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { |
2e70f6ef PB |
68 | cpu_io_recompile(env, retaddr); |
69 | } | |
b92e5a22 | 70 | |
db8886d3 | 71 | env->mem_io_vaddr = addr; |
791af8c8 PB |
72 | io_mem_read(mr, physaddr, &val, 1 << SHIFT); |
73 | return val; | |
b92e5a22 FB |
74 | } |
75 | ||
b92e5a22 | 76 | /* handle all cases except unaligned access which span two pages */ |
e25c3887 RH |
77 | #ifdef SOFTMMU_CODE_ACCESS |
78 | static | |
79 | #endif | |
e141ab52 | 80 | DATA_TYPE |
e25c3887 RH |
81 | glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, |
82 | target_ulong addr, int mmu_idx, | |
83 | uintptr_t retaddr) | |
b92e5a22 | 84 | { |
aac1fb05 RH |
85 | int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
86 | target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; | |
87 | uintptr_t haddr; | |
3b46e624 | 88 | |
aac1fb05 RH |
89 | /* If the TLB entry is for a different page, reload and try again. */ |
90 | if ((addr & TARGET_PAGE_MASK) | |
91 | != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { | |
a64d4718 | 92 | #ifdef ALIGNED_ONLY |
aac1fb05 | 93 | if ((addr & (DATA_SIZE - 1)) != 0) { |
89c33337 | 94 | do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
aac1fb05 | 95 | } |
a64d4718 | 96 | #endif |
aac1fb05 RH |
97 | tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
98 | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; | |
99 | } | |
100 | ||
101 | /* Handle an IO access. */ | |
102 | if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { | |
103 | hwaddr ioaddr; | |
104 | if ((addr & (DATA_SIZE - 1)) != 0) { | |
105 | goto do_unaligned_access; | |
b92e5a22 | 106 | } |
aac1fb05 RH |
107 | ioaddr = env->iotlb[mmu_idx][index]; |
108 | return glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr); | |
109 | } | |
110 | ||
111 | /* Handle slow unaligned access (it spans two pages or IO). */ | |
112 | if (DATA_SIZE > 1 | |
113 | && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 | |
114 | >= TARGET_PAGE_SIZE)) { | |
115 | target_ulong addr1, addr2; | |
116 | DATA_TYPE res1, res2, res; | |
117 | unsigned shift; | |
118 | do_unaligned_access: | |
a64d4718 | 119 | #ifdef ALIGNED_ONLY |
aac1fb05 | 120 | do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
a64d4718 | 121 | #endif |
aac1fb05 RH |
122 | addr1 = addr & ~(DATA_SIZE - 1); |
123 | addr2 = addr1 + DATA_SIZE; | |
124 | res1 = glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr1, | |
125 | mmu_idx, retaddr); | |
126 | res2 = glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr2, | |
127 | mmu_idx, retaddr); | |
128 | shift = (addr & (DATA_SIZE - 1)) * 8; | |
129 | #ifdef TARGET_WORDS_BIGENDIAN | |
130 | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift)); | |
131 | #else | |
132 | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift)); | |
133 | #endif | |
134 | return res; | |
135 | } | |
136 | ||
137 | /* Handle aligned access or unaligned access in the same page. */ | |
138 | #ifdef ALIGNED_ONLY | |
139 | if ((addr & (DATA_SIZE - 1)) != 0) { | |
140 | do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); | |
b92e5a22 | 141 | } |
aac1fb05 RH |
142 | #endif |
143 | ||
144 | haddr = addr + env->tlb_table[mmu_idx][index].addend; | |
145 | return glue(glue(ld, USUFFIX), _raw)((uint8_t *)haddr); | |
b92e5a22 FB |
146 | } |
147 | ||
e25c3887 RH |
148 | DATA_TYPE |
149 | glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, | |
150 | int mmu_idx) | |
151 | { | |
152 | return glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx, | |
153 | GETPC_EXT()); | |
154 | } | |
155 | ||
b769d8fe FB |
156 | #ifndef SOFTMMU_CODE_ACCESS |
157 | ||
89c33337 | 158 | static inline void glue(io_write, SUFFIX)(CPUArchState *env, |
a8170e5e | 159 | hwaddr physaddr, |
b769d8fe | 160 | DATA_TYPE val, |
0f459d16 | 161 | target_ulong addr, |
20503968 | 162 | uintptr_t retaddr) |
b769d8fe | 163 | { |
37ec01d4 AK |
164 | MemoryRegion *mr = iotlb_to_region(physaddr); |
165 | ||
0f459d16 | 166 | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
0844e007 | 167 | if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { |
2e70f6ef PB |
168 | cpu_io_recompile(env, retaddr); |
169 | } | |
b769d8fe | 170 | |
2e70f6ef | 171 | env->mem_io_vaddr = addr; |
20503968 | 172 | env->mem_io_pc = retaddr; |
37ec01d4 | 173 | io_mem_write(mr, physaddr, val, 1 << SHIFT); |
b769d8fe | 174 | } |
b92e5a22 | 175 | |
e25c3887 RH |
176 | void |
177 | glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, | |
178 | target_ulong addr, DATA_TYPE val, | |
179 | int mmu_idx, uintptr_t retaddr) | |
b92e5a22 | 180 | { |
aac1fb05 RH |
181 | int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
182 | target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; | |
183 | uintptr_t haddr; | |
3b46e624 | 184 | |
aac1fb05 RH |
185 | /* If the TLB entry is for a different page, reload and try again. */ |
186 | if ((addr & TARGET_PAGE_MASK) | |
187 | != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { | |
a64d4718 | 188 | #ifdef ALIGNED_ONLY |
aac1fb05 | 189 | if ((addr & (DATA_SIZE - 1)) != 0) { |
89c33337 | 190 | do_unaligned_access(env, addr, 1, mmu_idx, retaddr); |
aac1fb05 | 191 | } |
a64d4718 | 192 | #endif |
aac1fb05 RH |
193 | tlb_fill(env, addr, 1, mmu_idx, retaddr); |
194 | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; | |
195 | } | |
196 | ||
197 | /* Handle an IO access. */ | |
198 | if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { | |
199 | hwaddr ioaddr; | |
200 | if ((addr & (DATA_SIZE - 1)) != 0) { | |
201 | goto do_unaligned_access; | |
202 | } | |
203 | ioaddr = env->iotlb[mmu_idx][index]; | |
204 | glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr); | |
205 | return; | |
206 | } | |
207 | ||
208 | /* Handle slow unaligned access (it spans two pages or IO). */ | |
209 | if (DATA_SIZE > 1 | |
210 | && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 | |
211 | >= TARGET_PAGE_SIZE)) { | |
212 | int i; | |
213 | do_unaligned_access: | |
a64d4718 | 214 | #ifdef ALIGNED_ONLY |
aac1fb05 RH |
215 | do_unaligned_access(env, addr, 1, mmu_idx, retaddr); |
216 | #endif | |
217 | /* XXX: not efficient, but simple */ | |
218 | /* Note: relies on the fact that tlb_fill() does not remove the | |
219 | * previous page from the TLB cache. */ | |
220 | for (i = DATA_SIZE - 1; i >= 0; i--) { | |
221 | #ifdef TARGET_WORDS_BIGENDIAN | |
222 | uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8)); | |
223 | #else | |
224 | uint8_t val8 = val >> (i * 8); | |
a64d4718 | 225 | #endif |
aac1fb05 RH |
226 | glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, |
227 | mmu_idx, retaddr); | |
b92e5a22 | 228 | } |
aac1fb05 RH |
229 | return; |
230 | } | |
231 | ||
232 | /* Handle aligned access or unaligned access in the same page. */ | |
a64d4718 | 233 | #ifdef ALIGNED_ONLY |
aac1fb05 RH |
234 | if ((addr & (DATA_SIZE - 1)) != 0) { |
235 | do_unaligned_access(env, addr, 1, mmu_idx, retaddr); | |
b92e5a22 | 236 | } |
aac1fb05 RH |
237 | #endif |
238 | ||
239 | haddr = addr + env->tlb_table[mmu_idx][index].addend; | |
240 | glue(glue(st, SUFFIX), _raw)((uint8_t *)haddr, val); | |
b92e5a22 FB |
241 | } |
242 | ||
e25c3887 RH |
243 | void |
244 | glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, | |
245 | DATA_TYPE val, int mmu_idx) | |
246 | { | |
247 | glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, val, mmu_idx, | |
248 | GETPC_EXT()); | |
249 | } | |
250 | ||
b769d8fe FB |
251 | #endif /* !defined(SOFTMMU_CODE_ACCESS) */ |
252 | ||
253 | #undef READ_ACCESS_TYPE | |
b92e5a22 FB |
254 | #undef SHIFT |
255 | #undef DATA_TYPE | |
256 | #undef SUFFIX | |
61382a50 | 257 | #undef USUFFIX |
b92e5a22 | 258 | #undef DATA_SIZE |
84b7b8e7 | 259 | #undef ADDR_READ |