[mirror_qemu.git] / include / exec / softmmu_template.h

/*
 *  Software MMU support
 *
 * Generate helpers used by TCG for qemu_ld/st ops and code load
 * functions.
 *
 * Included from target op helpers and exec.c.
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/timer.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"

#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define LSUFFIX q
#define SDATA_TYPE  int64_t
#define DATA_TYPE  uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define LSUFFIX l
#define SDATA_TYPE  int32_t
#define DATA_TYPE  uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define LSUFFIX uw
#define SDATA_TYPE  int16_t
#define DATA_TYPE  uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define LSUFFIX ub
#define SDATA_TYPE  int8_t
#define DATA_TYPE  uint8_t
#else
#error unsupported data size
#endif


/* For the benefit of TCG generated code, we want to avoid the complication
   of ABI-specific return type promotion and always return a value extended
   to the register size of the host.  This is tcg_target_long, except in the
   case of a 32-bit host and 64-bit data, and for that we always have
   uint64_t.  Don't bother with this widened value for SOFTMMU_CODE_ACCESS.  */
#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
# define WORD_TYPE  DATA_TYPE
# define USUFFIX    SUFFIX
#else
# define WORD_TYPE  tcg_target_ulong
# define USUFFIX    glue(u, SUFFIX)
# define SSUFFIX    glue(s, SUFFIX)
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

#if DATA_SIZE == 8
# define BSWAP(X)  bswap64(X)
#elif DATA_SIZE == 4
# define BSWAP(X)  bswap32(X)
#elif DATA_SIZE == 2
# define BSWAP(X)  bswap16(X)
#else
# define BSWAP(X)  (X)
#endif

#ifdef TARGET_WORDS_BIGENDIAN
# define TGT_BE(X)  (X)
# define TGT_LE(X)  BSWAP(X)
#else
# define TGT_BE(X)  BSWAP(X)
# define TGT_LE(X)  (X)
#endif

#if DATA_SIZE == 1
# define helper_le_ld_name  glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
# define helper_be_ld_name  helper_le_ld_name
# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
# define helper_be_lds_name helper_le_lds_name
# define helper_le_st_name  glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
# define helper_be_st_name  helper_le_st_name
#else
# define helper_le_ld_name  glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
# define helper_be_ld_name  glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
# define helper_le_st_name  glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
# define helper_be_st_name  glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
#endif

#ifdef TARGET_WORDS_BIGENDIAN
# define helper_te_ld_name  helper_be_ld_name
# define helper_te_st_name  helper_be_st_name
#else
# define helper_te_ld_name  helper_le_ld_name
# define helper_te_st_name  helper_le_st_name
#endif

static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
                                              hwaddr physaddr,
                                              target_ulong addr,
                                              uintptr_t retaddr)
{
    uint64_t val;
    CPUState *cpu = ENV_GET_CPU(env);
    MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    cpu->mem_io_pc = retaddr;
    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
        cpu_io_recompile(cpu, retaddr);
    }

    cpu->mem_io_vaddr = addr;
    io_mem_read(mr, physaddr, &val, 1 << SHIFT);
    return val;
}

#ifdef SOFTMMU_CODE_ACCESS
static __attribute__((unused))
#endif
WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
                            uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    uintptr_t haddr;
    DATA_TYPE res;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                                 mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
        res = TGT_LE(res);
        return res;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                    >= TARGET_PAGE_SIZE)) {
        target_ulong addr1, addr2;
        DATA_TYPE res1, res2;
        unsigned shift;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
#endif
        addr1 = addr & ~(DATA_SIZE - 1);
        addr2 = addr1 + DATA_SIZE;
        /* Note the adjustment at the beginning of the function.
           Undo that for the recursion.  */
        res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
        res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
        shift = (addr & (DATA_SIZE - 1)) * 8;

        /* Little-endian combine.  */
        res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
        return res;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
#if DATA_SIZE == 1
    res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
#else
    res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
#endif
    return res;
}

#if DATA_SIZE > 1
#ifdef SOFTMMU_CODE_ACCESS
static __attribute__((unused))
#endif
WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
                            uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    uintptr_t haddr;
    DATA_TYPE res;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                                 mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
        res = TGT_BE(res);
        return res;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                    >= TARGET_PAGE_SIZE)) {
        target_ulong addr1, addr2;
        DATA_TYPE res1, res2;
        unsigned shift;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
#endif
        addr1 = addr & ~(DATA_SIZE - 1);
        addr2 = addr1 + DATA_SIZE;
        /* Note the adjustment at the beginning of the function.
           Undo that for the recursion.  */
        res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
        res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
        shift = (addr & (DATA_SIZE - 1)) * 8;

        /* Big-endian combine.  */
        res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
        return res;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
                             mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
    res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
    return res;
}
#endif /* DATA_SIZE > 1 */

DATA_TYPE
glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
                                         int mmu_idx)
{
    return helper_te_ld_name (env, addr, mmu_idx, GETRA());
}

#ifndef SOFTMMU_CODE_ACCESS

/* Provide signed versions of the load routines as well.  We can of course
   avoid this for 64-bit data, or for 32-bit data on 32-bit host.  */
#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
                             int mmu_idx, uintptr_t retaddr)
{
    return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
}

# if DATA_SIZE > 1
WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
                             int mmu_idx, uintptr_t retaddr)
{
    return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
}
# endif
#endif

static inline void glue(io_write, SUFFIX)(CPUArchState *env,
                                          hwaddr physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          uintptr_t retaddr)
{
    CPUState *cpu = ENV_GET_CPU(env);
    MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
        cpu_io_recompile(cpu, retaddr);
    }

    cpu->mem_io_vaddr = addr;
    cpu->mem_io_pc = retaddr;
    io_mem_write(mr, physaddr, val, 1 << SHIFT);
}

void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
                       int mmu_idx, uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    uintptr_t haddr;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        val = TGT_LE(val);
        glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
        return;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                     >= TARGET_PAGE_SIZE)) {
        int i;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
#endif
        /* XXX: not efficient, but simple */
        /* Note: relies on the fact that tlb_fill() does not remove the
         * previous page from the TLB cache.  */
        for (i = DATA_SIZE - 1; i >= 0; i--) {
            /* Little-endian extract.  */
            uint8_t val8 = val >> (i * 8);
            /* Note the adjustment at the beginning of the function.
               Undo that for the recursion.  */
            glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
                                            mmu_idx, retaddr + GETPC_ADJ);
        }
        return;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
#if DATA_SIZE == 1
    glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
#else
    glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
#endif
}

#if DATA_SIZE > 1
void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
                       int mmu_idx, uintptr_t retaddr)
{
    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    uintptr_t haddr;

    /* Adjust the given return address.  */
    retaddr -= GETPC_ADJ;

    /* If the TLB entry is for a different page, reload and try again.  */
    if ((addr & TARGET_PAGE_MASK)
        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0) {
            cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        }
#endif
        tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
        tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    }

    /* Handle an IO access.  */
    if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
        hwaddr ioaddr;
        if ((addr & (DATA_SIZE - 1)) != 0) {
            goto do_unaligned_access;
        }
        ioaddr = env->iotlb[mmu_idx][index];

        /* ??? Note that the io helpers always read data in the target
           byte ordering.  We should push the LE/BE request down into io.  */
        val = TGT_BE(val);
        glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
        return;
    }

    /* Handle slow unaligned access (it spans two pages or IO).  */
    if (DATA_SIZE > 1
        && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
                     >= TARGET_PAGE_SIZE)) {
        int i;
    do_unaligned_access:
#ifdef ALIGNED_ONLY
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
#endif
        /* XXX: not efficient, but simple */
        /* Note: relies on the fact that tlb_fill() does not remove the
         * previous page from the TLB cache.  */
        for (i = DATA_SIZE - 1; i >= 0; i--) {
            /* Big-endian extract.  */
            uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
            /* Note the adjustment at the beginning of the function.
               Undo that for the recursion.  */
            glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
                                            mmu_idx, retaddr + GETPC_ADJ);
        }
        return;
    }

    /* Handle aligned access or unaligned access in the same page.  */
#ifdef ALIGNED_ONLY
    if ((addr & (DATA_SIZE - 1)) != 0) {
        cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
    }
#endif

    haddr = addr + env->tlb_table[mmu_idx][index].addend;
    glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
}
#endif /* DATA_SIZE > 1 */

void
glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
                                         DATA_TYPE val, int mmu_idx)
{
    helper_te_st_name(env, addr, val, mmu_idx, GETRA());
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef LSUFFIX
#undef DATA_SIZE
#undef ADDR_READ
#undef WORD_TYPE
#undef SDATA_TYPE
#undef USUFFIX
#undef SSUFFIX
#undef BSWAP
#undef TGT_BE
#undef TGT_LE
#undef CPU_BE
#undef CPU_LE
#undef helper_le_ld_name
#undef helper_be_ld_name
#undef helper_le_lds_name
#undef helper_be_lds_name
#undef helper_le_st_name
#undef helper_be_st_name
#undef helper_te_ld_name
#undef helper_te_st_name
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
efbf29b6 BS	4	* Generate helpers used by TCG for qemu_ld/st ops and code load
	5	* functions.
	6	*
	7	* Included from target op helpers and exec.c.
	8	*
b92e5a22 FB	9	* Copyright (c) 2003 Fabrice Bellard
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
8167ee88	22	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22	23	*/
1de7afc9	24	#include "qemu/timer.h"
77717094	25	#include "exec/address-spaces.h"
022c62cb	26	#include "exec/memory.h"
29e922b6	27
b92e5a22 FB	28	#define DATA_SIZE (1 << SHIFT)
	29
	30	#if DATA_SIZE == 8
	31	#define SUFFIX q
701e3a5c	32	#define LSUFFIX q
c8f94df5	33	#define SDATA_TYPE int64_t
dc9a353c	34	#define DATA_TYPE uint64_t
b92e5a22 FB	35	#elif DATA_SIZE == 4
b92e5a22 FB	36	#define SUFFIX l
701e3a5c	37	#define LSUFFIX l
c8f94df5	38	#define SDATA_TYPE int32_t
dc9a353c	39	#define DATA_TYPE uint32_t
b92e5a22 FB	40	#elif DATA_SIZE == 2
b92e5a22 FB	41	#define SUFFIX w
701e3a5c	42	#define LSUFFIX uw
c8f94df5	43	#define SDATA_TYPE int16_t
dc9a353c	44	#define DATA_TYPE uint16_t
b92e5a22 FB	45	#elif DATA_SIZE == 1
b92e5a22 FB	46	#define SUFFIX b
701e3a5c	47	#define LSUFFIX ub
c8f94df5	48	#define SDATA_TYPE int8_t
dc9a353c	49	#define DATA_TYPE uint8_t
b92e5a22 FB	50	#else
	51	#error unsupported data size
	52	#endif
	53
c8f94df5 RH	54
	55	/* For the benefit of TCG generated code, we want to avoid the complication
	56	of ABI-specific return type promotion and always return a value extended
	57	to the register size of the host. This is tcg_target_long, except in the
	58	case of a 32-bit host and 64-bit data, and for that we always have
	59	uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
	60	#if defined(SOFTMMU_CODE_ACCESS) \|\| DATA_SIZE == 8
	61	# define WORD_TYPE DATA_TYPE
	62	# define USUFFIX SUFFIX
	63	#else
	64	# define WORD_TYPE tcg_target_ulong
	65	# define USUFFIX glue(u, SUFFIX)
	66	# define SSUFFIX glue(s, SUFFIX)
	67	#endif
	68
b769d8fe FB	69	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	70	#define READ_ACCESS_TYPE 2
84b7b8e7	71	#define ADDR_READ addr_code
b769d8fe FB	72	#else
b769d8fe FB	73	#define READ_ACCESS_TYPE 0
84b7b8e7	74	#define ADDR_READ addr_read
b769d8fe FB	75	#endif
b769d8fe FB	76
867b3201 RH	77	#if DATA_SIZE == 8
	78	# define BSWAP(X) bswap64(X)
	79	#elif DATA_SIZE == 4
	80	# define BSWAP(X) bswap32(X)
	81	#elif DATA_SIZE == 2
	82	# define BSWAP(X) bswap16(X)
	83	#else
	84	# define BSWAP(X) (X)
	85	#endif
	86
	87	#ifdef TARGET_WORDS_BIGENDIAN
	88	# define TGT_BE(X) (X)
	89	# define TGT_LE(X) BSWAP(X)
	90	#else
	91	# define TGT_BE(X) BSWAP(X)
	92	# define TGT_LE(X) (X)
	93	#endif
	94
	95	#if DATA_SIZE == 1
	96	# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
	97	# define helper_be_ld_name helper_le_ld_name
	98	# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
	99	# define helper_be_lds_name helper_le_lds_name
	100	# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
	101	# define helper_be_st_name helper_le_st_name
	102	#else
	103	# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
	104	# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
	105	# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
	106	# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
	107	# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
	108	# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
	109	#endif
	110
	111	#ifdef TARGET_WORDS_BIGENDIAN
	112	# define helper_te_ld_name helper_be_ld_name
	113	# define helper_te_st_name helper_be_st_name
	114	#else
	115	# define helper_te_ld_name helper_le_ld_name
	116	# define helper_te_st_name helper_le_st_name
	117	#endif
	118
89c33337	119	static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
a8170e5e	120	hwaddr physaddr,
2e70f6ef	121	target_ulong addr,
20503968	122	uintptr_t retaddr)
b92e5a22	123	{
791af8c8	124	uint64_t val;
09daed84 EI	125	CPUState *cpu = ENV_GET_CPU(env);
09daed84 EI	126	MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
37ec01d4	127
0f459d16	128	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
93afeade	129	cpu->mem_io_pc = retaddr;
99df7dce	130	if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
90b40a69	131	cpu_io_recompile(cpu, retaddr);
2e70f6ef	132	}
b92e5a22	133
93afeade	134	cpu->mem_io_vaddr = addr;
791af8c8 PB	135	io_mem_read(mr, physaddr, &val, 1 << SHIFT);
791af8c8 PB	136	return val;
b92e5a22 FB	137	}
b92e5a22 FB	138
e25c3887	139	#ifdef SOFTMMU_CODE_ACCESS
867b3201	140	static __attribute__((unused))
e25c3887	141	#endif
867b3201 RH	142	WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
867b3201 RH	143	uintptr_t retaddr)
b92e5a22	144	{
aac1fb05 RH	145	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	146	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	147	uintptr_t haddr;
867b3201	148	DATA_TYPE res;
3b46e624	149
0f842f8a RH	150	/* Adjust the given return address. */
	151	retaddr -= GETPC_ADJ;
	152
aac1fb05 RH	153	/* If the TLB entry is for a different page, reload and try again. */
	154	if ((addr & TARGET_PAGE_MASK)
	155	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a64d4718	156	#ifdef ALIGNED_ONLY
aac1fb05	157	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	158	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	159	mmu_idx, retaddr);
aac1fb05	160	}
a64d4718	161	#endif
d5a11fef	162	tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
aac1fb05 RH	163	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	164	}
	165
	166	/* Handle an IO access. */
	167	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	168	hwaddr ioaddr;
	169	if ((addr & (DATA_SIZE - 1)) != 0) {
	170	goto do_unaligned_access;
b92e5a22	171	}
aac1fb05	172	ioaddr = env->iotlb[mmu_idx][index];
867b3201 RH	173
	174	/* ??? Note that the io helpers always read data in the target
	175	byte ordering. We should push the LE/BE request down into io. */
	176	res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
	177	res = TGT_LE(res);
	178	return res;
aac1fb05 RH	179	}
	180
	181	/* Handle slow unaligned access (it spans two pages or IO). */
	182	if (DATA_SIZE > 1
	183	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	184	>= TARGET_PAGE_SIZE)) {
	185	target_ulong addr1, addr2;
867b3201	186	DATA_TYPE res1, res2;
aac1fb05 RH	187	unsigned shift;
aac1fb05 RH	188	do_unaligned_access:
a64d4718	189	#ifdef ALIGNED_ONLY
93e22326 PB	190	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	191	mmu_idx, retaddr);
a64d4718	192	#endif
aac1fb05 RH	193	addr1 = addr & ~(DATA_SIZE - 1);
aac1fb05 RH	194	addr2 = addr1 + DATA_SIZE;
0f842f8a RH	195	/* Note the adjustment at the beginning of the function.
0f842f8a RH	196	Undo that for the recursion. */
867b3201 RH	197	res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
867b3201 RH	198	res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
aac1fb05	199	shift = (addr & (DATA_SIZE - 1)) * 8;
867b3201 RH	200
867b3201 RH	201	/* Little-endian combine. */
aac1fb05	202	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
867b3201 RH	203	return res;
	204	}
	205
	206	/* Handle aligned access or unaligned access in the same page. */
	207	#ifdef ALIGNED_ONLY
	208	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	209	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	210	mmu_idx, retaddr);
867b3201 RH	211	}
	212	#endif
	213
	214	haddr = addr + env->tlb_table[mmu_idx][index].addend;
	215	#if DATA_SIZE == 1
	216	res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
	217	#else
	218	res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
	219	#endif
	220	return res;
	221	}
	222
	223	#if DATA_SIZE > 1
	224	#ifdef SOFTMMU_CODE_ACCESS
	225	static __attribute__((unused))
	226	#endif
	227	WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
	228	uintptr_t retaddr)
	229	{
	230	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	231	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	232	uintptr_t haddr;
	233	DATA_TYPE res;
	234
	235	/* Adjust the given return address. */
	236	retaddr -= GETPC_ADJ;
	237
	238	/* If the TLB entry is for a different page, reload and try again. */
	239	if ((addr & TARGET_PAGE_MASK)
	240	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	241	#ifdef ALIGNED_ONLY
	242	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	243	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	244	mmu_idx, retaddr);
867b3201 RH	245	}
867b3201 RH	246	#endif
d5a11fef	247	tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
867b3201 RH	248	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
	249	}
	250
	251	/* Handle an IO access. */
	252	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	253	hwaddr ioaddr;
	254	if ((addr & (DATA_SIZE - 1)) != 0) {
	255	goto do_unaligned_access;
	256	}
	257	ioaddr = env->iotlb[mmu_idx][index];
	258
	259	/* ??? Note that the io helpers always read data in the target
	260	byte ordering. We should push the LE/BE request down into io. */
	261	res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
	262	res = TGT_BE(res);
	263	return res;
	264	}
	265
	266	/* Handle slow unaligned access (it spans two pages or IO). */
	267	if (DATA_SIZE > 1
	268	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	269	>= TARGET_PAGE_SIZE)) {
	270	target_ulong addr1, addr2;
	271	DATA_TYPE res1, res2;
	272	unsigned shift;
	273	do_unaligned_access:
	274	#ifdef ALIGNED_ONLY
93e22326 PB	275	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	276	mmu_idx, retaddr);
aac1fb05	277	#endif
867b3201 RH	278	addr1 = addr & ~(DATA_SIZE - 1);
	279	addr2 = addr1 + DATA_SIZE;
	280	/* Note the adjustment at the beginning of the function.
	281	Undo that for the recursion. */
	282	res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
	283	res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
	284	shift = (addr & (DATA_SIZE - 1)) * 8;
	285
	286	/* Big-endian combine. */
	287	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
aac1fb05 RH	288	return res;
	289	}
	290
	291	/* Handle aligned access or unaligned access in the same page. */
	292	#ifdef ALIGNED_ONLY
	293	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326 PB	294	cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
93e22326 PB	295	mmu_idx, retaddr);
b92e5a22	296	}
aac1fb05 RH	297	#endif
	298
	299	haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201 RH	300	res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
867b3201 RH	301	return res;
b92e5a22	302	}
867b3201	303	#endif /* DATA_SIZE > 1 */
b92e5a22	304
e25c3887 RH	305	DATA_TYPE
	306	glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
	307	int mmu_idx)
	308	{
867b3201	309	return helper_te_ld_name (env, addr, mmu_idx, GETRA());
e25c3887 RH	310	}
e25c3887 RH	311
b769d8fe FB	312	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	313
c8f94df5 RH	314	/* Provide signed versions of the load routines as well. We can of course
	315	avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
	316	#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
867b3201 RH	317	WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
	318	int mmu_idx, uintptr_t retaddr)
	319	{
	320	return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
	321	}
	322
	323	# if DATA_SIZE > 1
	324	WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
	325	int mmu_idx, uintptr_t retaddr)
c8f94df5	326	{
867b3201	327	return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
c8f94df5	328	}
867b3201	329	# endif
c8f94df5 RH	330	#endif
c8f94df5 RH	331
89c33337	332	static inline void glue(io_write, SUFFIX)(CPUArchState *env,
a8170e5e	333	hwaddr physaddr,
b769d8fe	334	DATA_TYPE val,
0f459d16	335	target_ulong addr,
20503968	336	uintptr_t retaddr)
b769d8fe	337	{
09daed84 EI	338	CPUState *cpu = ENV_GET_CPU(env);
09daed84 EI	339	MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
37ec01d4	340
0f459d16	341	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
99df7dce	342	if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
90b40a69	343	cpu_io_recompile(cpu, retaddr);
2e70f6ef	344	}
b769d8fe	345
93afeade AF	346	cpu->mem_io_vaddr = addr;
93afeade AF	347	cpu->mem_io_pc = retaddr;
37ec01d4	348	io_mem_write(mr, physaddr, val, 1 << SHIFT);
b769d8fe	349	}
b92e5a22	350
867b3201 RH	351	void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
867b3201 RH	352	int mmu_idx, uintptr_t retaddr)
b92e5a22	353	{
aac1fb05 RH	354	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	355	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	356	uintptr_t haddr;
3b46e624	357
0f842f8a RH	358	/* Adjust the given return address. */
	359	retaddr -= GETPC_ADJ;
	360
aac1fb05 RH	361	/* If the TLB entry is for a different page, reload and try again. */
	362	if ((addr & TARGET_PAGE_MASK)
	363	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
a64d4718	364	#ifdef ALIGNED_ONLY
aac1fb05	365	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	366	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
aac1fb05	367	}
a64d4718	368	#endif
d5a11fef	369	tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
aac1fb05 RH	370	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	371	}
	372
	373	/* Handle an IO access. */
	374	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	375	hwaddr ioaddr;
	376	if ((addr & (DATA_SIZE - 1)) != 0) {
	377	goto do_unaligned_access;
	378	}
	379	ioaddr = env->iotlb[mmu_idx][index];
867b3201 RH	380
	381	/* ??? Note that the io helpers always read data in the target
	382	byte ordering. We should push the LE/BE request down into io. */
	383	val = TGT_LE(val);
aac1fb05 RH	384	glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
	385	return;
	386	}
	387
	388	/* Handle slow unaligned access (it spans two pages or IO). */
	389	if (DATA_SIZE > 1
	390	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	391	>= TARGET_PAGE_SIZE)) {
	392	int i;
	393	do_unaligned_access:
a64d4718	394	#ifdef ALIGNED_ONLY
93e22326	395	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
aac1fb05 RH	396	#endif
	397	/* XXX: not efficient, but simple */
	398	/* Note: relies on the fact that tlb_fill() does not remove the
	399	* previous page from the TLB cache. */
	400	for (i = DATA_SIZE - 1; i >= 0; i--) {
867b3201	401	/* Little-endian extract. */
aac1fb05	402	uint8_t val8 = val >> (i * 8);
867b3201 RH	403	/* Note the adjustment at the beginning of the function.
	404	Undo that for the recursion. */
	405	glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
	406	mmu_idx, retaddr + GETPC_ADJ);
	407	}
	408	return;
	409	}
	410
	411	/* Handle aligned access or unaligned access in the same page. */
	412	#ifdef ALIGNED_ONLY
	413	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	414	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	415	}
	416	#endif
	417
	418	haddr = addr + env->tlb_table[mmu_idx][index].addend;
	419	#if DATA_SIZE == 1
	420	glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
	421	#else
	422	glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
a64d4718	423	#endif
867b3201 RH	424	}
	425
	426	#if DATA_SIZE > 1
	427	void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
	428	int mmu_idx, uintptr_t retaddr)
	429	{
	430	int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	431	target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	432	uintptr_t haddr;
	433
	434	/* Adjust the given return address. */
	435	retaddr -= GETPC_ADJ;
	436
	437	/* If the TLB entry is for a different page, reload and try again. */
	438	if ((addr & TARGET_PAGE_MASK)
	439	!= (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	440	#ifdef ALIGNED_ONLY
	441	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	442	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	443	}
867b3201 RH	444	#endif
d5a11fef	445	tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	446	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
	447	}
	448
	449	/* Handle an IO access. */
	450	if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
	451	hwaddr ioaddr;
	452	if ((addr & (DATA_SIZE - 1)) != 0) {
	453	goto do_unaligned_access;
	454	}
	455	ioaddr = env->iotlb[mmu_idx][index];
	456
	457	/* ??? Note that the io helpers always read data in the target
	458	byte ordering. We should push the LE/BE request down into io. */
	459	val = TGT_BE(val);
	460	glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
	461	return;
	462	}
	463
	464	/* Handle slow unaligned access (it spans two pages or IO). */
	465	if (DATA_SIZE > 1
	466	&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
	467	>= TARGET_PAGE_SIZE)) {
	468	int i;
	469	do_unaligned_access:
	470	#ifdef ALIGNED_ONLY
93e22326	471	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
867b3201 RH	472	#endif
	473	/* XXX: not efficient, but simple */
	474	/* Note: relies on the fact that tlb_fill() does not remove the
	475	* previous page from the TLB cache. */
	476	for (i = DATA_SIZE - 1; i >= 0; i--) {
	477	/* Big-endian extract. */
	478	uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
0f842f8a RH	479	/* Note the adjustment at the beginning of the function.
0f842f8a RH	480	Undo that for the recursion. */
aac1fb05	481	glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
0f842f8a	482	mmu_idx, retaddr + GETPC_ADJ);
b92e5a22	483	}
aac1fb05 RH	484	return;
	485	}
	486
	487	/* Handle aligned access or unaligned access in the same page. */
a64d4718	488	#ifdef ALIGNED_ONLY
aac1fb05	489	if ((addr & (DATA_SIZE - 1)) != 0) {
93e22326	490	cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
b92e5a22	491	}
aac1fb05 RH	492	#endif
	493
	494	haddr = addr + env->tlb_table[mmu_idx][index].addend;
867b3201	495	glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
b92e5a22	496	}
867b3201	497	#endif /* DATA_SIZE > 1 */
b92e5a22	498
e25c3887 RH	499	void
	500	glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
	501	DATA_TYPE val, int mmu_idx)
	502	{
867b3201	503	helper_te_st_name(env, addr, val, mmu_idx, GETRA());
e25c3887 RH	504	}
e25c3887 RH	505
b769d8fe FB	506	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	507
	508	#undef READ_ACCESS_TYPE
b92e5a22 FB	509	#undef SHIFT
	510	#undef DATA_TYPE
	511	#undef SUFFIX
701e3a5c	512	#undef LSUFFIX
b92e5a22	513	#undef DATA_SIZE
84b7b8e7	514	#undef ADDR_READ
c8f94df5 RH	515	#undef WORD_TYPE
	516	#undef SDATA_TYPE
	517	#undef USUFFIX
	518	#undef SSUFFIX
867b3201 RH	519	#undef BSWAP
	520	#undef TGT_BE
	521	#undef TGT_LE
	522	#undef CPU_BE
	523	#undef CPU_LE
	524	#undef helper_le_ld_name
	525	#undef helper_be_ld_name
	526	#undef helper_le_lds_name
	527	#undef helper_be_lds_name
	528	#undef helper_le_st_name
	529	#undef helper_be_st_name
	530	#undef helper_te_ld_name
	531	#undef helper_te_st_name