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77fc6f5e LV |
1 | /* |
2 | * Generic intermediate code generation. | |
3 | * | |
4 | * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu> | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
7 | * See the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #ifndef EXEC__TRANSLATOR_H | |
11 | #define EXEC__TRANSLATOR_H | |
12 | ||
bb2e0039 LV |
13 | /* |
14 | * Include this header from a target-specific file, and add a | |
15 | * | |
16 | * DisasContextBase base; | |
17 | * | |
18 | * member in your target-specific DisasContext. | |
19 | */ | |
20 | ||
21 | ||
409c1a0b | 22 | #include "qemu/bswap.h" |
bb2e0039 | 23 | #include "exec/exec-all.h" |
409c1a0b EC |
24 | #include "exec/cpu_ldst.h" |
25 | #include "exec/plugin-gen.h" | |
f025692c | 26 | #include "exec/translate-all.h" |
bb2e0039 LV |
27 | #include "tcg/tcg.h" |
28 | ||
306c8721 RH |
29 | /** |
30 | * gen_intermediate_code | |
31 | * @cpu: cpu context | |
32 | * @tb: translation block | |
33 | * @max_insns: max number of instructions to translate | |
34 | * @pc: guest virtual program counter address | |
35 | * @host_pc: host physical program counter address | |
36 | * | |
37 | * This function must be provided by the target, which should create | |
38 | * the target-specific DisasContext, and then invoke translator_loop. | |
39 | */ | |
597f9b2d | 40 | void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, |
306c8721 | 41 | target_ulong pc, void *host_pc); |
bb2e0039 | 42 | |
77fc6f5e LV |
43 | /** |
44 | * DisasJumpType: | |
45 | * @DISAS_NEXT: Next instruction in program order. | |
46 | * @DISAS_TOO_MANY: Too many instructions translated. | |
47 | * @DISAS_NORETURN: Following code is dead. | |
48 | * @DISAS_TARGET_*: Start of target-specific conditions. | |
49 | * | |
50 | * What instruction to disassemble next. | |
51 | */ | |
52 | typedef enum DisasJumpType { | |
53 | DISAS_NEXT, | |
54 | DISAS_TOO_MANY, | |
55 | DISAS_NORETURN, | |
56 | DISAS_TARGET_0, | |
57 | DISAS_TARGET_1, | |
58 | DISAS_TARGET_2, | |
59 | DISAS_TARGET_3, | |
60 | DISAS_TARGET_4, | |
61 | DISAS_TARGET_5, | |
62 | DISAS_TARGET_6, | |
63 | DISAS_TARGET_7, | |
64 | DISAS_TARGET_8, | |
65 | DISAS_TARGET_9, | |
66 | DISAS_TARGET_10, | |
67 | DISAS_TARGET_11, | |
68 | } DisasJumpType; | |
69 | ||
bb2e0039 LV |
70 | /** |
71 | * DisasContextBase: | |
72 | * @tb: Translation block for this disassembly. | |
73 | * @pc_first: Address of first guest instruction in this TB. | |
74 | * @pc_next: Address of next guest instruction in this TB (current during | |
75 | * disassembly). | |
76 | * @is_jmp: What instruction to disassemble next. | |
77 | * @num_insns: Number of translated instructions (including current). | |
b542683d | 78 | * @max_insns: Maximum number of instructions to be translated in this TB. |
bb2e0039 LV |
79 | * @singlestep_enabled: "Hardware" single stepping enabled. |
80 | * | |
81 | * Architecture-agnostic disassembly context. | |
82 | */ | |
83 | typedef struct DisasContextBase { | |
50627f1b | 84 | TranslationBlock *tb; |
bb2e0039 LV |
85 | target_ulong pc_first; |
86 | target_ulong pc_next; | |
87 | DisasJumpType is_jmp; | |
b542683d EC |
88 | int num_insns; |
89 | int max_insns; | |
bb2e0039 | 90 | bool singlestep_enabled; |
50627f1b | 91 | void *host_addr[2]; |
bb2e0039 LV |
92 | } DisasContextBase; |
93 | ||
94 | /** | |
95 | * TranslatorOps: | |
96 | * @init_disas_context: | |
97 | * Initialize the target-specific portions of DisasContext struct. | |
98 | * The generic DisasContextBase has already been initialized. | |
bb2e0039 LV |
99 | * |
100 | * @tb_start: | |
101 | * Emit any code required before the start of the main loop, | |
102 | * after the generic gen_tb_start(). | |
103 | * | |
104 | * @insn_start: | |
105 | * Emit the tcg_gen_insn_start opcode. | |
106 | * | |
bb2e0039 LV |
107 | * @translate_insn: |
108 | * Disassemble one instruction and set db->pc_next for the start | |
109 | * of the following instruction. Set db->is_jmp as necessary to | |
110 | * terminate the main loop. | |
111 | * | |
112 | * @tb_stop: | |
113 | * Emit any opcodes required to exit the TB, based on db->is_jmp. | |
114 | * | |
115 | * @disas_log: | |
116 | * Print instruction disassembly to log. | |
117 | */ | |
118 | typedef struct TranslatorOps { | |
b542683d | 119 | void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); |
bb2e0039 LV |
120 | void (*tb_start)(DisasContextBase *db, CPUState *cpu); |
121 | void (*insn_start)(DisasContextBase *db, CPUState *cpu); | |
bb2e0039 LV |
122 | void (*translate_insn)(DisasContextBase *db, CPUState *cpu); |
123 | void (*tb_stop)(DisasContextBase *db, CPUState *cpu); | |
8eb806a7 | 124 | void (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f); |
bb2e0039 LV |
125 | } TranslatorOps; |
126 | ||
127 | /** | |
128 | * translator_loop: | |
bb2e0039 LV |
129 | * @cpu: Target vCPU. |
130 | * @tb: Translation block. | |
8b86d6d2 | 131 | * @max_insns: Maximum number of insns to translate. |
306c8721 RH |
132 | * @pc: guest virtual program counter address |
133 | * @host_pc: host physical program counter address | |
134 | * @ops: Target-specific operations. | |
135 | * @db: Disassembly context. | |
bb2e0039 LV |
136 | * |
137 | * Generic translator loop. | |
138 | * | |
139 | * Translation will stop in the following cases (in order): | |
140 | * - When is_jmp set by #TranslatorOps::breakpoint_check. | |
141 | * - set to DISAS_TOO_MANY exits after translating one more insn | |
142 | * - set to any other value than DISAS_NEXT exits immediately. | |
143 | * - When is_jmp set by #TranslatorOps::translate_insn. | |
144 | * - set to any value other than DISAS_NEXT exits immediately. | |
145 | * - When the TCG operation buffer is full. | |
146 | * - When single-stepping is enabled (system-wide or on the current vCPU). | |
147 | * - When too many instructions have been translated. | |
148 | */ | |
597f9b2d | 149 | void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, |
306c8721 RH |
150 | target_ulong pc, void *host_pc, |
151 | const TranslatorOps *ops, DisasContextBase *db); | |
bb2e0039 | 152 | |
d3a2a1d8 RH |
153 | /** |
154 | * translator_use_goto_tb | |
155 | * @db: Disassembly context | |
156 | * @dest: target pc of the goto | |
157 | * | |
158 | * Return true if goto_tb is allowed between the current TB | |
159 | * and the destination PC. | |
160 | */ | |
161 | bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); | |
162 | ||
409c1a0b EC |
163 | /* |
164 | * Translator Load Functions | |
165 | * | |
a6d456df RH |
166 | * These are intended to replace the direct usage of the cpu_ld*_code |
167 | * functions and are mandatory for front-ends that have been migrated | |
168 | * to the common translator_loop. These functions are only intended | |
169 | * to be called from the translation stage and should not be called | |
170 | * from helper functions. Those functions should be converted to encode | |
171 | * the relevant information at translation time. | |
409c1a0b EC |
172 | */ |
173 | ||
50627f1b RH |
174 | uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc); |
175 | uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc); | |
176 | uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc); | |
177 | uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc); | |
409c1a0b | 178 | |
50627f1b RH |
179 | static inline uint16_t |
180 | translator_lduw_swap(CPUArchState *env, DisasContextBase *db, | |
181 | abi_ptr pc, bool do_swap) | |
182 | { | |
183 | uint16_t ret = translator_lduw(env, db, pc); | |
184 | if (do_swap) { | |
185 | ret = bswap16(ret); | |
186 | } | |
187 | return ret; | |
188 | } | |
f025692c | 189 | |
50627f1b RH |
190 | static inline uint32_t |
191 | translator_ldl_swap(CPUArchState *env, DisasContextBase *db, | |
192 | abi_ptr pc, bool do_swap) | |
193 | { | |
194 | uint32_t ret = translator_ldl(env, db, pc); | |
195 | if (do_swap) { | |
196 | ret = bswap32(ret); | |
197 | } | |
198 | return ret; | |
199 | } | |
f025692c | 200 | |
50627f1b RH |
201 | static inline uint64_t |
202 | translator_ldq_swap(CPUArchState *env, DisasContextBase *db, | |
203 | abi_ptr pc, bool do_swap) | |
204 | { | |
205 | uint64_t ret = translator_ldq(env, db, pc); | |
206 | if (do_swap) { | |
207 | ret = bswap64(ret); | |
208 | } | |
209 | return ret; | |
210 | } | |
409c1a0b | 211 | |
9fa97e04 AB |
212 | /** |
213 | * translator_fake_ldb - fake instruction load | |
214 | * @insn8: byte of instruction | |
215 | * @pc: program counter of instruction | |
216 | * | |
217 | * This is a special case helper used where the instruction we are | |
218 | * about to translate comes from somewhere else (e.g. being | |
219 | * re-synthesised for s390x "ex"). It ensures we update other areas of | |
220 | * the translator with details of the executed instruction. | |
221 | */ | |
222 | ||
223 | static inline void translator_fake_ldb(uint8_t insn8, abi_ptr pc) | |
224 | { | |
225 | plugin_insn_append(pc, &insn8, sizeof(insn8)); | |
226 | } | |
227 | ||
228 | ||
f3b2b81b IL |
229 | /* |
230 | * Return whether addr is on the same page as where disassembly started. | |
231 | * Translators can use this to enforce the rule that only single-insn | |
232 | * translation blocks are allowed to cross page boundaries. | |
233 | */ | |
234 | static inline bool is_same_page(const DisasContextBase *db, target_ulong addr) | |
235 | { | |
236 | return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0; | |
237 | } | |
238 | ||
ea9cea93 | 239 | #endif /* EXEC__TRANSLATOR_H */ |