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virt_arm: acpi: reuse common build_fadt()
[mirror_qemu.git] / include / hw / acpi / acpi-defs.h
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72c194f7
MT		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11
12 * You should have received a copy of the GNU General Public License along
13 * with this program; if not, see <http://www.gnu.org/licenses/>.
14 */
15#ifndef QEMU_ACPI_DEFS_H
16#define QEMU_ACPI_DEFS_H
17
18enum {
19 ACPI_FADT_F_WBINVD,
20 ACPI_FADT_F_WBINVD_FLUSH,
21 ACPI_FADT_F_PROC_C1,
22 ACPI_FADT_F_P_LVL2_UP,
23 ACPI_FADT_F_PWR_BUTTON,
24 ACPI_FADT_F_SLP_BUTTON,
25 ACPI_FADT_F_FIX_RTC,
26 ACPI_FADT_F_RTC_S4,
27 ACPI_FADT_F_TMR_VAL_EXT,
28 ACPI_FADT_F_DCK_CAP,
29 ACPI_FADT_F_RESET_REG_SUP,
30 ACPI_FADT_F_SEALED_CASE,
31 ACPI_FADT_F_HEADLESS,
32 ACPI_FADT_F_CPU_SW_SLP,
33 ACPI_FADT_F_PCI_EXP_WAK,
34 ACPI_FADT_F_USE_PLATFORM_CLOCK,
35 ACPI_FADT_F_S4_RTC_STS_VALID,
36 ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
37 ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
38 ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
39 ACPI_FADT_F_HW_REDUCED_ACPI,
40 ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
41};
42
72c194f7
MT		 43struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */
44 uint64_t signature; /* ACPI signature, contains "RSD PTR " */
45 uint8_t checksum; /* To make sum of struct == 0 */
46 uint8_t oem_id [6]; /* OEM identification */
47 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
48 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
49 uint32_t length; /* XSDT Length in bytes including hdr */
50 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
51 uint8_t extended_checksum; /* Checksum of entire table */
52 uint8_t reserved [3]; /* Reserved field must be 0 */
53} QEMU_PACKED;
54typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor;
55
56/* Table structure from Linux kernel (the ACPI tables are under the
57 BSD license) */
58
59
60#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
61 uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
62 uint32_t length; /* Length of table, in bytes, including header */ \
63 uint8_t revision; /* ACPI Specification minor version # */ \
64 uint8_t checksum; /* To make sum of entire table == 0 */ \
65 uint8_t oem_id [6]; /* OEM identification */ \
66 uint8_t oem_table_id [8]; /* OEM table identification */ \
67 uint32_t oem_revision; /* OEM revision number */ \
68 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \
69 uint32_t asl_compiler_revision; /* ASL compiler revision number */
70
71
8b12e489
MT		 72/* ACPI common table header */
73struct AcpiTableHeader {
72c194f7
MT		 74 ACPI_TABLE_HEADER_DEF
75} QEMU_PACKED;
76typedef struct AcpiTableHeader AcpiTableHeader;
77
78/*
c2f7c0c3 79 * ACPI Fixed ACPI Description Table (FADT)
72c194f7 80 */
c2f7c0c3
SZ		 81#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \
82 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
83 uint32_t firmware_ctrl; /* Physical address of FACS */ \
84 uint32_t dsdt; /* Physical address of DSDT */ \
85 uint8_t model; /* System Interrupt Model */ \
86 uint8_t reserved1; /* Reserved */ \
87 uint16_t sci_int; /* System vector of SCI interrupt */ \
88 uint32_t smi_cmd; /* Port address of SMI command port */ \
89 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
90 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
91 /* Value to write to SMI CMD to enter S4BIOS state */ \
92 uint8_t S4bios_req; \
93 uint8_t reserved2; /* Reserved - must be zero */ \
94 /* Port address of Power Mgt 1a acpi_event Reg Blk */ \
95 uint32_t pm1a_evt_blk; \
96 /* Port address of Power Mgt 1b acpi_event Reg Blk */ \
97 uint32_t pm1b_evt_blk; \
98 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
99 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
100 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
101 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
102 /* Port addr of General Purpose acpi_event 0 Reg Blk */ \
103 uint32_t gpe0_blk; \
104 /* Port addr of General Purpose acpi_event 1 Reg Blk */ \
105 uint32_t gpe1_blk; \
106 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \
107 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \
108 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
109 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \
110 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
111 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
112 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \
113 uint8_t reserved3; /* Reserved */ \
114 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
115 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
116 uint16_t flush_size; /* Size of area read to flush caches */ \
117 uint16_t flush_stride; /* Stride used in flushing caches */ \
118 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \
119 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \
120 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
121 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
77af8a2b
PDJ		 122 uint8_t century; /* Index to century in RTC CMOS RAM */ \
123 /* IA-PC Boot Architecture Flags (see below for individual flags) */ \
124 uint16_t boot_flags; \
125 uint8_t reserved; /* Reserved, must be zero */ \
126 /* Miscellaneous flag bits (see below for individual flags) */ \
127 uint32_t flags; \
128 /* 64-bit address of the Reset register */ \
129 struct AcpiGenericAddress reset_register; \
130 /* Value to write to the reset_register port to reset the system */ \
131 uint8_t reset_value; \
132 /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */ \
133 uint16_t arm_boot_flags; \
134 uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ \
5ee85347
AB		 135 uint64_t x_facs; /* 64-bit physical address of FACS */ \
136 uint64_t x_dsdt; /* 64-bit physical address of DSDT */ \
77af8a2b
PDJ		 137 /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ \
138 struct AcpiGenericAddress xpm1a_event_block; \
139 /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ \
140 struct AcpiGenericAddress xpm1b_event_block; \
141 /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ \
142 struct AcpiGenericAddress xpm1a_control_block; \
143 /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ \
144 struct AcpiGenericAddress xpm1b_control_block; \
145 /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ \
146 struct AcpiGenericAddress xpm2_control_block; \
147 /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ \
148 struct AcpiGenericAddress xpm_timer_block; \
149 /* 64-bit Extended General Purpose Event 0 Reg Blk address */ \
150 struct AcpiGenericAddress xgpe0_block; \
151 /* 64-bit Extended General Purpose Event 1 Reg Blk address */ \
152 struct AcpiGenericAddress xgpe1_block; \
72c194f7 153
c2f7c0c3
SZ		 154struct AcpiGenericAddress {
155 uint8_t space_id; /* Address space where struct or register exists */
156 uint8_t bit_width; /* Size in bits of given register */
157 uint8_t bit_offset; /* Bit offset within the register */
b8e0f589
IM		 158 uint8_t access_width; /* ACPI 3.0: Minimum Access size (ACPI 3.0),
159 ACPI 2.0: Reserved, Table 5-1 */
c2f7c0c3
SZ		 160 uint64_t address; /* 64-bit address of struct or register */
161} QEMU_PACKED;
162
77af8a2b
PDJ		 163struct AcpiFadtDescriptorRev3 {
164 ACPI_FADT_COMMON_DEF
165} QEMU_PACKED;
166typedef struct AcpiFadtDescriptorRev3 AcpiFadtDescriptorRev3;
167
937d1b58
IM		 168typedef struct AcpiFadtData {
169 struct AcpiGenericAddress pm1a_cnt; /* PM1a_CNT_BLK */
170 struct AcpiGenericAddress pm1a_evt; /* PM1a_EVT_BLK */
171 struct AcpiGenericAddress pm_tmr; /* PM_TMR_BLK */
172 struct AcpiGenericAddress gpe0_blk; /* GPE0_BLK */
173 struct AcpiGenericAddress reset_reg; /* RESET_REG */
174 uint8_t reset_val; /* RESET_VALUE */
175 uint8_t rev; /* Revision */
176 uint32_t flags; /* Flags */
177 uint32_t smi_cmd; /* SMI_CMD */
178 uint16_t sci_int; /* SCI_INT */
179 uint8_t int_model; /* INT_MODEL */
180 uint8_t acpi_enable_cmd; /* ACPI_ENABLE */
181 uint8_t acpi_disable_cmd; /* ACPI_DISABLE */
182 uint8_t rtc_century; /* CENTURY */
183 uint16_t plvl2_lat; /* P_LVL2_LAT */
184 uint16_t plvl3_lat; /* P_LVL3_LAT */
dd1b2037
IM		 185 uint16_t arm_boot_arch; /* ARM_BOOT_ARCH */
186 uint8_t minor_ver; /* FADT Minor Version */
937d1b58
IM		 187
188 /*
189 * respective tables offsets within ACPI_BUILD_TABLE_FILE,
190 * NULL if table doesn't exist (in that case field's value
191 * won't be patched by linker and will be kept set to 0)
192 */
193 unsigned *facs_tbl_offset; /* FACS offset in */
194 unsigned *dsdt_tbl_offset;
195 unsigned *xdsdt_tbl_offset;
196} AcpiFadtData;
197
8c92c6a4
AJ		 198#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
199#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
c2f7c0c3 200
b8a0d75e
AJ		 201/*
202 * Serial Port Console Redirection Table (SPCR), Rev. 1.02
203 *
204 * For .interface_type see Debug Port Table 2 (DBG2) serial port
205 * subtypes in Table 3, Rev. May 22, 2012
206 */
207struct AcpiSerialPortConsoleRedirection {
208 ACPI_TABLE_HEADER_DEF
209 uint8_t interface_type;
210 uint8_t reserved1[3];
211 struct AcpiGenericAddress base_address;
212 uint8_t interrupt_types;
213 uint8_t irq;
214 uint32_t gsi;
215 uint8_t baud;
216 uint8_t parity;
217 uint8_t stopbits;
218 uint8_t flowctrl;
219 uint8_t term_type;
220 uint8_t reserved2;
221 uint16_t pci_device_id;
222 uint16_t pci_vendor_id;
223 uint8_t pci_bus;
224 uint8_t pci_slot;
225 uint8_t pci_func;
226 uint32_t pci_flags;
227 uint8_t pci_seg;
228 uint32_t reserved3;
229} QEMU_PACKED;
230typedef struct AcpiSerialPortConsoleRedirection
231 AcpiSerialPortConsoleRedirection;
232
72c194f7
MT		 233/*
234 * ACPI 1.0 Root System Description Table (RSDT)
235 */
8b12e489 236struct AcpiRsdtDescriptorRev1 {
72c194f7
MT		 237 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
238 uint32_t table_offset_entry[0]; /* Array of pointers to other */
239 /* ACPI tables */
240} QEMU_PACKED;
241typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
242
cb51ac2f
AB		 243/*
244 * ACPI 2.0 eXtended System Description Table (XSDT)
245 */
8b12e489 246struct AcpiXsdtDescriptorRev2 {
cb51ac2f
AB		 247 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
248 uint64_t table_offset_entry[0]; /* Array of pointers to other */
249 /* ACPI tables */
250} QEMU_PACKED;
251typedef struct AcpiXsdtDescriptorRev2 AcpiXsdtDescriptorRev2;
252
72c194f7
MT		 253/*
254 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
255 */
8b12e489 256struct AcpiFacsDescriptorRev1 {
72c194f7
MT		 257 uint32_t signature; /* ACPI Signature */
258 uint32_t length; /* Length of structure, in bytes */
259 uint32_t hardware_signature; /* Hardware configuration signature */
260 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
261 uint32_t global_lock; /* Global Lock */
262 uint32_t flags;
263 uint8_t resverved3 [40]; /* Reserved - must be zero */
264} QEMU_PACKED;
265typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
266
267/*
268 * Differentiated System Description Table (DSDT)
269 */
72c194f7
MT		 270
271/*
272 * MADT values and structures
273 */
274
275/* Values for MADT PCATCompat */
276
277#define ACPI_DUAL_PIC 0
278#define ACPI_MULTIPLE_APIC 1
279
280/* Master MADT */
281
8b12e489 282struct AcpiMultipleApicTable {
72c194f7
MT		 283 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
284 uint32_t local_apic_address; /* Physical address of local APIC */
285 uint32_t flags;
286} QEMU_PACKED;
287typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
288
289/* Values for Type in APIC sub-headers */
290
291#define ACPI_APIC_PROCESSOR 0
292#define ACPI_APIC_IO 1
293#define ACPI_APIC_XRUPT_OVERRIDE 2
294#define ACPI_APIC_NMI 3
295#define ACPI_APIC_LOCAL_NMI 4
296#define ACPI_APIC_ADDRESS_OVERRIDE 5
297#define ACPI_APIC_IO_SAPIC 6
298#define ACPI_APIC_LOCAL_SAPIC 7
299#define ACPI_APIC_XRUPT_SOURCE 8
982d06c5
SZ		 300#define ACPI_APIC_LOCAL_X2APIC 9
301#define ACPI_APIC_LOCAL_X2APIC_NMI 10
6e2ed65f 302#define ACPI_APIC_GENERIC_CPU_INTERFACE 11
982d06c5
SZ		 303#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
304#define ACPI_APIC_GENERIC_MSI_FRAME 13
305#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
1c2e4ea7
SZ		 306#define ACPI_APIC_GENERIC_TRANSLATOR 15
307#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
72c194f7
MT		 308
309/*
310 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
311 */
312#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
313 uint8_t type; \
314 uint8_t length;
315
316/* Sub-structures for MADT */
317
8b12e489 318struct AcpiMadtProcessorApic {
72c194f7
MT		 319 ACPI_SUB_HEADER_DEF
320 uint8_t processor_id; /* ACPI processor id */
321 uint8_t local_apic_id; /* Processor's local APIC id */
322 uint32_t flags;
323} QEMU_PACKED;
324typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
325
8b12e489 326struct AcpiMadtIoApic {
72c194f7
MT		 327 ACPI_SUB_HEADER_DEF
328 uint8_t io_apic_id; /* I/O APIC ID */
329 uint8_t reserved; /* Reserved - must be zero */
330 uint32_t address; /* APIC physical address */
331 uint32_t interrupt; /* Global system interrupt where INTI
332 * lines start */
333} QEMU_PACKED;
334typedef struct AcpiMadtIoApic AcpiMadtIoApic;
335
336struct AcpiMadtIntsrcovr {
337 ACPI_SUB_HEADER_DEF
338 uint8_t bus;
339 uint8_t source;
340 uint32_t gsi;
341 uint16_t flags;
342} QEMU_PACKED;
343typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
344
345struct AcpiMadtLocalNmi {
346 ACPI_SUB_HEADER_DEF
347 uint8_t processor_id; /* ACPI processor id */
348 uint16_t flags; /* MPS INTI flags */
349 uint8_t lint; /* Local APIC LINT# */
350} QEMU_PACKED;
351typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
352
e2c95939
IM		 353struct AcpiMadtProcessorX2Apic {
354 ACPI_SUB_HEADER_DEF
355 uint16_t reserved;
356 uint32_t x2apic_id; /* Processor's local x2APIC ID */
357 uint32_t flags;
358 uint32_t uid; /* Processor object _UID */
359} QEMU_PACKED;
360typedef struct AcpiMadtProcessorX2Apic AcpiMadtProcessorX2Apic;
361
362struct AcpiMadtLocalX2ApicNmi {
363 ACPI_SUB_HEADER_DEF
364 uint16_t flags; /* MPS INTI flags */
365 uint32_t uid; /* Processor object _UID */
366 uint8_t lint; /* Local APIC LINT# */
367 uint8_t reserved[3]; /* Local APIC LINT# */
368} QEMU_PACKED;
369typedef struct AcpiMadtLocalX2ApicNmi AcpiMadtLocalX2ApicNmi;
370
6e2ed65f 371struct AcpiMadtGenericCpuInterface {
982d06c5
SZ		 372 ACPI_SUB_HEADER_DEF
373 uint16_t reserved;
374 uint32_t cpu_interface_number;
375 uint32_t uid;
376 uint32_t flags;
377 uint32_t parking_version;
378 uint32_t performance_interrupt;
379 uint64_t parked_address;
380 uint64_t base_address;
381 uint64_t gicv_base_address;
382 uint64_t gich_base_address;
383 uint32_t vgic_interrupt;
384 uint64_t gicr_base_address;
385 uint64_t arm_mpidr;
386} QEMU_PACKED;
387
6e2ed65f
AJ		 388typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface;
389
390/* GICC CPU Interface Flags */
391#define ACPI_MADT_GICC_ENABLED 1
982d06c5
SZ		 392
393struct AcpiMadtGenericDistributor {
394 ACPI_SUB_HEADER_DEF
395 uint16_t reserved;
396 uint32_t gic_id;
397 uint64_t base_address;
398 uint32_t global_irq_base;
f06765a9
SZ		 399 /* ACPI 5.1 Errata 1228 Present GIC version in MADT table */
400 uint8_t version;
401 uint8_t reserved2[3];
982d06c5
SZ		 402} QEMU_PACKED;
403
404typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
405
ca793736
SZ		 406struct AcpiMadtGenericMsiFrame {
407 ACPI_SUB_HEADER_DEF
408 uint16_t reserved;
409 uint32_t gic_msi_frame_id;
410 uint64_t base_address;
411 uint32_t flags;
412 uint16_t spi_count;
413 uint16_t spi_base;
414} QEMU_PACKED;
415
416typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
417
b92ad394
PF		 418struct AcpiMadtGenericRedistributor {
419 ACPI_SUB_HEADER_DEF
420 uint16_t reserved;
421 uint64_t base_address;
422 uint32_t range_length;
423} QEMU_PACKED;
424
425typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor;
426
1c2e4ea7
SZ		 427struct AcpiMadtGenericTranslator {
428 ACPI_SUB_HEADER_DEF
429 uint16_t reserved;
430 uint32_t translation_id;
431 uint64_t base_address;
432 uint32_t reserved2;
433} QEMU_PACKED;
434
435typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
436
ee246400
SZ		 437/*
438 * Generic Timer Description Table (GTDT)
439 */
8dd845d3 440#define ACPI_GTDT_INTERRUPT_MODE_LEVEL (0 << 0)
aca4bbf4
AJ		 441#define ACPI_GTDT_INTERRUPT_MODE_EDGE (1 << 0)
442#define ACPI_GTDT_CAP_ALWAYS_ON (1 << 2)
ee246400
SZ		 443
444struct AcpiGenericTimerTable {
445 ACPI_TABLE_HEADER_DEF
446 uint64_t counter_block_addresss;
447 uint32_t reserved;
448 uint32_t secure_el1_interrupt;
449 uint32_t secure_el1_flags;
450 uint32_t non_secure_el1_interrupt;
451 uint32_t non_secure_el1_flags;
452 uint32_t virtual_timer_interrupt;
453 uint32_t virtual_timer_flags;
454 uint32_t non_secure_el2_interrupt;
455 uint32_t non_secure_el2_flags;
456 uint64_t counter_read_block_address;
457 uint32_t platform_timer_count;
458 uint32_t platform_timer_offset;
459} QEMU_PACKED;
460typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
461
72c194f7
MT		 462/*
463 * HPET Description Table
464 */
72c194f7
MT		 465struct Acpi20Hpet {
466 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
467 uint32_t timer_block_id;
b8e0f589 468 struct AcpiGenericAddress addr;
72c194f7
MT		 469 uint8_t hpet_number;
470 uint16_t min_tick;
471 uint8_t page_protect;
472} QEMU_PACKED;
473typedef struct Acpi20Hpet Acpi20Hpet;
474
475/*
476 * SRAT (NUMA topology description) table
477 */
478
8b12e489 479struct AcpiSystemResourceAffinityTable {
72c194f7
MT		 480 ACPI_TABLE_HEADER_DEF
481 uint32_t reserved1;
482 uint32_t reserved2[2];
483} QEMU_PACKED;
484typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
485
e6e400d5 486#define ACPI_SRAT_PROCESSOR_APIC 0
72c194f7 487#define ACPI_SRAT_MEMORY 1
e6e400d5
SZ		 488#define ACPI_SRAT_PROCESSOR_x2APIC 2
489#define ACPI_SRAT_PROCESSOR_GICC 3
72c194f7 490
8b12e489 491struct AcpiSratProcessorAffinity {
72c194f7
MT		 492 ACPI_SUB_HEADER_DEF
493 uint8_t proximity_lo;
494 uint8_t local_apic_id;
495 uint32_t flags;
496 uint8_t local_sapic_eid;
497 uint8_t proximity_hi[3];
498 uint32_t reserved;
499} QEMU_PACKED;
500typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
501
5eff33a2
IM		 502struct AcpiSratProcessorX2ApicAffinity {
503 ACPI_SUB_HEADER_DEF
504 uint16_t reserved;
505 uint32_t proximity_domain;
506 uint32_t x2apic_id;
507 uint32_t flags;
508 uint32_t clk_domain;
509 uint32_t reserved2;
510} QEMU_PACKED;
511typedef struct AcpiSratProcessorX2ApicAffinity AcpiSratProcessorX2ApicAffinity;
512
8b12e489 513struct AcpiSratMemoryAffinity {
72c194f7 514 ACPI_SUB_HEADER_DEF
ea9fcbd7 515 uint32_t proximity;
72c194f7
MT		 516 uint16_t reserved1;
517 uint64_t base_addr;
518 uint64_t range_length;
519 uint32_t reserved2;
520 uint32_t flags;
521 uint32_t reserved3[2];
522} QEMU_PACKED;
523typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
524
8b12e489 525struct AcpiSratProcessorGiccAffinity {
e6e400d5
SZ		 526 ACPI_SUB_HEADER_DEF
527 uint32_t proximity;
528 uint32_t acpi_processor_uid;
529 uint32_t flags;
530 uint32_t clock_domain;
531} QEMU_PACKED;
532
533typedef struct AcpiSratProcessorGiccAffinity AcpiSratProcessorGiccAffinity;
534
72c194f7
MT		 535/* PCI fw r3.0 MCFG table. */
536/* Subtable */
537struct AcpiMcfgAllocation {
538 uint64_t address; /* Base address, processor-relative */
539 uint16_t pci_segment; /* PCI segment group number */
540 uint8_t start_bus_number; /* Starting PCI Bus number */
541 uint8_t end_bus_number; /* Final PCI Bus number */
542 uint32_t reserved;
543} QEMU_PACKED;
544typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
545
72c194f7
MT		 546struct AcpiTableMcfg {
547 ACPI_TABLE_HEADER_DEF;
548 uint8_t reserved[8];
549 AcpiMcfgAllocation allocation[0];
550} QEMU_PACKED;
551typedef struct AcpiTableMcfg AcpiTableMcfg;
552
711b20b4
SB		 553/*
554 * TCPA Description Table
5cb18b3d
SB		 555 *
556 * Following Level 00, Rev 00.37 of specs:
557 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
711b20b4
SB		 558 */
559struct Acpi20Tcpa {
560 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
561 uint16_t platform_class;
562 uint32_t log_area_minimum_length;
563 uint64_t log_area_start_address;
564} QEMU_PACKED;
565typedef struct Acpi20Tcpa Acpi20Tcpa;
566
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SB		 567/*
568 * TPM2
569 *
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SB		 570 * Following Version 1.2, Revision 8 of specs:
571 * https://trustedcomputinggroup.org/tcg-acpi-specification/
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SB		 572 */
573struct Acpi20TPM2 {
574 ACPI_TABLE_HEADER_DEF
575 uint16_t platform_class;
576 uint16_t reserved;
577 uint64_t control_area_address;
578 uint32_t start_method;
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SB		 579 uint8_t start_method_params[12];
580 uint32_t log_area_minimum_length;
581 uint64_t log_area_start_address;
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SB		 582} QEMU_PACKED;
583typedef struct Acpi20TPM2 Acpi20TPM2;
584
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LT		 585/* DMAR - DMA Remapping table r2.2 */
586struct AcpiTableDmar {
587 ACPI_TABLE_HEADER_DEF
588 uint8_t host_address_width; /* Maximum DMA physical addressability */
589 uint8_t flags;
590 uint8_t reserved[10];
591} QEMU_PACKED;
592typedef struct AcpiTableDmar AcpiTableDmar;
593
594/* Masks for Flags field above */
595#define ACPI_DMAR_INTR_REMAP 1
596#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
597
598/* Values for sub-structure type for DMAR */
599enum {
600 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
601 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
602 ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
603 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
604 ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
605 ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
606};
607
608/*
609 * Sub-structures for DMAR
610 */
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PX		 611
612/* Device scope structure for DRHD. */
613struct AcpiDmarDeviceScope {
614 uint8_t entry_type;
615 uint8_t length;
616 uint16_t reserved;
617 uint8_t enumeration_id;
618 uint8_t bus;
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PX		 619 struct {
620 uint8_t device;
621 uint8_t function;
622 } path[0];
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PX		 623} QEMU_PACKED;
624typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope;
625
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LT		 626/* Type 0: Hardware Unit Definition */
627struct AcpiDmarHardwareUnit {
628 uint16_t type;
629 uint16_t length;
630 uint8_t flags;
631 uint8_t reserved;
632 uint16_t pci_segment; /* The PCI Segment associated with this unit */
633 uint64_t address; /* Base address of remapping hardware register-set */
cfc13df4 634 AcpiDmarDeviceScope scope[0];
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LT		 635} QEMU_PACKED;
636typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
637
bd2baacc
JW		 638/* Type 2: Root Port ATS Capability Reporting Structure */
639struct AcpiDmarRootPortATS {
640 uint16_t type;
641 uint16_t length;
642 uint8_t flags;
643 uint8_t reserved;
644 uint16_t pci_segment;
645 AcpiDmarDeviceScope scope[0];
646} QEMU_PACKED;
647typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS;
648
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LT		 649/* Masks for Flags field above */
650#define ACPI_DMAR_INCLUDE_PCI_ALL 1
bd2baacc 651#define ACPI_DMAR_ATSR_ALL_PORTS 1
d4eb9119 652
16fc326a
PM		 653/*
654 * Input Output Remapping Table (IORT)
655 * Conforms to "IO Remapping Table System Software on ARM Platforms",
656 * Document number: ARM DEN 0049B, October 2015
657 */
658
659struct AcpiIortTable {
660 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
661 uint32_t node_count;
662 uint32_t node_offset;
663 uint32_t reserved;
664} QEMU_PACKED;
665typedef struct AcpiIortTable AcpiIortTable;
666
667/*
668 * IORT node types
669 */
670
671#define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \
672 uint8_t type; \
673 uint16_t length; \
674 uint8_t revision; \
675 uint32_t reserved; \
676 uint32_t mapping_count; \
677 uint32_t mapping_offset;
678
679/* Values for node Type above */
680enum {
681 ACPI_IORT_NODE_ITS_GROUP = 0x00,
682 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
683 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
684 ACPI_IORT_NODE_SMMU = 0x03,
685 ACPI_IORT_NODE_SMMU_V3 = 0x04
686};
687
688struct AcpiIortIdMapping {
689 uint32_t input_base;
690 uint32_t id_count;
691 uint32_t output_base;
692 uint32_t output_reference;
693 uint32_t flags;
694} QEMU_PACKED;
695typedef struct AcpiIortIdMapping AcpiIortIdMapping;
696
697struct AcpiIortMemoryAccess {
698 uint32_t cache_coherency;
699 uint8_t hints;
700 uint16_t reserved;
701 uint8_t memory_flags;
702} QEMU_PACKED;
703typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess;
704
705struct AcpiIortItsGroup {
706 ACPI_IORT_NODE_HEADER_DEF
707 uint32_t its_count;
708 uint32_t identifiers[0];
709} QEMU_PACKED;
710typedef struct AcpiIortItsGroup AcpiIortItsGroup;
711
712struct AcpiIortRC {
713 ACPI_IORT_NODE_HEADER_DEF
714 AcpiIortMemoryAccess memory_properties;
715 uint32_t ats_attribute;
716 uint32_t pci_segment_number;
717 AcpiIortIdMapping id_mapping_array[0];
718} QEMU_PACKED;
719typedef struct AcpiIortRC AcpiIortRC;
720
72c194f7 721#endif
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