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740dafc0 NL |
1 | /* |
2 | * Allwinner H3 System on Chip emulation | |
3 | * | |
4 | * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 | |
22 | * processor cores. Features and specifications include DDR2/DDR3 memory, | |
23 | * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and | |
24 | * various I/O modules. | |
25 | * | |
26 | * This implementation is based on the following datasheet: | |
27 | * | |
28 | * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf | |
29 | * | |
30 | * The latest datasheet and more info can be found on the Linux Sunxi wiki: | |
31 | * | |
32 | * https://linux-sunxi.org/H3 | |
33 | */ | |
34 | ||
35 | #ifndef HW_ARM_ALLWINNER_H3_H | |
36 | #define HW_ARM_ALLWINNER_H3_H | |
37 | ||
38 | #include "qom/object.h" | |
39 | #include "hw/arm/boot.h" | |
40 | #include "hw/timer/allwinner-a10-pit.h" | |
41 | #include "hw/intc/arm_gic.h" | |
fef06c8b | 42 | #include "hw/misc/allwinner-h3-ccu.h" |
d26af5de | 43 | #include "hw/misc/allwinner-cpucfg.h" |
b71d0385 | 44 | #include "hw/misc/allwinner-h3-dramc.h" |
7e83c9dd | 45 | #include "hw/misc/allwinner-h3-sysctrl.h" |
6556617c | 46 | #include "hw/misc/allwinner-sid.h" |
82e48382 | 47 | #include "hw/sd/allwinner-sdhost.h" |
29d08975 | 48 | #include "hw/net/allwinner-sun8i-emac.h" |
a9ad9e73 | 49 | #include "hw/rtc/allwinner-rtc.h" |
740dafc0 | 50 | #include "target/arm/cpu.h" |
a80beb16 | 51 | #include "sysemu/block-backend.h" |
740dafc0 NL |
52 | |
53 | /** | |
54 | * Allwinner H3 device list | |
55 | * | |
56 | * This enumeration is can be used refer to a particular device in the | |
57 | * Allwinner H3 SoC. For example, the physical memory base address for | |
58 | * each device can be found in the AwH3State object in the memmap member | |
59 | * using the device enum value as index. | |
60 | * | |
61 | * @see AwH3State | |
62 | */ | |
63 | enum { | |
4af44e1e EH |
64 | AW_H3_DEV_SRAM_A1, |
65 | AW_H3_DEV_SRAM_A2, | |
66 | AW_H3_DEV_SRAM_C, | |
67 | AW_H3_DEV_SYSCTRL, | |
68 | AW_H3_DEV_MMC0, | |
69 | AW_H3_DEV_SID, | |
70 | AW_H3_DEV_EHCI0, | |
71 | AW_H3_DEV_OHCI0, | |
72 | AW_H3_DEV_EHCI1, | |
73 | AW_H3_DEV_OHCI1, | |
74 | AW_H3_DEV_EHCI2, | |
75 | AW_H3_DEV_OHCI2, | |
76 | AW_H3_DEV_EHCI3, | |
77 | AW_H3_DEV_OHCI3, | |
78 | AW_H3_DEV_CCU, | |
79 | AW_H3_DEV_PIT, | |
80 | AW_H3_DEV_UART0, | |
81 | AW_H3_DEV_UART1, | |
82 | AW_H3_DEV_UART2, | |
83 | AW_H3_DEV_UART3, | |
84 | AW_H3_DEV_EMAC, | |
85 | AW_H3_DEV_DRAMCOM, | |
86 | AW_H3_DEV_DRAMCTL, | |
87 | AW_H3_DEV_DRAMPHY, | |
88 | AW_H3_DEV_GIC_DIST, | |
89 | AW_H3_DEV_GIC_CPU, | |
90 | AW_H3_DEV_GIC_HYP, | |
91 | AW_H3_DEV_GIC_VCPU, | |
92 | AW_H3_DEV_RTC, | |
93 | AW_H3_DEV_CPUCFG, | |
94 | AW_H3_DEV_SDRAM | |
740dafc0 NL |
95 | }; |
96 | ||
97 | /** Total number of CPU cores in the H3 SoC */ | |
98 | #define AW_H3_NUM_CPUS (4) | |
99 | ||
100 | /** | |
101 | * Allwinner H3 object model | |
102 | * @{ | |
103 | */ | |
104 | ||
105 | /** Object type for the Allwinner H3 SoC */ | |
106 | #define TYPE_AW_H3 "allwinner-h3" | |
107 | ||
108 | /** Convert input object to Allwinner H3 state object */ | |
db1015e9 | 109 | typedef struct AwH3State AwH3State; |
8110fa1d EH |
110 | DECLARE_INSTANCE_CHECKER(AwH3State, AW_H3, |
111 | TYPE_AW_H3) | |
740dafc0 NL |
112 | |
113 | /** @} */ | |
114 | ||
115 | /** | |
116 | * Allwinner H3 object | |
117 | * | |
118 | * This struct contains the state of all the devices | |
119 | * which are currently emulated by the H3 SoC code. | |
120 | */ | |
db1015e9 | 121 | struct AwH3State { |
740dafc0 NL |
122 | /*< private >*/ |
123 | DeviceState parent_obj; | |
124 | /*< public >*/ | |
125 | ||
126 | ARMCPU cpus[AW_H3_NUM_CPUS]; | |
127 | const hwaddr *memmap; | |
128 | AwA10PITState timer; | |
fef06c8b | 129 | AwH3ClockCtlState ccu; |
d26af5de | 130 | AwCpuCfgState cpucfg; |
b71d0385 | 131 | AwH3DramCtlState dramc; |
7e83c9dd | 132 | AwH3SysCtrlState sysctrl; |
6556617c | 133 | AwSidState sid; |
82e48382 | 134 | AwSdHostState mmc0; |
29d08975 | 135 | AwSun8iEmacState emac; |
a9ad9e73 | 136 | AwRtcState rtc; |
740dafc0 NL |
137 | GICState gic; |
138 | MemoryRegion sram_a1; | |
139 | MemoryRegion sram_a2; | |
140 | MemoryRegion sram_c; | |
db1015e9 | 141 | }; |
740dafc0 | 142 | |
a80beb16 NL |
143 | /** |
144 | * Emulate Boot ROM firmware setup functionality. | |
145 | * | |
146 | * A real Allwinner H3 SoC contains a Boot ROM | |
147 | * which is the first code that runs right after | |
148 | * the SoC is powered on. The Boot ROM is responsible | |
149 | * for loading user code (e.g. a bootloader) from any | |
150 | * of the supported external devices and writing the | |
151 | * downloaded code to internal SRAM. After loading the SoC | |
152 | * begins executing the code written to SRAM. | |
153 | * | |
154 | * This function emulates the Boot ROM by copying 32 KiB | |
155 | * of data from the given block device and writes it to | |
156 | * the start of the first internal SRAM memory. | |
157 | * | |
158 | * @s: Allwinner H3 state object pointer | |
159 | * @blk: Block backend device object pointer | |
160 | */ | |
161 | void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk); | |
162 | ||
740dafc0 | 163 | #endif /* HW_ARM_ALLWINNER_H3_H */ |