projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 43e3346e | 1 | /* |
| ff90606f | 2 | * ASPEED SoC family |
| 43e3346e AJ |
3 | * |
| 4 | * Andrew Jeffery <andrew@aj.id.au> | |
| 5 | * | |
| 6 | * Copyright 2016 IBM Corp. | |
| 7 | * | |
| 8 | * This code is licensed under the GPL version 2 or later. See | |
| 9 | * the COPYING file in the top-level directory. | |
| 10 | */ | |
| 11 | ||
| ff90606f CLG |
12 | #ifndef ASPEED_SOC_H |
| 13 | #define ASPEED_SOC_H | |
| 43e3346e AJ |
14 | |
| 15 | #include "hw/arm/arm.h" | |
| 16 | #include "hw/intc/aspeed_vic.h" | |
| 334973bb | 17 | #include "hw/misc/aspeed_scu.h" |
| c2da8a8b | 18 | #include "hw/misc/aspeed_sdmc.h" |
| 43e3346e | 19 | #include "hw/timer/aspeed_timer.h" |
| 16020011 | 20 | #include "hw/i2c/aspeed_i2c.h" |
| 7c1c69bc | 21 | #include "hw/ssi/aspeed_smc.h" |
| 013befe1 | 22 | #include "hw/watchdog/wdt_aspeed.h" |
| ea337c65 | 23 | #include "hw/net/ftgmac100.h" |
| 43e3346e | 24 | |
| dbcabeeb | 25 | #define ASPEED_SPIS_NUM 2 |
| f986ee1d | 26 | #define ASPEED_WDTS_NUM 3 |
| dbcabeeb | 27 | |
| ff90606f | 28 | typedef struct AspeedSoCState { |
| 43e3346e AJ |
29 | /*< private >*/ |
| 30 | DeviceState parent; | |
| 31 | ||
| 32 | /*< public >*/ | |
| 2d105bd6 | 33 | ARMCPU cpu; |
| 74af4eec | 34 | MemoryRegion sram; |
| 43e3346e AJ |
35 | AspeedVICState vic; |
| 36 | AspeedTimerCtrlState timerctrl; | |
| 16020011 | 37 | AspeedI2CState i2c; |
| 334973bb | 38 | AspeedSCUState scu; |
| 0e5803df | 39 | AspeedSMCState fmc; |
| dbcabeeb | 40 | AspeedSMCState spi[ASPEED_SPIS_NUM]; |
| c2da8a8b | 41 | AspeedSDMCState sdmc; |
| f986ee1d | 42 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; |
| ea337c65 | 43 | FTGMAC100State ftgmac100; |
| ff90606f | 44 | } AspeedSoCState; |
| 43e3346e | 45 | |
| ff90606f CLG |
46 | #define TYPE_ASPEED_SOC "aspeed-soc" |
| 47 | #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) | |
| 43e3346e | 48 | |
| b033271f CLG |
49 | typedef struct AspeedSoCInfo { |
| 50 | const char *name; | |
| ba1ba5cc | 51 | const char *cpu_type; |
| b033271f CLG |
52 | uint32_t silicon_rev; |
| 53 | hwaddr sdram_base; | |
| 74af4eec | 54 | uint64_t sram_size; |
| dbcabeeb CLG |
55 | int spis_num; |
| 56 | const hwaddr *spi_bases; | |
| 6dc52326 CLG |
57 | const char *fmc_typename; |
| 58 | const char **spi_typename; | |
| f986ee1d | 59 | int wdts_num; |
| b033271f CLG |
60 | } AspeedSoCInfo; |
| 61 | ||
| 62 | typedef struct AspeedSoCClass { | |
| 63 | DeviceClass parent_class; | |
| 64 | AspeedSoCInfo *info; | |
| 65 | } AspeedSoCClass; | |
| 66 | ||
| 67 | #define ASPEED_SOC_CLASS(klass) \ | |
| 68 | OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) | |
| 69 | #define ASPEED_SOC_GET_CLASS(obj) \ | |
| 70 | OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) | |
| 43e3346e | 71 | |
| ff90606f | 72 | #endif /* ASPEED_SOC_H */ |