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hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500
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43e3346e 1/*
ff90606f 2 * ASPEED SoC family
43e3346e
AJ
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
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12#ifndef ASPEED_SOC_H
13#define ASPEED_SOC_H
43e3346e 14
43e3346e 15#include "hw/intc/aspeed_vic.h"
334973bb 16#include "hw/misc/aspeed_scu.h"
c2da8a8b 17#include "hw/misc/aspeed_sdmc.h"
118c82e7 18#include "hw/misc/aspeed_xdma.h"
43e3346e 19#include "hw/timer/aspeed_timer.h"
75fb4577 20#include "hw/timer/aspeed_rtc.h"
16020011 21#include "hw/i2c/aspeed_i2c.h"
7c1c69bc 22#include "hw/ssi/aspeed_smc.h"
013befe1 23#include "hw/watchdog/wdt_aspeed.h"
ea337c65 24#include "hw/net/ftgmac100.h"
ec150c7e 25#include "target/arm/cpu.h"
43e3346e 26
dbcabeeb 27#define ASPEED_SPIS_NUM 2
f986ee1d 28#define ASPEED_WDTS_NUM 3
ece09bee 29#define ASPEED_CPUS_NUM 2
67340990 30#define ASPEED_MACS_NUM 2
dbcabeeb 31
ff90606f 32typedef struct AspeedSoCState {
43e3346e
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33 /*< private >*/
34 DeviceState parent;
35
36 /*< public >*/
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37 ARMCPU cpu[ASPEED_CPUS_NUM];
38 uint32_t num_cpus;
74af4eec 39 MemoryRegion sram;
43e3346e 40 AspeedVICState vic;
75fb4577 41 AspeedRtcState rtc;
43e3346e 42 AspeedTimerCtrlState timerctrl;
16020011 43 AspeedI2CState i2c;
334973bb 44 AspeedSCUState scu;
118c82e7 45 AspeedXDMAState xdma;
0e5803df 46 AspeedSMCState fmc;
dbcabeeb 47 AspeedSMCState spi[ASPEED_SPIS_NUM];
c2da8a8b 48 AspeedSDMCState sdmc;
f986ee1d 49 AspeedWDTState wdt[ASPEED_WDTS_NUM];
67340990 50 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
ff90606f 51} AspeedSoCState;
43e3346e 52
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53#define TYPE_ASPEED_SOC "aspeed-soc"
54#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
43e3346e 55
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56typedef struct AspeedSoCInfo {
57 const char *name;
ba1ba5cc 58 const char *cpu_type;
b033271f 59 uint32_t silicon_rev;
74af4eec 60 uint64_t sram_size;
dbcabeeb 61 int spis_num;
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62 const char *fmc_typename;
63 const char **spi_typename;
f986ee1d 64 int wdts_num;
b456b113 65 const int *irqmap;
d783d1fe 66 const hwaddr *memmap;
ece09bee 67 uint32_t num_cpus;
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68} AspeedSoCInfo;
69
70typedef struct AspeedSoCClass {
71 DeviceClass parent_class;
72 AspeedSoCInfo *info;
73} AspeedSoCClass;
74
75#define ASPEED_SOC_CLASS(klass) \
76 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
77#define ASPEED_SOC_GET_CLASS(obj) \
78 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
43e3346e 79
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80enum {
81 ASPEED_IOMEM,
82 ASPEED_UART1,
83 ASPEED_UART2,
84 ASPEED_UART3,
85 ASPEED_UART4,
86 ASPEED_UART5,
87 ASPEED_VUART,
88 ASPEED_FMC,
89 ASPEED_SPI1,
90 ASPEED_SPI2,
91 ASPEED_VIC,
92 ASPEED_SDMC,
93 ASPEED_SCU,
94 ASPEED_ADC,
95 ASPEED_SRAM,
96 ASPEED_GPIO,
97 ASPEED_RTC,
98 ASPEED_TIMER1,
99 ASPEED_TIMER2,
100 ASPEED_TIMER3,
101 ASPEED_TIMER4,
102 ASPEED_TIMER5,
103 ASPEED_TIMER6,
104 ASPEED_TIMER7,
105 ASPEED_TIMER8,
106 ASPEED_WDT,
107 ASPEED_PWM,
108 ASPEED_LPC,
109 ASPEED_IBT,
110 ASPEED_I2C,
111 ASPEED_ETH1,
112 ASPEED_ETH2,
d783d1fe 113 ASPEED_SDRAM,
118c82e7 114 ASPEED_XDMA,
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115};
116
ff90606f 117#endif /* ASPEED_SOC_H */