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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
ff90606f CLG |
12 | #ifndef ASPEED_SOC_H |
13 | #define ASPEED_SOC_H | |
43e3346e | 14 | |
f25c0ae1 | 15 | #include "hw/cpu/a15mpcore.h" |
43e3346e | 16 | #include "hw/intc/aspeed_vic.h" |
334973bb | 17 | #include "hw/misc/aspeed_scu.h" |
c2da8a8b | 18 | #include "hw/misc/aspeed_sdmc.h" |
118c82e7 | 19 | #include "hw/misc/aspeed_xdma.h" |
43e3346e | 20 | #include "hw/timer/aspeed_timer.h" |
75fb4577 | 21 | #include "hw/timer/aspeed_rtc.h" |
16020011 | 22 | #include "hw/i2c/aspeed_i2c.h" |
7c1c69bc | 23 | #include "hw/ssi/aspeed_smc.h" |
013befe1 | 24 | #include "hw/watchdog/wdt_aspeed.h" |
ea337c65 | 25 | #include "hw/net/ftgmac100.h" |
ec150c7e | 26 | #include "target/arm/cpu.h" |
fdcc7c06 | 27 | #include "hw/gpio/aspeed_gpio.h" |
2bea128c | 28 | #include "hw/sd/aspeed_sdhci.h" |
43e3346e | 29 | |
dbcabeeb | 30 | #define ASPEED_SPIS_NUM 2 |
6b2b2a70 | 31 | #define ASPEED_WDTS_NUM 4 |
ece09bee | 32 | #define ASPEED_CPUS_NUM 2 |
d300db02 | 33 | #define ASPEED_MACS_NUM 4 |
dbcabeeb | 34 | |
ff90606f | 35 | typedef struct AspeedSoCState { |
43e3346e AJ |
36 | /*< private >*/ |
37 | DeviceState parent; | |
38 | ||
39 | /*< public >*/ | |
ece09bee CLG |
40 | ARMCPU cpu[ASPEED_CPUS_NUM]; |
41 | uint32_t num_cpus; | |
f25c0ae1 | 42 | A15MPPrivState a7mpcore; |
74af4eec | 43 | MemoryRegion sram; |
43e3346e | 44 | AspeedVICState vic; |
75fb4577 | 45 | AspeedRtcState rtc; |
43e3346e | 46 | AspeedTimerCtrlState timerctrl; |
16020011 | 47 | AspeedI2CState i2c; |
334973bb | 48 | AspeedSCUState scu; |
118c82e7 | 49 | AspeedXDMAState xdma; |
0e5803df | 50 | AspeedSMCState fmc; |
dbcabeeb | 51 | AspeedSMCState spi[ASPEED_SPIS_NUM]; |
c2da8a8b | 52 | AspeedSDMCState sdmc; |
f986ee1d | 53 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; |
67340990 | 54 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; |
289251b0 | 55 | AspeedMiiState mii[ASPEED_MACS_NUM]; |
fdcc7c06 | 56 | AspeedGPIOState gpio; |
f25c0ae1 | 57 | AspeedGPIOState gpio_1_8v; |
2bea128c | 58 | AspeedSDHCIState sdhci; |
ff90606f | 59 | } AspeedSoCState; |
43e3346e | 60 | |
ff90606f CLG |
61 | #define TYPE_ASPEED_SOC "aspeed-soc" |
62 | #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) | |
43e3346e | 63 | |
54ecafb7 CLG |
64 | typedef struct AspeedSoCClass { |
65 | DeviceClass parent_class; | |
66 | ||
b033271f | 67 | const char *name; |
ba1ba5cc | 68 | const char *cpu_type; |
b033271f | 69 | uint32_t silicon_rev; |
74af4eec | 70 | uint64_t sram_size; |
dbcabeeb | 71 | int spis_num; |
f986ee1d | 72 | int wdts_num; |
d300db02 | 73 | int macs_num; |
b456b113 | 74 | const int *irqmap; |
d783d1fe | 75 | const hwaddr *memmap; |
ece09bee | 76 | uint32_t num_cpus; |
b033271f CLG |
77 | } AspeedSoCClass; |
78 | ||
79 | #define ASPEED_SOC_CLASS(klass) \ | |
80 | OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) | |
81 | #define ASPEED_SOC_GET_CLASS(obj) \ | |
82 | OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) | |
43e3346e | 83 | |
b456b113 CLG |
84 | enum { |
85 | ASPEED_IOMEM, | |
86 | ASPEED_UART1, | |
87 | ASPEED_UART2, | |
88 | ASPEED_UART3, | |
89 | ASPEED_UART4, | |
90 | ASPEED_UART5, | |
91 | ASPEED_VUART, | |
92 | ASPEED_FMC, | |
93 | ASPEED_SPI1, | |
94 | ASPEED_SPI2, | |
95 | ASPEED_VIC, | |
96 | ASPEED_SDMC, | |
97 | ASPEED_SCU, | |
98 | ASPEED_ADC, | |
514bcf6f | 99 | ASPEED_VIDEO, |
b456b113 | 100 | ASPEED_SRAM, |
2bea128c | 101 | ASPEED_SDHCI, |
b456b113 | 102 | ASPEED_GPIO, |
f25c0ae1 | 103 | ASPEED_GPIO_1_8V, |
b456b113 CLG |
104 | ASPEED_RTC, |
105 | ASPEED_TIMER1, | |
106 | ASPEED_TIMER2, | |
107 | ASPEED_TIMER3, | |
108 | ASPEED_TIMER4, | |
109 | ASPEED_TIMER5, | |
110 | ASPEED_TIMER6, | |
111 | ASPEED_TIMER7, | |
112 | ASPEED_TIMER8, | |
113 | ASPEED_WDT, | |
114 | ASPEED_PWM, | |
115 | ASPEED_LPC, | |
116 | ASPEED_IBT, | |
117 | ASPEED_I2C, | |
118 | ASPEED_ETH1, | |
119 | ASPEED_ETH2, | |
d300db02 JS |
120 | ASPEED_ETH3, |
121 | ASPEED_ETH4, | |
289251b0 CLG |
122 | ASPEED_MII1, |
123 | ASPEED_MII2, | |
124 | ASPEED_MII3, | |
125 | ASPEED_MII4, | |
d783d1fe | 126 | ASPEED_SDRAM, |
118c82e7 | 127 | ASPEED_XDMA, |
b456b113 CLG |
128 | }; |
129 | ||
ff90606f | 130 | #endif /* ASPEED_SOC_H */ |