projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 43e3346e | 1 | /* |
| ff90606f | 2 | * ASPEED SoC family |
| 43e3346e AJ |
3 | * |
| 4 | * Andrew Jeffery <andrew@aj.id.au> | |
| 5 | * | |
| 6 | * Copyright 2016 IBM Corp. | |
| 7 | * | |
| 8 | * This code is licensed under the GPL version 2 or later. See | |
| 9 | * the COPYING file in the top-level directory. | |
| 10 | */ | |
| 11 | ||
| ff90606f CLG |
12 | #ifndef ASPEED_SOC_H |
| 13 | #define ASPEED_SOC_H | |
| 43e3346e | 14 | |
| 43e3346e | 15 | #include "hw/intc/aspeed_vic.h" |
| 334973bb | 16 | #include "hw/misc/aspeed_scu.h" |
| c2da8a8b | 17 | #include "hw/misc/aspeed_sdmc.h" |
| 43e3346e | 18 | #include "hw/timer/aspeed_timer.h" |
| 16020011 | 19 | #include "hw/i2c/aspeed_i2c.h" |
| 7c1c69bc | 20 | #include "hw/ssi/aspeed_smc.h" |
| 013befe1 | 21 | #include "hw/watchdog/wdt_aspeed.h" |
| ea337c65 | 22 | #include "hw/net/ftgmac100.h" |
| 43e3346e | 23 | |
| dbcabeeb | 24 | #define ASPEED_SPIS_NUM 2 |
| f986ee1d | 25 | #define ASPEED_WDTS_NUM 3 |
| dbcabeeb | 26 | |
| ff90606f | 27 | typedef struct AspeedSoCState { |
| 43e3346e AJ |
28 | /*< private >*/ |
| 29 | DeviceState parent; | |
| 30 | ||
| 31 | /*< public >*/ | |
| 2d105bd6 | 32 | ARMCPU cpu; |
| 74af4eec | 33 | MemoryRegion sram; |
| 43e3346e AJ |
34 | AspeedVICState vic; |
| 35 | AspeedTimerCtrlState timerctrl; | |
| 16020011 | 36 | AspeedI2CState i2c; |
| 334973bb | 37 | AspeedSCUState scu; |
| 0e5803df | 38 | AspeedSMCState fmc; |
| dbcabeeb | 39 | AspeedSMCState spi[ASPEED_SPIS_NUM]; |
| c2da8a8b | 40 | AspeedSDMCState sdmc; |
| f986ee1d | 41 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; |
| ea337c65 | 42 | FTGMAC100State ftgmac100; |
| ff90606f | 43 | } AspeedSoCState; |
| 43e3346e | 44 | |
| ff90606f CLG |
45 | #define TYPE_ASPEED_SOC "aspeed-soc" |
| 46 | #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) | |
| 43e3346e | 47 | |
| b033271f CLG |
48 | typedef struct AspeedSoCInfo { |
| 49 | const char *name; | |
| ba1ba5cc | 50 | const char *cpu_type; |
| b033271f | 51 | uint32_t silicon_rev; |
| 74af4eec | 52 | uint64_t sram_size; |
| dbcabeeb | 53 | int spis_num; |
| 6dc52326 CLG |
54 | const char *fmc_typename; |
| 55 | const char **spi_typename; | |
| f986ee1d | 56 | int wdts_num; |
| b456b113 | 57 | const int *irqmap; |
| d783d1fe | 58 | const hwaddr *memmap; |
| b033271f CLG |
59 | } AspeedSoCInfo; |
| 60 | ||
| 61 | typedef struct AspeedSoCClass { | |
| 62 | DeviceClass parent_class; | |
| 63 | AspeedSoCInfo *info; | |
| 64 | } AspeedSoCClass; | |
| 65 | ||
| 66 | #define ASPEED_SOC_CLASS(klass) \ | |
| 67 | OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) | |
| 68 | #define ASPEED_SOC_GET_CLASS(obj) \ | |
| 69 | OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) | |
| 43e3346e | 70 | |
| b456b113 CLG |
71 | enum { |
| 72 | ASPEED_IOMEM, | |
| 73 | ASPEED_UART1, | |
| 74 | ASPEED_UART2, | |
| 75 | ASPEED_UART3, | |
| 76 | ASPEED_UART4, | |
| 77 | ASPEED_UART5, | |
| 78 | ASPEED_VUART, | |
| 79 | ASPEED_FMC, | |
| 80 | ASPEED_SPI1, | |
| 81 | ASPEED_SPI2, | |
| 82 | ASPEED_VIC, | |
| 83 | ASPEED_SDMC, | |
| 84 | ASPEED_SCU, | |
| 85 | ASPEED_ADC, | |
| 86 | ASPEED_SRAM, | |
| 87 | ASPEED_GPIO, | |
| 88 | ASPEED_RTC, | |
| 89 | ASPEED_TIMER1, | |
| 90 | ASPEED_TIMER2, | |
| 91 | ASPEED_TIMER3, | |
| 92 | ASPEED_TIMER4, | |
| 93 | ASPEED_TIMER5, | |
| 94 | ASPEED_TIMER6, | |
| 95 | ASPEED_TIMER7, | |
| 96 | ASPEED_TIMER8, | |
| 97 | ASPEED_WDT, | |
| 98 | ASPEED_PWM, | |
| 99 | ASPEED_LPC, | |
| 100 | ASPEED_IBT, | |
| 101 | ASPEED_I2C, | |
| 102 | ASPEED_ETH1, | |
| 103 | ASPEED_ETH2, | |
| d783d1fe | 104 | ASPEED_SDRAM, |
| b456b113 CLG |
105 | }; |
| 106 | ||
| ff90606f | 107 | #endif /* ASPEED_SOC_H */ |