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1/*
2 * Microsemi Smartfusion2 SoC
3 *
4 * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#ifndef HW_ARM_MSF2_SOC_H
26#define HW_ARM_MSF2_SOC_H
27
28#include "hw/arm/armv7m.h"
29#include "hw/timer/mss-timer.h"
30#include "hw/misc/msf2-sysreg.h"
31#include "hw/ssi/mss-spi.h"
05b7374a 32#include "hw/net/msf2-emac.h"
9bfaf375 33#include "hw/clock.h"
db1015e9 34#include "qom/object.h"
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35
36#define TYPE_MSF2_SOC "msf2-soc"
8063396b 37OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC)
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38
39#define MSF2_NUM_SPIS 2
40#define MSF2_NUM_UARTS 2
41
42/*
43 * System timer consists of two programmable 32-bit
44 * decrementing counters that generate individual interrupts to
45 * the Cortex-M3 processor
46 */
47#define MSF2_NUM_TIMERS 2
48
db1015e9 49struct MSF2State {
ebc1fbb4 50 SysBusDevice parent_obj;
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51
52 ARMv7MState armv7m;
53
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54 char *part_name;
55 uint64_t envm_size;
56 uint64_t esram_size;
57
9bfaf375 58 Clock *m3clk;
3b76e185 59 Clock *refclk;
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60 uint8_t apb0div;
61 uint8_t apb1div;
62
63 MSF2SysregState sysreg;
64 MSSTimerState timer;
65 MSSSpiState spi[MSF2_NUM_SPIS];
05b7374a 66 MSF2EmacState emac;
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67
68 MemoryRegion nvm;
69 MemoryRegion nvm_alias;
70 MemoryRegion sram;
db1015e9 71};
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72
73#endif