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2d8f048c HS |
1 | /* |
2 | * Nuvoton NPCM7xx SoC family. | |
3 | * | |
4 | * Copyright 2020 Google LLC | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | */ | |
16 | #ifndef NPCM7XX_H | |
17 | #define NPCM7XX_H | |
18 | ||
19 | #include "hw/boards.h" | |
77c05b0b | 20 | #include "hw/adc/npcm7xx_adc.h" |
2d8f048c | 21 | #include "hw/cpu/a9mpcore.h" |
526dbbe0 | 22 | #include "hw/gpio/npcm7xx_gpio.h" |
94e77879 | 23 | #include "hw/i2c/npcm7xx_smbus.h" |
1351f892 | 24 | #include "hw/mem/npcm7xx_mc.h" |
2d8f048c HS |
25 | #include "hw/misc/npcm7xx_clk.h" |
26 | #include "hw/misc/npcm7xx_gcr.h" | |
1e943c58 | 27 | #include "hw/misc/npcm7xx_pwm.h" |
326ccfe2 | 28 | #include "hw/misc/npcm7xx_rng.h" |
77586436 | 29 | #include "hw/net/npcm7xx_emc.h" |
c752bb07 | 30 | #include "hw/nvram/npcm7xx_otp.h" |
2d8f048c | 31 | #include "hw/timer/npcm7xx_timer.h" |
b821242c | 32 | #include "hw/ssi/npcm7xx_fiu.h" |
e23e7b12 HS |
33 | #include "hw/usb/hcd-ehci.h" |
34 | #include "hw/usb/hcd-ohci.h" | |
2d8f048c HS |
35 | #include "target/arm/cpu.h" |
36 | ||
37 | #define NPCM7XX_MAX_NUM_CPUS (2) | |
38 | ||
39 | /* The first half of the address space is reserved for DDR4 DRAM. */ | |
40 | #define NPCM7XX_DRAM_BA (0x00000000) | |
41 | #define NPCM7XX_DRAM_SZ (2 * GiB) | |
42 | ||
43 | /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ | |
44 | #define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ | |
45 | #define NPCM7XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ | |
46 | #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ | |
47 | #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ | |
2ddae9cc | 48 | #define NPCM7XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ |
2d8f048c | 49 | |
b773acf4 HS |
50 | typedef struct NPCM7xxMachine { |
51 | MachineState parent; | |
52 | } NPCM7xxMachine; | |
53 | ||
54 | #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") | |
55 | #define NPCM7XX_MACHINE(obj) \ | |
56 | OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) | |
57 | ||
58 | typedef struct NPCM7xxMachineClass { | |
59 | MachineClass parent; | |
60 | ||
61 | const char *soc_type; | |
62 | } NPCM7xxMachineClass; | |
63 | ||
64 | #define NPCM7XX_MACHINE_CLASS(klass) \ | |
65 | OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) | |
66 | #define NPCM7XX_MACHINE_GET_CLASS(obj) \ | |
67 | OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) | |
68 | ||
2d8f048c HS |
69 | typedef struct NPCM7xxState { |
70 | DeviceState parent; | |
71 | ||
72 | ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; | |
73 | A9MPPrivState a9mpcore; | |
74 | ||
75 | MemoryRegion sram; | |
76 | MemoryRegion irom; | |
77 | MemoryRegion ram3; | |
78 | MemoryRegion *dram; | |
79 | ||
80 | NPCM7xxGCRState gcr; | |
81 | NPCM7xxCLKState clk; | |
82 | NPCM7xxTimerCtrlState tim[3]; | |
77c05b0b | 83 | NPCM7xxADCState adc; |
1e943c58 | 84 | NPCM7xxPWMState pwm[2]; |
c752bb07 HS |
85 | NPCM7xxOTPState key_storage; |
86 | NPCM7xxOTPState fuse_array; | |
1351f892 | 87 | NPCM7xxMCState mc; |
326ccfe2 | 88 | NPCM7xxRNGState rng; |
526dbbe0 | 89 | NPCM7xxGPIOState gpio[8]; |
94e77879 | 90 | NPCM7xxSMBusState smbus[16]; |
e23e7b12 HS |
91 | EHCISysBusState ehci; |
92 | OHCISysBusState ohci; | |
b821242c | 93 | NPCM7xxFIUState fiu[2]; |
77586436 | 94 | NPCM7xxEMCState emc[2]; |
2d8f048c HS |
95 | } NPCM7xxState; |
96 | ||
97 | #define TYPE_NPCM7XX "npcm7xx" | |
98 | #define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) | |
99 | ||
100 | #define TYPE_NPCM730 "npcm730" | |
101 | #define TYPE_NPCM750 "npcm750" | |
102 | ||
103 | typedef struct NPCM7xxClass { | |
104 | DeviceClass parent; | |
105 | ||
106 | /* Bitmask of modules that are permanently disabled on this chip. */ | |
107 | uint32_t disabled_modules; | |
108 | /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ | |
109 | uint32_t num_cpus; | |
110 | } NPCM7xxClass; | |
111 | ||
112 | #define NPCM7XX_CLASS(klass) \ | |
113 | OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) | |
114 | #define NPCM7XX_GET_CLASS(obj) \ | |
115 | OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) | |
116 | ||
117 | /** | |
118 | * npcm7xx_load_kernel - Loads memory with everything needed to boot | |
119 | * @machine - The machine containing the SoC to be booted. | |
120 | * @soc - The SoC containing the CPU to be booted. | |
121 | * | |
122 | * This will set up the ARM boot info structure for the specific NPCM7xx | |
123 | * derivative and call arm_load_kernel() to set up loading of the kernel, etc. | |
124 | * into memory, if requested by the user. | |
125 | */ | |
126 | void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc); | |
127 | ||
128 | #endif /* NPCM7XX_H */ |