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1 | /* |
2 | * Copyright (C) 2014-2016 Broadcom Corporation | |
3 | * Copyright (c) 2017 Red Hat, Inc. | |
4 | * Written by Prem Mallappa, Eric Auger | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef HW_ARM_SMMUV3_H | |
20 | #define HW_ARM_SMMUV3_H | |
21 | ||
22 | #include "hw/arm/smmu-common.h" | |
23 | #include "hw/registerfields.h" | |
db1015e9 | 24 | #include "qom/object.h" |
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25 | |
26 | #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" | |
27 | ||
28 | typedef struct SMMUQueue { | |
29 | uint64_t base; /* base register */ | |
30 | uint32_t prod; | |
31 | uint32_t cons; | |
32 | uint8_t entry_size; | |
33 | uint8_t log2size; | |
34 | } SMMUQueue; | |
35 | ||
db1015e9 | 36 | struct SMMUv3State { |
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37 | SMMUState smmu_state; |
38 | ||
39 | uint32_t features; | |
40 | uint8_t sid_size; | |
41 | uint8_t sid_split; | |
42 | ||
43 | uint32_t idr[6]; | |
44 | uint32_t iidr; | |
5888f0ad | 45 | uint32_t aidr; |
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46 | uint32_t cr[3]; |
47 | uint32_t cr0ack; | |
48 | uint32_t statusr; | |
49 | uint32_t irq_ctrl; | |
50 | uint32_t gerror; | |
51 | uint32_t gerrorn; | |
52 | uint64_t gerror_irq_cfg0; | |
53 | uint32_t gerror_irq_cfg1; | |
54 | uint32_t gerror_irq_cfg2; | |
55 | uint64_t strtab_base; | |
56 | uint32_t strtab_base_cfg; | |
57 | uint64_t eventq_irq_cfg0; | |
58 | uint32_t eventq_irq_cfg1; | |
59 | uint32_t eventq_irq_cfg2; | |
60 | ||
61 | SMMUQueue eventq, cmdq; | |
62 | ||
63 | qemu_irq irq[4]; | |
32cfd7f3 | 64 | QemuMutex mutex; |
db1015e9 EH |
65 | }; |
66 | typedef struct SMMUv3State SMMUv3State; | |
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67 | |
68 | typedef enum { | |
69 | SMMU_IRQ_EVTQ, | |
70 | SMMU_IRQ_PRIQ, | |
71 | SMMU_IRQ_CMD_SYNC, | |
72 | SMMU_IRQ_GERROR, | |
73 | } SMMUIrq; | |
74 | ||
db1015e9 | 75 | struct SMMUv3Class { |
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76 | /*< private >*/ |
77 | SMMUBaseClass smmu_base_class; | |
78 | /*< public >*/ | |
79 | ||
80 | DeviceRealize parent_realize; | |
81 | DeviceReset parent_reset; | |
db1015e9 EH |
82 | }; |
83 | typedef struct SMMUv3Class SMMUv3Class; | |
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84 | |
85 | #define TYPE_ARM_SMMUV3 "arm-smmuv3" | |
8110fa1d EH |
86 | DECLARE_OBJ_CHECKERS(SMMUv3State, SMMUv3Class, |
87 | ARM_SMMUV3, TYPE_ARM_SMMUV3) | |
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88 | |
89 | #endif |