]>
Commit | Line | Data |
---|---|---|
529fc5fd AF |
1 | /* |
2 | * STM32F405 SoC | |
3 | * | |
4 | * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef HW_ARM_STM32F405_SOC_H | |
26 | #define HW_ARM_STM32F405_SOC_H | |
27 | ||
28 | #include "hw/misc/stm32f4xx_syscfg.h" | |
29 | #include "hw/timer/stm32f2xx_timer.h" | |
30 | #include "hw/char/stm32f2xx_usart.h" | |
31 | #include "hw/adc/stm32f2xx_adc.h" | |
32 | #include "hw/misc/stm32f4xx_exti.h" | |
33 | #include "hw/or-irq.h" | |
34 | #include "hw/ssi/stm32f2xx_spi.h" | |
35 | #include "hw/arm/armv7m.h" | |
db1015e9 | 36 | #include "qom/object.h" |
529fc5fd AF |
37 | |
38 | #define TYPE_STM32F405_SOC "stm32f405-soc" | |
db1015e9 | 39 | typedef struct STM32F405State STM32F405State; |
529fc5fd AF |
40 | #define STM32F405_SOC(obj) \ |
41 | OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC) | |
42 | ||
43 | #define STM_NUM_USARTS 7 | |
44 | #define STM_NUM_TIMERS 4 | |
45 | #define STM_NUM_ADCS 6 | |
46 | #define STM_NUM_SPIS 6 | |
47 | ||
48 | #define FLASH_BASE_ADDRESS 0x08000000 | |
49 | #define FLASH_SIZE (1024 * 1024) | |
50 | #define SRAM_BASE_ADDRESS 0x20000000 | |
51 | #define SRAM_SIZE (192 * 1024) | |
52 | ||
db1015e9 | 53 | struct STM32F405State { |
529fc5fd AF |
54 | /*< private >*/ |
55 | SysBusDevice parent_obj; | |
56 | /*< public >*/ | |
57 | ||
58 | char *cpu_type; | |
59 | ||
60 | ARMv7MState armv7m; | |
61 | ||
62 | STM32F4xxSyscfgState syscfg; | |
63 | STM32F4xxExtiState exti; | |
64 | STM32F2XXUsartState usart[STM_NUM_USARTS]; | |
65 | STM32F2XXTimerState timer[STM_NUM_TIMERS]; | |
66 | qemu_or_irq adc_irqs; | |
67 | STM32F2XXADCState adc[STM_NUM_ADCS]; | |
68 | STM32F2XXSPIState spi[STM_NUM_SPIS]; | |
69 | ||
70 | MemoryRegion sram; | |
71 | MemoryRegion flash; | |
72 | MemoryRegion flash_alias; | |
db1015e9 | 73 | }; |
529fc5fd AF |
74 | |
75 | #endif |