[mirror_qemu.git] / include / hw / arm / xlnx-versal.h

/*
 * Model of the Xilinx Versal
 *
 * Copyright (c) 2018 Xilinx Inc.
 * Written by Edgar E. Iglesias
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 or
 * (at your option) any later version.
 */

#ifndef XLNX_VERSAL_H
#define XLNX_VERSAL_H

#include "hw/sysbus.h"
#include "hw/cpu/cluster.h"
#include "hw/or-irq.h"
#include "hw/sd/sdhci.h"
#include "hw/intc/arm_gicv3.h"
#include "hw/char/pl011.h"
#include "hw/dma/xlnx-zdma.h"
#include "hw/net/cadence_gem.h"
#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "qom/object.h"
#include "hw/usb/xlnx-usb-subsystem.h"
#include "hw/misc/xlnx-versal-xramc.h"
#include "hw/nvram/xlnx-bbram.h"
#include "hw/nvram/xlnx-versal-efuse.h"
#include "hw/ssi/xlnx-versal-ospi.h"
#include "hw/dma/xlnx_csu_dma.h"
#include "hw/misc/xlnx-versal-crl.h"
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#include "hw/misc/xlnx-versal-trng.h"
#include "hw/net/xlnx-versal-canfd.h"
#include "hw/misc/xlnx-versal-cfu.h"
#include "hw/misc/xlnx-versal-cframe-reg.h"
#include "target/arm/cpu.h"

#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)

#define XLNX_VERSAL_NR_ACPUS   2
#define XLNX_VERSAL_NR_RCPUS   2
#define XLNX_VERSAL_NR_UARTS   2
#define XLNX_VERSAL_NR_GEMS    2
#define XLNX_VERSAL_NR_ADMAS   8
#define XLNX_VERSAL_NR_SDS     2
#define XLNX_VERSAL_NR_XRAM    4
#define XLNX_VERSAL_NR_IRQS    192
#define XLNX_VERSAL_NR_CANFD   2
#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
#define XLNX_VERSAL_NR_CFRAME  15

struct Versal {
    /*< private >*/
    SysBusDevice parent_obj;

    /*< public >*/
    struct {
        struct {
            MemoryRegion mr;
            CPUClusterState cluster;
            ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
            GICv3State gic;
        } apu;
    } fpd;

    MemoryRegion mr_ps;

    struct {
        /* 4 ranges to access DDR.  */
        MemoryRegion mr_ddr_ranges[4];
    } noc;

    struct {
        MemoryRegion mr_ocm;

        struct {
            PL011State uart[XLNX_VERSAL_NR_UARTS];
            CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
            XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
            VersalUsb2 usb;
            CanBusState *canbus[XLNX_VERSAL_NR_CANFD];
            XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD];
        } iou;

        /* Real-time Processing Unit.  */
        struct {
            MemoryRegion mr;
            MemoryRegion mr_ps_alias;

            CPUClusterState cluster;
            ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
        } rpu;

        struct {
            OrIRQState irq_orgate;
            XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
        } xram;

        XlnxVersalCRL crl;
    } lpd;

    /* The Platform Management Controller subsystem.  */
    struct {
        struct {
            SDHCIState sd[XLNX_VERSAL_NR_SDS];
            XlnxVersalPmcIouSlcr slcr;

            struct {
                XlnxVersalOspi ospi;
                XlnxCSUDMA dma_src;
                XlnxCSUDMA dma_dst;
                MemoryRegion linear_mr;
                OrIRQState irq_orgate;
            } ospi;
        } iou;

        XlnxZynqMPRTC rtc;
        XlnxVersalTRng trng;
        XlnxBBRam bbram;
        XlnxEFuse efuse;
        XlnxVersalEFuseCtrl efuse_ctrl;
        XlnxVersalEFuseCache efuse_cache;
        XlnxVersalCFUAPB cfu_apb;
        XlnxVersalCFUFDRO cfu_fdro;
        XlnxVersalCFUSFR cfu_sfr;
        XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
        XlnxVersalCFrameBcastReg cframe_bcast;

        OrIRQState apb_irq_orgate;
    } pmc;

    struct {
        MemoryRegion *mr_ddr;
    } cfg;
};

/* Memory-map and IRQ definitions. Copied a subset from
 * auto-generated files.  */

#define VERSAL_GIC_MAINT_IRQ        9
#define VERSAL_TIMER_VIRT_IRQ       11
#define VERSAL_TIMER_S_EL1_IRQ      13
#define VERSAL_TIMER_NS_EL1_IRQ     14
#define VERSAL_TIMER_NS_EL2_IRQ     10

#define VERSAL_CRL_IRQ             10
#define VERSAL_UART0_IRQ_0         18
#define VERSAL_UART1_IRQ_0         19
#define VERSAL_CANFD0_IRQ_0        20
#define VERSAL_CANFD1_IRQ_0        21
#define VERSAL_USB0_IRQ_0          22
#define VERSAL_GEM0_IRQ_0          56
#define VERSAL_GEM0_WAKE_IRQ_0     57
#define VERSAL_GEM1_IRQ_0          58
#define VERSAL_GEM1_WAKE_IRQ_0     59
#define VERSAL_ADMA_IRQ_0          60
#define VERSAL_XRAM_IRQ_0          79
#define VERSAL_CFU_IRQ_0           120
#define VERSAL_PMC_APB_IRQ         121
#define VERSAL_OSPI_IRQ            124
#define VERSAL_SD0_IRQ_0           126
#define VERSAL_EFUSE_IRQ           139
#define VERSAL_TRNG_IRQ            141
#define VERSAL_RTC_ALARM_IRQ       142
#define VERSAL_RTC_SECONDS_IRQ     143

/* Architecturally reserved IRQs suitable for virtualization.  */
#define VERSAL_RSVD_IRQ_FIRST 111
#define VERSAL_RSVD_IRQ_LAST  118

#define MM_TOP_RSVD                 0xa0000000U
#define MM_TOP_RSVD_SIZE            0x4000000
#define MM_GIC_APU_DIST_MAIN        0xf9000000U
#define MM_GIC_APU_DIST_MAIN_SIZE   0x10000
#define MM_GIC_APU_REDIST_0         0xf9080000U
#define MM_GIC_APU_REDIST_0_SIZE    0x80000

#define MM_UART0                    0xff000000U
#define MM_UART0_SIZE               0x10000
#define MM_UART1                    0xff010000U
#define MM_UART1_SIZE               0x10000

#define MM_CANFD0                   0xff060000U
#define MM_CANFD0_SIZE              0x10000
#define MM_CANFD1                   0xff070000U
#define MM_CANFD1_SIZE              0x10000

#define MM_GEM0                     0xff0c0000U
#define MM_GEM0_SIZE                0x10000
#define MM_GEM1                     0xff0d0000U
#define MM_GEM1_SIZE                0x10000

#define MM_ADMA_CH0                 0xffa80000U
#define MM_ADMA_CH0_SIZE            0x10000

#define MM_OCM                      0xfffc0000U
#define MM_OCM_SIZE                 0x40000

#define MM_XRAM                     0xfe800000
#define MM_XRAMC                    0xff8e0000
#define MM_XRAMC_SIZE               0x10000

#define MM_USB2_CTRL_REGS           0xFF9D0000
#define MM_USB2_CTRL_REGS_SIZE      0x10000

#define MM_USB_0                    0xFE200000
#define MM_USB_0_SIZE               0x10000

#define MM_TOP_DDR                  0x0
#define MM_TOP_DDR_SIZE             0x80000000U
#define MM_TOP_DDR_2                0x800000000ULL
#define MM_TOP_DDR_2_SIZE           0x800000000ULL
#define MM_TOP_DDR_3                0xc000000000ULL
#define MM_TOP_DDR_3_SIZE           0x4000000000ULL
#define MM_TOP_DDR_4                0x10000000000ULL
#define MM_TOP_DDR_4_SIZE           0xb780000000ULL

#define MM_PSM_START                0xffc80000U
#define MM_PSM_END                  0xffcf0000U

#define MM_CRL                      0xff5e0000U
#define MM_CRL_SIZE                 0x300000
#define MM_IOU_SCNTR                0xff130000U
#define MM_IOU_SCNTR_SIZE           0x10000
#define MM_IOU_SCNTRS               0xff140000U
#define MM_IOU_SCNTRS_SIZE          0x10000
#define MM_FPD_CRF                  0xfd1a0000U
#define MM_FPD_CRF_SIZE             0x140000
#define MM_FPD_FPD_APU              0xfd5c0000
#define MM_FPD_FPD_APU_SIZE         0x100

#define MM_PMC_PMC_IOU_SLCR         0xf1060000
#define MM_PMC_PMC_IOU_SLCR_SIZE    0x10000

#define MM_PMC_OSPI                 0xf1010000
#define MM_PMC_OSPI_SIZE            0x10000

#define MM_PMC_OSPI_DAC             0xc0000000
#define MM_PMC_OSPI_DAC_SIZE        0x20000000

#define MM_PMC_OSPI_DMA_DST         0xf1011800
#define MM_PMC_OSPI_DMA_SRC         0xf1011000

#define MM_PMC_SD0                  0xf1040000U
#define MM_PMC_SD0_SIZE             0x10000
#define MM_PMC_BBRAM_CTRL           0xf11f0000
#define MM_PMC_BBRAM_CTRL_SIZE      0x00050
#define MM_PMC_EFUSE_CTRL           0xf1240000
#define MM_PMC_EFUSE_CTRL_SIZE      0x00104
#define MM_PMC_EFUSE_CACHE          0xf1250000
#define MM_PMC_EFUSE_CACHE_SIZE     0x00C00

#define MM_PMC_CFU_APB              0xf12b0000
#define MM_PMC_CFU_APB_SIZE         0x10000
#define MM_PMC_CFU_STREAM           0xf12c0000
#define MM_PMC_CFU_STREAM_SIZE      0x1000
#define MM_PMC_CFU_SFR              0xf12c1000
#define MM_PMC_CFU_SFR_SIZE         0x1000
#define MM_PMC_CFU_FDRO             0xf12c2000
#define MM_PMC_CFU_FDRO_SIZE        0x1000
#define MM_PMC_CFU_STREAM_2         0xf1f80000
#define MM_PMC_CFU_STREAM_2_SIZE    0x40000

#define MM_PMC_CFRAME0_REG          0xf12d0000
#define MM_PMC_CFRAME0_REG_SIZE     0x1000
#define MM_PMC_CFRAME0_FDRI         0xf12d1000
#define MM_PMC_CFRAME0_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME1_REG          0xf12d2000
#define MM_PMC_CFRAME1_REG_SIZE     0x1000
#define MM_PMC_CFRAME1_FDRI         0xf12d3000
#define MM_PMC_CFRAME1_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME2_REG          0xf12d4000
#define MM_PMC_CFRAME2_REG_SIZE     0x1000
#define MM_PMC_CFRAME2_FDRI         0xf12d5000
#define MM_PMC_CFRAME2_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME3_REG          0xf12d6000
#define MM_PMC_CFRAME3_REG_SIZE     0x1000
#define MM_PMC_CFRAME3_FDRI         0xf12d7000
#define MM_PMC_CFRAME3_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME4_REG          0xf12d8000
#define MM_PMC_CFRAME4_REG_SIZE     0x1000
#define MM_PMC_CFRAME4_FDRI         0xf12d9000
#define MM_PMC_CFRAME4_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME5_REG          0xf12da000
#define MM_PMC_CFRAME5_REG_SIZE     0x1000
#define MM_PMC_CFRAME5_FDRI         0xf12db000
#define MM_PMC_CFRAME5_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME6_REG          0xf12dc000
#define MM_PMC_CFRAME6_REG_SIZE     0x1000
#define MM_PMC_CFRAME6_FDRI         0xf12dd000
#define MM_PMC_CFRAME6_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME7_REG          0xf12de000
#define MM_PMC_CFRAME7_REG_SIZE     0x1000
#define MM_PMC_CFRAME7_FDRI         0xf12df000
#define MM_PMC_CFRAME7_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME8_REG          0xf12e0000
#define MM_PMC_CFRAME8_REG_SIZE     0x1000
#define MM_PMC_CFRAME8_FDRI         0xf12e1000
#define MM_PMC_CFRAME8_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME9_REG          0xf12e2000
#define MM_PMC_CFRAME9_REG_SIZE     0x1000
#define MM_PMC_CFRAME9_FDRI         0xf12e3000
#define MM_PMC_CFRAME9_FDRI_SIZE    0x1000
#define MM_PMC_CFRAME10_REG         0xf12e4000
#define MM_PMC_CFRAME10_REG_SIZE    0x1000
#define MM_PMC_CFRAME10_FDRI        0xf12e5000
#define MM_PMC_CFRAME10_FDRI_SIZE   0x1000
#define MM_PMC_CFRAME11_REG         0xf12e6000
#define MM_PMC_CFRAME11_REG_SIZE    0x1000
#define MM_PMC_CFRAME11_FDRI        0xf12e7000
#define MM_PMC_CFRAME11_FDRI_SIZE   0x1000
#define MM_PMC_CFRAME12_REG         0xf12e8000
#define MM_PMC_CFRAME12_REG_SIZE    0x1000
#define MM_PMC_CFRAME12_FDRI        0xf12e9000
#define MM_PMC_CFRAME12_FDRI_SIZE   0x1000
#define MM_PMC_CFRAME13_REG         0xf12ea000
#define MM_PMC_CFRAME13_REG_SIZE    0x1000
#define MM_PMC_CFRAME13_FDRI        0xf12eb000
#define MM_PMC_CFRAME13_FDRI_SIZE   0x1000
#define MM_PMC_CFRAME14_REG         0xf12ec000
#define MM_PMC_CFRAME14_REG_SIZE    0x1000
#define MM_PMC_CFRAME14_FDRI        0xf12ed000
#define MM_PMC_CFRAME14_FDRI_SIZE   0x1000
#define MM_PMC_CFRAME_BCAST_REG       0xf12ee000
#define MM_PMC_CFRAME_BCAST_REG_SIZE  0x1000
#define MM_PMC_CFRAME_BCAST_FDRI      0xf12ef000
#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000

#define MM_PMC_CRP                  0xf1260000U
#define MM_PMC_CRP_SIZE             0x10000
#define MM_PMC_RTC                  0xf12a0000
#define MM_PMC_RTC_SIZE             0x10000
#define MM_PMC_TRNG                 0xf1230000
#define MM_PMC_TRNG_SIZE            0x10000
#endif
Commit	Line	Data
b89de436 EI	1	/*
	2	* Model of the Xilinx Versal
	3	*
	4	* Copyright (c) 2018 Xilinx Inc.
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 or
	9	* (at your option) any later version.
	10	*/
	11
	12	#ifndef XLNX_VERSAL_H
	13	#define XLNX_VERSAL_H
	14
	15	#include "hw/sysbus.h"
8779d00c	16	#include "hw/cpu/cluster.h"
a55b441b	17	#include "hw/or-irq.h"
724c6e12	18	#include "hw/sd/sdhci.h"
b89de436	19	#include "hw/intc/arm_gicv3.h"
88052ffd	20	#include "hw/char/pl011.h"
f4e3fa37	21	#include "hw/dma/xlnx-zdma.h"
4bd9b59c	22	#include "hw/net/cadence_gem.h"
eb1221c5	23	#include "hw/rtc/xlnx-zynqmp-rtc.h"
db1015e9	24	#include "qom/object.h"
144677d4	25	#include "hw/usb/xlnx-usb-subsystem.h"
a55b441b	26	#include "hw/misc/xlnx-versal-xramc.h"
393185bc	27	#include "hw/nvram/xlnx-bbram.h"
5f4910ff	28	#include "hw/nvram/xlnx-versal-efuse.h"
868d9680 FI	29	#include "hw/ssi/xlnx-versal-ospi.h"
868d9680 FI	30	#include "hw/dma/xlnx_csu_dma.h"
d6ccfc7e	31	#include "hw/misc/xlnx-versal-crl.h"
f7c9aecb	32	#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
3b22376b	33	#include "hw/misc/xlnx-versal-trng.h"
042d6b02	34	#include "hw/net/xlnx-versal-canfd.h"
b286d08a	35	#include "hw/misc/xlnx-versal-cfu.h"
4a0244b4	36	#include "hw/misc/xlnx-versal-cframe-reg.h"
5b5f4169	37	#include "target/arm/cpu.h"
b89de436 EI	38
b89de436 EI	39	#define TYPE_XLNX_VERSAL "xlnx-versal"
8063396b	40	OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
b89de436 EI	41
b89de436 EI	42	#define XLNX_VERSAL_NR_ACPUS 2
67a645a3	43	#define XLNX_VERSAL_NR_RCPUS 2
b89de436 EI	44	#define XLNX_VERSAL_NR_UARTS 2
b89de436 EI	45	#define XLNX_VERSAL_NR_GEMS 2
8a218651	46	#define XLNX_VERSAL_NR_ADMAS 8
724c6e12	47	#define XLNX_VERSAL_NR_SDS 2
a55b441b	48	#define XLNX_VERSAL_NR_XRAM 4
f6ef171d	49	#define XLNX_VERSAL_NR_IRQS 192
042d6b02 VG	50	#define XLNX_VERSAL_NR_CANFD 2
042d6b02 VG	51	#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
4a0244b4	52	#define XLNX_VERSAL_NR_CFRAME 15
b89de436	53
db1015e9	54	struct Versal {
b89de436 EI	55	/< private >/
	56	SysBusDevice parent_obj;
	57
	58	/< public >/
	59	struct {
	60	struct {
	61	MemoryRegion mr;
8779d00c	62	CPUClusterState cluster;
ced18d5e	63	ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
b89de436 EI	64	GICv3State gic;
	65	} apu;
	66	} fpd;
	67
	68	MemoryRegion mr_ps;
	69
	70	struct {
	71	/* 4 ranges to access DDR. */
	72	MemoryRegion mr_ddr_ranges[4];
	73	} noc;
	74
	75	struct {
	76	MemoryRegion mr_ocm;
	77
	78	struct {
88052ffd	79	PL011State uart[XLNX_VERSAL_NR_UARTS];
4bd9b59c	80	CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
f4e3fa37	81	XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
144677d4	82	VersalUsb2 usb;
042d6b02 VG	83	CanBusState *canbus[XLNX_VERSAL_NR_CANFD];
042d6b02 VG	84	XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD];
b89de436	85	} iou;
a55b441b	86
67a645a3 EI	87	/* Real-time Processing Unit. */
	88	struct {
	89	MemoryRegion mr;
	90	MemoryRegion mr_ps_alias;
	91
	92	CPUClusterState cluster;
	93	ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
	94	} rpu;
	95
a55b441b	96	struct {
e844f0c5	97	OrIRQState irq_orgate;
a55b441b EI	98	XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
a55b441b EI	99	} xram;
d6ccfc7e EI	100
d6ccfc7e EI	101	XlnxVersalCRL crl;
b89de436 EI	102	} lpd;
b89de436 EI	103
724c6e12 EI	104	/* The Platform Management Controller subsystem. */
	105	struct {
	106	struct {
	107	SDHCIState sd[XLNX_VERSAL_NR_SDS];
f7c9aecb	108	XlnxVersalPmcIouSlcr slcr;
868d9680 FI	109
	110	struct {
	111	XlnxVersalOspi ospi;
	112	XlnxCSUDMA dma_src;
	113	XlnxCSUDMA dma_dst;
	114	MemoryRegion linear_mr;
e844f0c5	115	OrIRQState irq_orgate;
868d9680	116	} ospi;
724c6e12	117	} iou;
eb1221c5 EI	118
eb1221c5 EI	119	XlnxZynqMPRTC rtc;
3b22376b	120	XlnxVersalTRng trng;
393185bc	121	XlnxBBRam bbram;
5f4910ff TH	122	XlnxEFuse efuse;
	123	XlnxVersalEFuseCtrl efuse_ctrl;
	124	XlnxVersalEFuseCache efuse_cache;
b286d08a FI	125	XlnxVersalCFUAPB cfu_apb;
	126	XlnxVersalCFUFDRO cfu_fdro;
	127	XlnxVersalCFUSFR cfu_sfr;
4a0244b4 FI	128	XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
4a0244b4 FI	129	XlnxVersalCFrameBcastReg cframe_bcast;
9a6d4918	130
e844f0c5	131	OrIRQState apb_irq_orgate;
724c6e12 EI	132	} pmc;
724c6e12 EI	133
b89de436 EI	134	struct {
b89de436 EI	135	MemoryRegion *mr_ddr;
b89de436	136	} cfg;
db1015e9	137	};
b89de436 EI	138
	139	/* Memory-map and IRQ definitions. Copied a subset from
	140	* auto-generated files. */
	141
	142	#define VERSAL_GIC_MAINT_IRQ 9
	143	#define VERSAL_TIMER_VIRT_IRQ 11
	144	#define VERSAL_TIMER_S_EL1_IRQ 13
	145	#define VERSAL_TIMER_NS_EL1_IRQ 14
	146	#define VERSAL_TIMER_NS_EL2_IRQ 10
	147
d6ccfc7e	148	#define VERSAL_CRL_IRQ 10
b89de436 EI	149	#define VERSAL_UART0_IRQ_0 18
b89de436 EI	150	#define VERSAL_UART1_IRQ_0 19
042d6b02 VG	151	#define VERSAL_CANFD0_IRQ_0 20
042d6b02 VG	152	#define VERSAL_CANFD1_IRQ_0 21
144677d4	153	#define VERSAL_USB0_IRQ_0 22
b89de436 EI	154	#define VERSAL_GEM0_IRQ_0 56
	155	#define VERSAL_GEM0_WAKE_IRQ_0 57
	156	#define VERSAL_GEM1_IRQ_0 58
	157	#define VERSAL_GEM1_WAKE_IRQ_0 59
8a218651	158	#define VERSAL_ADMA_IRQ_0 60
a55b441b	159	#define VERSAL_XRAM_IRQ_0 79
b286d08a	160	#define VERSAL_CFU_IRQ_0 120
9a6d4918	161	#define VERSAL_PMC_APB_IRQ 121
868d9680	162	#define VERSAL_OSPI_IRQ 124
724c6e12	163	#define VERSAL_SD0_IRQ_0 126
5f4910ff	164	#define VERSAL_EFUSE_IRQ 139
3b22376b	165	#define VERSAL_TRNG_IRQ 141
eb1221c5 EI	166	#define VERSAL_RTC_ALARM_IRQ 142
eb1221c5 EI	167	#define VERSAL_RTC_SECONDS_IRQ 143
b89de436	168
fb179055 EI	169	/* Architecturally reserved IRQs suitable for virtualization. */
	170	#define VERSAL_RSVD_IRQ_FIRST 111
	171	#define VERSAL_RSVD_IRQ_LAST 118
b89de436 EI	172
	173	#define MM_TOP_RSVD 0xa0000000U
	174	#define MM_TOP_RSVD_SIZE 0x4000000
	175	#define MM_GIC_APU_DIST_MAIN 0xf9000000U
	176	#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
	177	#define MM_GIC_APU_REDIST_0 0xf9080000U
	178	#define MM_GIC_APU_REDIST_0_SIZE 0x80000
	179
	180	#define MM_UART0 0xff000000U
	181	#define MM_UART0_SIZE 0x10000
	182	#define MM_UART1 0xff010000U
	183	#define MM_UART1_SIZE 0x10000
	184
042d6b02 VG	185	#define MM_CANFD0 0xff060000U
	186	#define MM_CANFD0_SIZE 0x10000
	187	#define MM_CANFD1 0xff070000U
	188	#define MM_CANFD1_SIZE 0x10000
	189
b89de436 EI	190	#define MM_GEM0 0xff0c0000U
	191	#define MM_GEM0_SIZE 0x10000
	192	#define MM_GEM1 0xff0d0000U
	193	#define MM_GEM1_SIZE 0x10000
	194
8a218651 EI	195	#define MM_ADMA_CH0 0xffa80000U
	196	#define MM_ADMA_CH0_SIZE 0x10000
	197
b89de436 EI	198	#define MM_OCM 0xfffc0000U
	199	#define MM_OCM_SIZE 0x40000
	200
a55b441b EI	201	#define MM_XRAM 0xfe800000
	202	#define MM_XRAMC 0xff8e0000
	203	#define MM_XRAMC_SIZE 0x10000
	204
144677d4 VG	205	#define MM_USB2_CTRL_REGS 0xFF9D0000
	206	#define MM_USB2_CTRL_REGS_SIZE 0x10000
	207
	208	#define MM_USB_0 0xFE200000
	209	#define MM_USB_0_SIZE 0x10000
	210
b89de436 EI	211	#define MM_TOP_DDR 0x0
	212	#define MM_TOP_DDR_SIZE 0x80000000U
	213	#define MM_TOP_DDR_2 0x800000000ULL
	214	#define MM_TOP_DDR_2_SIZE 0x800000000ULL
	215	#define MM_TOP_DDR_3 0xc000000000ULL
	216	#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
	217	#define MM_TOP_DDR_4 0x10000000000ULL
	218	#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
	219
	220	#define MM_PSM_START 0xffc80000U
	221	#define MM_PSM_END 0xffcf0000U
	222
	223	#define MM_CRL 0xff5e0000U
	224	#define MM_CRL_SIZE 0x300000
	225	#define MM_IOU_SCNTR 0xff130000U
	226	#define MM_IOU_SCNTR_SIZE 0x10000
	227	#define MM_IOU_SCNTRS 0xff140000U
	228	#define MM_IOU_SCNTRS_SIZE 0x10000
	229	#define MM_FPD_CRF 0xfd1a0000U
	230	#define MM_FPD_CRF_SIZE 0x140000
9a0fcb7f TH	231	#define MM_FPD_FPD_APU 0xfd5c0000
9a0fcb7f TH	232	#define MM_FPD_FPD_APU_SIZE 0x100
f0138990	233
f7c9aecb FI	234	#define MM_PMC_PMC_IOU_SLCR 0xf1060000
	235	#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
	236
868d9680 FI	237	#define MM_PMC_OSPI 0xf1010000
	238	#define MM_PMC_OSPI_SIZE 0x10000
	239
	240	#define MM_PMC_OSPI_DAC 0xc0000000
	241	#define MM_PMC_OSPI_DAC_SIZE 0x20000000
	242
	243	#define MM_PMC_OSPI_DMA_DST 0xf1011800
	244	#define MM_PMC_OSPI_DMA_SRC 0xf1011000
	245
724c6e12 EI	246	#define MM_PMC_SD0 0xf1040000U
724c6e12 EI	247	#define MM_PMC_SD0_SIZE 0x10000
393185bc TH	248	#define MM_PMC_BBRAM_CTRL 0xf11f0000
393185bc TH	249	#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
5f4910ff TH	250	#define MM_PMC_EFUSE_CTRL 0xf1240000
	251	#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
	252	#define MM_PMC_EFUSE_CACHE 0xf1250000
	253	#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
	254
b286d08a FI	255	#define MM_PMC_CFU_APB 0xf12b0000
	256	#define MM_PMC_CFU_APB_SIZE 0x10000
	257	#define MM_PMC_CFU_STREAM 0xf12c0000
	258	#define MM_PMC_CFU_STREAM_SIZE 0x1000
	259	#define MM_PMC_CFU_SFR 0xf12c1000
	260	#define MM_PMC_CFU_SFR_SIZE 0x1000
	261	#define MM_PMC_CFU_FDRO 0xf12c2000
	262	#define MM_PMC_CFU_FDRO_SIZE 0x1000
	263	#define MM_PMC_CFU_STREAM_2 0xf1f80000
	264	#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
	265
4a0244b4 FI	266	#define MM_PMC_CFRAME0_REG 0xf12d0000
	267	#define MM_PMC_CFRAME0_REG_SIZE 0x1000
	268	#define MM_PMC_CFRAME0_FDRI 0xf12d1000
	269	#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
	270	#define MM_PMC_CFRAME1_REG 0xf12d2000
	271	#define MM_PMC_CFRAME1_REG_SIZE 0x1000
	272	#define MM_PMC_CFRAME1_FDRI 0xf12d3000
	273	#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
	274	#define MM_PMC_CFRAME2_REG 0xf12d4000
	275	#define MM_PMC_CFRAME2_REG_SIZE 0x1000
	276	#define MM_PMC_CFRAME2_FDRI 0xf12d5000
	277	#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
	278	#define MM_PMC_CFRAME3_REG 0xf12d6000
	279	#define MM_PMC_CFRAME3_REG_SIZE 0x1000
	280	#define MM_PMC_CFRAME3_FDRI 0xf12d7000
	281	#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
	282	#define MM_PMC_CFRAME4_REG 0xf12d8000
	283	#define MM_PMC_CFRAME4_REG_SIZE 0x1000
	284	#define MM_PMC_CFRAME4_FDRI 0xf12d9000
	285	#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
	286	#define MM_PMC_CFRAME5_REG 0xf12da000
	287	#define MM_PMC_CFRAME5_REG_SIZE 0x1000
	288	#define MM_PMC_CFRAME5_FDRI 0xf12db000
	289	#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
	290	#define MM_PMC_CFRAME6_REG 0xf12dc000
	291	#define MM_PMC_CFRAME6_REG_SIZE 0x1000
	292	#define MM_PMC_CFRAME6_FDRI 0xf12dd000
	293	#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
	294	#define MM_PMC_CFRAME7_REG 0xf12de000
	295	#define MM_PMC_CFRAME7_REG_SIZE 0x1000
	296	#define MM_PMC_CFRAME7_FDRI 0xf12df000
	297	#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
	298	#define MM_PMC_CFRAME8_REG 0xf12e0000
	299	#define MM_PMC_CFRAME8_REG_SIZE 0x1000
	300	#define MM_PMC_CFRAME8_FDRI 0xf12e1000
	301	#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
	302	#define MM_PMC_CFRAME9_REG 0xf12e2000
	303	#define MM_PMC_CFRAME9_REG_SIZE 0x1000
	304	#define MM_PMC_CFRAME9_FDRI 0xf12e3000
	305	#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
	306	#define MM_PMC_CFRAME10_REG 0xf12e4000
	307	#define MM_PMC_CFRAME10_REG_SIZE 0x1000
	308	#define MM_PMC_CFRAME10_FDRI 0xf12e5000
	309	#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
	310	#define MM_PMC_CFRAME11_REG 0xf12e6000
	311	#define MM_PMC_CFRAME11_REG_SIZE 0x1000
	312	#define MM_PMC_CFRAME11_FDRI 0xf12e7000
	313	#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
	314	#define MM_PMC_CFRAME12_REG 0xf12e8000
	315	#define MM_PMC_CFRAME12_REG_SIZE 0x1000
	316	#define MM_PMC_CFRAME12_FDRI 0xf12e9000
	317	#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
	318	#define MM_PMC_CFRAME13_REG 0xf12ea000
	319	#define MM_PMC_CFRAME13_REG_SIZE 0x1000
	320	#define MM_PMC_CFRAME13_FDRI 0xf12eb000
	321	#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
	322	#define MM_PMC_CFRAME14_REG 0xf12ec000
	323	#define MM_PMC_CFRAME14_REG_SIZE 0x1000
	324	#define MM_PMC_CFRAME14_FDRI 0xf12ed000
	325	#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
	326	#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
	327	#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
	328	#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
	329	#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
330
f0138990 EI	331	#define MM_PMC_CRP 0xf1260000U
f0138990 EI	332	#define MM_PMC_CRP_SIZE 0x10000
eb1221c5 EI	333	#define MM_PMC_RTC 0xf12a0000
eb1221c5 EI	334	#define MM_PMC_RTC_SIZE 0x10000
3b22376b TH	335	#define MM_PMC_TRNG 0xf1230000
3b22376b TH	336	#define MM_PMC_TRNG_SIZE 0x10000
b89de436	337	#endif