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f0a902f7 PC |
1 | /* |
2 | * Xilinx Zynq MPSoC emulation | |
3 | * | |
4 | * Copyright (C) 2015 Xilinx Inc | |
5 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | */ | |
17 | ||
18 | #ifndef XLNX_ZYNQMP_H | |
0553d895 | 19 | #define XLNX_ZYNQMP_H |
f0a902f7 | 20 | |
12ec8bd5 | 21 | #include "hw/arm/boot.h" |
7729e1f4 | 22 | #include "hw/intc/arm_gic.h" |
14ca2e46 | 23 | #include "hw/net/cadence_gem.h" |
3bade2a9 | 24 | #include "hw/char/cadence_uart.h" |
840c22cd | 25 | #include "hw/net/xlnx-zynqmp-can.h" |
6fdf3282 | 26 | #include "hw/ide/ahci.h" |
33108e9f | 27 | #include "hw/sd/sdhci.h" |
02d07eb4 | 28 | #include "hw/ssi/xilinx_spips.h" |
b93dbcdd | 29 | #include "hw/dma/xlnx_dpdma.h" |
04965bca | 30 | #include "hw/dma/xlnx-zdma.h" |
b93dbcdd | 31 | #include "hw/display/xlnx_dp.h" |
0ab7bbc7 | 32 | #include "hw/intc/xlnx-zynqmp-ipi.h" |
8035f85e | 33 | #include "hw/rtc/xlnx-zynqmp-rtc.h" |
816fd397 | 34 | #include "hw/cpu/cluster.h" |
ec150c7e | 35 | #include "target/arm/cpu.h" |
db1015e9 | 36 | #include "qom/object.h" |
840c22cd | 37 | #include "net/can_emu.h" |
668351a5 | 38 | #include "hw/dma/xlnx_csu_dma.h" |
7e47e15c | 39 | #include "hw/nvram/xlnx-bbram.h" |
db1264df | 40 | #include "hw/nvram/xlnx-zynqmp-efuse.h" |
c74ccb5d | 41 | #include "hw/or-irq.h" |
eb7a38ba | 42 | #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" |
63320bca | 43 | #include "hw/misc/xlnx-zynqmp-crf.h" |
51af6231 | 44 | #include "hw/timer/cadence_ttc.h" |
acc0b8b0 | 45 | #include "hw/usb/hcd-dwc3.h" |
f0a902f7 | 46 | |
e178113f | 47 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" |
8063396b | 48 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) |
f0a902f7 | 49 | |
2e5577bc | 50 | #define XLNX_ZYNQMP_NUM_APU_CPUS 4 |
b58850e7 | 51 | #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 |
14ca2e46 | 52 | #define XLNX_ZYNQMP_NUM_GEMS 4 |
3bade2a9 | 53 | #define XLNX_ZYNQMP_NUM_UARTS 2 |
840c22cd VG |
54 | #define XLNX_ZYNQMP_NUM_CAN 2 |
55 | #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) | |
33108e9f | 56 | #define XLNX_ZYNQMP_NUM_SDHCI 2 |
02d07eb4 | 57 | #define XLNX_ZYNQMP_NUM_SPIS 2 |
04965bca FI |
58 | #define XLNX_ZYNQMP_NUM_GDMA_CH 8 |
59 | #define XLNX_ZYNQMP_NUM_ADMA_CH 8 | |
acc0b8b0 | 60 | #define XLNX_ZYNQMP_NUM_USB 2 |
f0a902f7 | 61 | |
babc1f30 FI |
62 | #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 |
63 | #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 | |
64 | #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 | |
65 | ||
6675d719 AF |
66 | #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 |
67 | #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 | |
68 | #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 | |
69 | ||
75b749af | 70 | #define XLNX_ZYNQMP_GIC_REGIONS 6 |
7729e1f4 | 71 | |
21bce371 XC |
72 | /* |
73 | * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets | |
7729e1f4 PC |
74 | * and under-decodes the 64k region. This mirrors the 4k regions to every 4k |
75 | * aligned address in the 64k region. To implement each GIC region needs a | |
76 | * number of memory region aliases. | |
77 | */ | |
78 | ||
52c16b45 | 79 | #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 |
75b749af | 80 | #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) |
7729e1f4 | 81 | |
dc3b89ef AF |
82 | #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull |
83 | ||
84 | #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull | |
85 | #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull | |
86 | ||
87 | #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ | |
88 | XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) | |
89 | ||
51af6231 EI |
90 | #define XLNX_ZYNQMP_NUM_TTC 4 |
91 | ||
d2e6f370 TH |
92 | /* |
93 | * Unimplemented mmio regions needed to boot some images. | |
94 | */ | |
eb7a38ba | 95 | #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 |
d2e6f370 | 96 | |
db1015e9 | 97 | struct XlnxZynqMPState { |
f0a902f7 PC |
98 | /*< private >*/ |
99 | DeviceState parent_obj; | |
100 | ||
101 | /*< public >*/ | |
816fd397 LM |
102 | CPUClusterState apu_cluster; |
103 | CPUClusterState rpu_cluster; | |
2e5577bc | 104 | ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; |
b58850e7 | 105 | ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; |
7729e1f4 PC |
106 | GICState gic; |
107 | MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; | |
dc3b89ef | 108 | |
6675d719 AF |
109 | MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; |
110 | ||
dc3b89ef AF |
111 | MemoryRegion *ddr_ram; |
112 | MemoryRegion ddr_ram_low, ddr_ram_high; | |
7e47e15c | 113 | XlnxBBRam bbram; |
db1264df TH |
114 | XlnxEFuse efuse; |
115 | XlnxZynqMPEFuse efuse_ctrl; | |
dc3b89ef | 116 | |
d2e6f370 TH |
117 | MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; |
118 | ||
14ca2e46 | 119 | CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; |
3bade2a9 | 120 | CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; |
840c22cd | 121 | XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; |
6fdf3282 | 122 | SysbusAHCIState sata; |
33108e9f | 123 | SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; |
02d07eb4 | 124 | XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; |
babc1f30 | 125 | XlnxZynqMPQSPIPS qspi; |
b93dbcdd FK |
126 | XlnxDPState dp; |
127 | XlnxDPDMAState dpdma; | |
0ab7bbc7 | 128 | XlnxZynqMPIPI ipi; |
08b2f15e | 129 | XlnxZynqMPRTC rtc; |
04965bca FI |
130 | XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; |
131 | XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; | |
668351a5 | 132 | XlnxCSUDMA qspi_dma; |
c74ccb5d | 133 | qemu_or_irq qspi_irq_orgate; |
eb7a38ba | 134 | XlnxZynqMPAPUCtrl apu_ctrl; |
63320bca | 135 | XlnxZynqMPCRF crf; |
51af6231 | 136 | CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; |
acc0b8b0 | 137 | USBDWC3 usb[XLNX_ZYNQMP_NUM_USB]; |
6396a193 PC |
138 | |
139 | char *boot_cpu; | |
140 | ARMCPU *boot_cpu_ptr; | |
37d42473 EI |
141 | |
142 | /* Has the ARM Security extensions? */ | |
143 | bool secure; | |
1946809e AF |
144 | /* Has the ARM Virtualization extensions? */ |
145 | bool virt; | |
840c22cd VG |
146 | |
147 | /* CAN bus. */ | |
148 | CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; | |
db1015e9 | 149 | }; |
f0a902f7 | 150 | |
f0a902f7 | 151 | #endif |