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f0a902f7 PC |
1 | /* |
2 | * Xilinx Zynq MPSoC emulation | |
3 | * | |
4 | * Copyright (C) 2015 Xilinx Inc | |
5 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | */ | |
17 | ||
18 | #ifndef XLNX_ZYNQMP_H | |
19 | ||
20 | #include "qemu-common.h" | |
12ec8bd5 | 21 | #include "hw/arm/boot.h" |
7729e1f4 | 22 | #include "hw/intc/arm_gic.h" |
14ca2e46 | 23 | #include "hw/net/cadence_gem.h" |
3bade2a9 | 24 | #include "hw/char/cadence_uart.h" |
6fdf3282 AF |
25 | #include "hw/ide/pci.h" |
26 | #include "hw/ide/ahci.h" | |
33108e9f | 27 | #include "hw/sd/sdhci.h" |
02d07eb4 | 28 | #include "hw/ssi/xilinx_spips.h" |
b93dbcdd | 29 | #include "hw/dma/xlnx_dpdma.h" |
04965bca | 30 | #include "hw/dma/xlnx-zdma.h" |
b93dbcdd | 31 | #include "hw/display/xlnx_dp.h" |
0ab7bbc7 | 32 | #include "hw/intc/xlnx-zynqmp-ipi.h" |
08b2f15e | 33 | #include "hw/timer/xlnx-zynqmp-rtc.h" |
816fd397 | 34 | #include "hw/cpu/cluster.h" |
f0a902f7 PC |
35 | |
36 | #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" | |
37 | #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ | |
38 | TYPE_XLNX_ZYNQMP) | |
39 | ||
2e5577bc | 40 | #define XLNX_ZYNQMP_NUM_APU_CPUS 4 |
b58850e7 | 41 | #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 |
14ca2e46 | 42 | #define XLNX_ZYNQMP_NUM_GEMS 4 |
3bade2a9 | 43 | #define XLNX_ZYNQMP_NUM_UARTS 2 |
33108e9f | 44 | #define XLNX_ZYNQMP_NUM_SDHCI 2 |
02d07eb4 | 45 | #define XLNX_ZYNQMP_NUM_SPIS 2 |
04965bca FI |
46 | #define XLNX_ZYNQMP_NUM_GDMA_CH 8 |
47 | #define XLNX_ZYNQMP_NUM_ADMA_CH 8 | |
f0a902f7 | 48 | |
babc1f30 FI |
49 | #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 |
50 | #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 | |
51 | #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 | |
52 | ||
6675d719 AF |
53 | #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 |
54 | #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 | |
55 | #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 | |
56 | ||
75b749af | 57 | #define XLNX_ZYNQMP_GIC_REGIONS 6 |
7729e1f4 PC |
58 | |
59 | /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets | |
60 | * and under-decodes the 64k region. This mirrors the 4k regions to every 4k | |
61 | * aligned address in the 64k region. To implement each GIC region needs a | |
62 | * number of memory region aliases. | |
63 | */ | |
64 | ||
52c16b45 | 65 | #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 |
75b749af | 66 | #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) |
7729e1f4 | 67 | |
dc3b89ef AF |
68 | #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull |
69 | ||
70 | #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull | |
71 | #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull | |
72 | ||
73 | #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ | |
74 | XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) | |
75 | ||
f0a902f7 PC |
76 | typedef struct XlnxZynqMPState { |
77 | /*< private >*/ | |
78 | DeviceState parent_obj; | |
79 | ||
80 | /*< public >*/ | |
816fd397 LM |
81 | CPUClusterState apu_cluster; |
82 | CPUClusterState rpu_cluster; | |
2e5577bc | 83 | ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; |
b58850e7 | 84 | ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; |
7729e1f4 PC |
85 | GICState gic; |
86 | MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; | |
dc3b89ef | 87 | |
6675d719 AF |
88 | MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; |
89 | ||
dc3b89ef AF |
90 | MemoryRegion *ddr_ram; |
91 | MemoryRegion ddr_ram_low, ddr_ram_high; | |
92 | ||
14ca2e46 | 93 | CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; |
3bade2a9 | 94 | CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; |
6fdf3282 | 95 | SysbusAHCIState sata; |
33108e9f | 96 | SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; |
02d07eb4 | 97 | XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; |
babc1f30 | 98 | XlnxZynqMPQSPIPS qspi; |
b93dbcdd FK |
99 | XlnxDPState dp; |
100 | XlnxDPDMAState dpdma; | |
0ab7bbc7 | 101 | XlnxZynqMPIPI ipi; |
08b2f15e | 102 | XlnxZynqMPRTC rtc; |
04965bca FI |
103 | XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; |
104 | XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; | |
6396a193 PC |
105 | |
106 | char *boot_cpu; | |
107 | ARMCPU *boot_cpu_ptr; | |
37d42473 EI |
108 | |
109 | /* Has the ARM Security extensions? */ | |
110 | bool secure; | |
1946809e AF |
111 | /* Has the ARM Virtualization extensions? */ |
112 | bool virt; | |
6ed92b14 EI |
113 | /* Has the RPU subsystem? */ |
114 | bool has_rpu; | |
f0a902f7 PC |
115 | } XlnxZynqMPState; |
116 | ||
117 | #define XLNX_ZYNQMP_H | |
118 | #endif |