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Commit | Line | Data |
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cb9c377f | 1 | #ifndef HW_FLASH_H |
175de524 | 2 | #define HW_FLASH_H |
cb9c377f | 3 | |
87ecb68b | 4 | /* NOR flash devices */ |
cfe5f011 | 5 | |
022c62cb | 6 | #include "exec/memory.h" |
cfe5f011 | 7 | |
16434065 MA |
8 | /* pflash_cfi01.c */ |
9 | ||
e7b62741 | 10 | #define TYPE_PFLASH_CFI01 "cfi.pflash01" |
81c7db72 MA |
11 | #define PFLASH_CFI01(obj) \ |
12 | OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01) | |
1a004c7f | 13 | |
16434065 | 14 | typedef struct PFlashCFI01 PFlashCFI01; |
87ecb68b | 15 | |
16434065 | 16 | PFlashCFI01 *pflash_cfi01_register(hwaddr base, |
940d5b13 | 17 | const char *name, |
16434065 MA |
18 | hwaddr size, |
19 | BlockBackend *blk, | |
20 | uint32_t sector_len, int nb_blocs, | |
21 | int width, | |
22 | uint16_t id0, uint16_t id1, | |
23 | uint16_t id2, uint16_t id3, | |
24 | int be); | |
25 | MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl); | |
88eeee0a AZ |
26 | |
27 | /* pflash_cfi02.c */ | |
16434065 | 28 | |
e7b62741 | 29 | #define TYPE_PFLASH_CFI02 "cfi.pflash02" |
81c7db72 MA |
30 | #define PFLASH_CFI02(obj) \ |
31 | OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02) | |
16434065 MA |
32 | |
33 | typedef struct PFlashCFI02 PFlashCFI02; | |
34 | ||
35 | PFlashCFI02 *pflash_cfi02_register(hwaddr base, | |
940d5b13 | 36 | const char *name, |
16434065 MA |
37 | hwaddr size, |
38 | BlockBackend *blk, | |
39 | uint32_t sector_len, int nb_blocs, | |
40 | int nb_mappings, | |
41 | int width, | |
42 | uint16_t id0, uint16_t id1, | |
43 | uint16_t id2, uint16_t id3, | |
44 | uint16_t unlock_addr0, | |
45 | uint16_t unlock_addr1, | |
46 | int be); | |
cfe5f011 | 47 | |
87ecb68b | 48 | /* nand.c */ |
4be74634 | 49 | DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id); |
d4220389 | 50 | void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, |
51db57f7 | 51 | uint8_t ce, uint8_t wp, uint8_t gnd); |
d4220389 JR |
52 | void nand_getpins(DeviceState *dev, int *rb); |
53 | void nand_setio(DeviceState *dev, uint32_t value); | |
54 | uint32_t nand_getio(DeviceState *dev); | |
55 | uint32_t nand_getbuswidth(DeviceState *dev); | |
87ecb68b PB |
56 | |
57 | #define NAND_MFR_TOSHIBA 0x98 | |
58 | #define NAND_MFR_SAMSUNG 0xec | |
59 | #define NAND_MFR_FUJITSU 0x04 | |
60 | #define NAND_MFR_NATIONAL 0x8f | |
61 | #define NAND_MFR_RENESAS 0x07 | |
62 | #define NAND_MFR_STMICRO 0x20 | |
63 | #define NAND_MFR_HYNIX 0xad | |
64 | #define NAND_MFR_MICRON 0x2c | |
65 | ||
7e7c5e4c | 66 | /* onenand.c */ |
500954e3 | 67 | void *onenand_raw_otp(DeviceState *onenand_device); |
7e7c5e4c | 68 | |
87ecb68b | 69 | /* ecc.c */ |
bc24a225 | 70 | typedef struct { |
87ecb68b PB |
71 | uint8_t cp; /* Column parity */ |
72 | uint16_t lp[2]; /* Line parity */ | |
73 | uint16_t count; | |
bc24a225 | 74 | } ECCState; |
87ecb68b | 75 | |
bc24a225 PB |
76 | uint8_t ecc_digest(ECCState *s, uint8_t sample); |
77 | void ecc_reset(ECCState *s); | |
34f9f0b5 | 78 | extern VMStateDescription vmstate_ecc_state; |
cb9c377f PB |
79 | |
80 | #endif |