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Commit | Line | Data |
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cb9c377f | 1 | #ifndef HW_FLASH_H |
175de524 | 2 | #define HW_FLASH_H |
cb9c377f | 3 | |
87ecb68b | 4 | /* NOR flash devices */ |
cfe5f011 | 5 | |
d4842052 | 6 | #include "exec/hwaddr.h" |
cfe5f011 | 7 | |
16434065 MA |
8 | /* pflash_cfi01.c */ |
9 | ||
e7b62741 | 10 | #define TYPE_PFLASH_CFI01 "cfi.pflash01" |
81c7db72 MA |
11 | #define PFLASH_CFI01(obj) \ |
12 | OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01) | |
1a004c7f | 13 | |
16434065 | 14 | typedef struct PFlashCFI01 PFlashCFI01; |
87ecb68b | 15 | |
16434065 | 16 | PFlashCFI01 *pflash_cfi01_register(hwaddr base, |
940d5b13 | 17 | const char *name, |
16434065 MA |
18 | hwaddr size, |
19 | BlockBackend *blk, | |
ce14710f | 20 | uint32_t sector_len, |
16434065 MA |
21 | int width, |
22 | uint16_t id0, uint16_t id1, | |
23 | uint16_t id2, uint16_t id3, | |
24 | int be); | |
e60cf765 | 25 | BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl); |
16434065 | 26 | MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl); |
2d731dbd | 27 | void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo); |
88eeee0a AZ |
28 | |
29 | /* pflash_cfi02.c */ | |
16434065 | 30 | |
e7b62741 | 31 | #define TYPE_PFLASH_CFI02 "cfi.pflash02" |
81c7db72 MA |
32 | #define PFLASH_CFI02(obj) \ |
33 | OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02) | |
16434065 MA |
34 | |
35 | typedef struct PFlashCFI02 PFlashCFI02; | |
36 | ||
37 | PFlashCFI02 *pflash_cfi02_register(hwaddr base, | |
940d5b13 | 38 | const char *name, |
16434065 MA |
39 | hwaddr size, |
40 | BlockBackend *blk, | |
ce14710f | 41 | uint32_t sector_len, |
16434065 MA |
42 | int nb_mappings, |
43 | int width, | |
44 | uint16_t id0, uint16_t id1, | |
45 | uint16_t id2, uint16_t id3, | |
46 | uint16_t unlock_addr0, | |
47 | uint16_t unlock_addr1, | |
48 | int be); | |
cfe5f011 | 49 | |
87ecb68b | 50 | /* nand.c */ |
4be74634 | 51 | DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id); |
d4220389 | 52 | void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, |
51db57f7 | 53 | uint8_t ce, uint8_t wp, uint8_t gnd); |
d4220389 JR |
54 | void nand_getpins(DeviceState *dev, int *rb); |
55 | void nand_setio(DeviceState *dev, uint32_t value); | |
56 | uint32_t nand_getio(DeviceState *dev); | |
57 | uint32_t nand_getbuswidth(DeviceState *dev); | |
87ecb68b PB |
58 | |
59 | #define NAND_MFR_TOSHIBA 0x98 | |
60 | #define NAND_MFR_SAMSUNG 0xec | |
61 | #define NAND_MFR_FUJITSU 0x04 | |
62 | #define NAND_MFR_NATIONAL 0x8f | |
63 | #define NAND_MFR_RENESAS 0x07 | |
64 | #define NAND_MFR_STMICRO 0x20 | |
65 | #define NAND_MFR_HYNIX 0xad | |
66 | #define NAND_MFR_MICRON 0x2c | |
67 | ||
7e7c5e4c | 68 | /* onenand.c */ |
500954e3 | 69 | void *onenand_raw_otp(DeviceState *onenand_device); |
7e7c5e4c | 70 | |
87ecb68b | 71 | /* ecc.c */ |
bc24a225 | 72 | typedef struct { |
87ecb68b PB |
73 | uint8_t cp; /* Column parity */ |
74 | uint16_t lp[2]; /* Line parity */ | |
75 | uint16_t count; | |
bc24a225 | 76 | } ECCState; |
87ecb68b | 77 | |
bc24a225 PB |
78 | uint8_t ecc_digest(ECCState *s, uint8_t sample); |
79 | void ecc_reset(ECCState *s); | |
34f9f0b5 | 80 | extern VMStateDescription vmstate_ecc_state; |
cb9c377f PB |
81 | |
82 | #endif |