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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
3979fca4 | 24 | #include "disas/dis-asm.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
66b9b43c | 26 | #include "exec/memattrs.h" |
9af23989 | 27 | #include "qapi/qapi-types-run-state.h" |
48151859 | 28 | #include "qemu/bitmap.h" |
068a5ea0 | 29 | #include "qemu/rcu_queue.h" |
bdc44640 | 30 | #include "qemu/queue.h" |
1de7afc9 | 31 | #include "qemu/thread.h" |
54cb65d8 | 32 | #include "qemu/plugin.h" |
dd83b06a | 33 | |
b5ba1cc6 QN |
34 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
35 | void *opaque); | |
c72bf468 | 36 | |
577f42c0 AF |
37 | /** |
38 | * vaddr: | |
39 | * Type wide enough to contain any #target_ulong virtual address. | |
40 | */ | |
41 | typedef uint64_t vaddr; | |
42 | #define VADDR_PRId PRId64 | |
43 | #define VADDR_PRIu PRIu64 | |
44 | #define VADDR_PRIo PRIo64 | |
45 | #define VADDR_PRIx PRIx64 | |
46 | #define VADDR_PRIX PRIX64 | |
47 | #define VADDR_MAX UINT64_MAX | |
48 | ||
dd83b06a AF |
49 | /** |
50 | * SECTION:cpu | |
51 | * @section_id: QEMU-cpu | |
52 | * @title: CPU Class | |
53 | * @short_description: Base class for all CPUs | |
54 | */ | |
55 | ||
56 | #define TYPE_CPU "cpu" | |
57 | ||
0d6d1ab4 AF |
58 | /* Since this macro is used a lot in hot code paths and in conjunction with |
59 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
60 | * an unchecked cast. | |
61 | */ | |
62 | #define CPU(obj) ((CPUState *)(obj)) | |
63 | ||
dd83b06a AF |
64 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
65 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
66 | ||
b35399bb SS |
67 | typedef enum MMUAccessType { |
68 | MMU_DATA_LOAD = 0, | |
69 | MMU_DATA_STORE = 1, | |
70 | MMU_INST_FETCH = 2 | |
71 | } MMUAccessType; | |
72 | ||
568496c0 | 73 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 74 | |
bdf7ae5b AF |
75 | struct TranslationBlock; |
76 | ||
dd83b06a AF |
77 | /** |
78 | * CPUClass: | |
2b8c2754 AF |
79 | * @class_by_name: Callback to map -cpu command line model name to an |
80 | * instantiatable CPU type. | |
94a444b2 | 81 | * @parse_features: Callback to parse command line arguments. |
91b1df8c | 82 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 83 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 84 | * @do_interrupt: Callback for interrupt handling. |
93e22326 | 85 | * @do_unaligned_access: Callback for unaligned access handling, if |
52bf9771 | 86 | * the target defines #TARGET_ALIGNED_ONLY. |
0dff0939 PM |
87 | * @do_transaction_failed: Callback for handling failed memory transactions |
88 | * (ie bus faults or external aborts; not MMU faults) | |
c08295d4 PM |
89 | * @virtio_is_big_endian: Callback to return %true if a CPU which supports |
90 | * runtime configurable endianness is currently big-endian. Non-configurable | |
91 | * CPUs can use the default implementation of this method. This method should | |
92 | * not be used by any callers other than the pre-1.0 virtio devices. | |
f3659eee | 93 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
94 | * @dump_state: Callback for dumping state. |
95 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 96 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 97 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 98 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
42f6ed91 JS |
99 | * @set_pc: Callback for setting the Program Counter register. This |
100 | * should have the semantics used by the target architecture when | |
101 | * setting the PC from a source such as an ELF file entry point; | |
102 | * for example on Arm it will also set the Thumb mode bit based | |
103 | * on the least significant bit of the new PC value. | |
104 | * If the target behaviour here is anything other than "set | |
105 | * the PC register to the value passed in" then the target must | |
106 | * also implement the synchronize_from_tb hook. | |
bdf7ae5b | 107 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
42f6ed91 JS |
108 | * #TranslationBlock. This is called when we abandon execution |
109 | * of a TB before starting it, and must set all parts of the CPU | |
110 | * state which the previous TB in the chain may not have updated. | |
111 | * This always includes at least the program counter; some targets | |
112 | * will need to do more. If this hook is not implemented then the | |
113 | * default is to call @set_pc(tb->pc). | |
da6bbf85 RH |
114 | * @tlb_fill: Callback for handling a softmmu tlb miss or user-only |
115 | * address fault. For system mode, if the access is valid, call | |
116 | * tlb_set_page and return true; if the access is invalid, and | |
117 | * probe is true, return false; otherwise raise an exception and | |
118 | * do not return. For user-only mode, always raise an exception | |
119 | * and do not return. | |
00b941e5 | 120 | * @get_phys_page_debug: Callback for obtaining a physical address. |
1dc6fb1f PM |
121 | * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the |
122 | * associated memory transaction attributes to use for the access. | |
123 | * CPUs which use memory transaction attributes should implement this | |
124 | * instead of get_phys_page_debug. | |
d7f25a9e PM |
125 | * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for |
126 | * a memory access with the specified memory transaction attributes. | |
5b50e790 AF |
127 | * @gdb_read_register: Callback for letting GDB read a register. |
128 | * @gdb_write_register: Callback for letting GDB write a register. | |
568496c0 SF |
129 | * @debug_check_watchpoint: Callback: return true if the architectural |
130 | * watchpoint whose address has matched should really fire. | |
86025ee4 | 131 | * @debug_excp_handler: Callback for handling debug exceptions. |
c08295d4 PM |
132 | * @write_elf64_note: Callback for writing a CPU-specific ELF note to a |
133 | * 64-bit VM coredump. | |
134 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
135 | * note to a 32-bit VM coredump. | |
136 | * @write_elf32_note: Callback for writing a CPU-specific ELF note to a | |
137 | * 32-bit VM coredump. | |
138 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
139 | * note to a 32-bit VM coredump. | |
b170fce3 | 140 | * @vmsd: State description for migration. |
a0e372f0 | 141 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 142 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
143 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
144 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
145 | * @gdb_arch_name: Optional callback that returns the architecture name known |
146 | * to GDB. The caller must free the returned string with g_free. | |
200bf5b7 AB |
147 | * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the |
148 | * gdb stub. Returns a pointer to the XML contents for the specified XML file | |
149 | * or NULL if the CPU doesn't have a dynamically generated content for it. | |
cffe7b32 RH |
150 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
151 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
9585db68 | 152 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. |
37b9de46 | 153 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
154 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
155 | * address before attempting to match it against watchpoints. | |
dd83b06a AF |
156 | * |
157 | * Represents a CPU family or model. | |
158 | */ | |
159 | typedef struct CPUClass { | |
160 | /*< private >*/ | |
961f8395 | 161 | DeviceClass parent_class; |
dd83b06a AF |
162 | /*< public >*/ |
163 | ||
2b8c2754 | 164 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 165 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 166 | |
91b1df8c | 167 | int reset_dump_flags; |
8c2e1b00 | 168 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 169 | void (*do_interrupt)(CPUState *cpu); |
93e22326 | 170 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
b35399bb SS |
171 | MMUAccessType access_type, |
172 | int mmu_idx, uintptr_t retaddr); | |
0dff0939 PM |
173 | void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, |
174 | unsigned size, MMUAccessType access_type, | |
175 | int mmu_idx, MemTxAttrs attrs, | |
176 | MemTxResult response, uintptr_t retaddr); | |
bf7663c4 | 177 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
178 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
179 | uint8_t *buf, int len, bool is_write); | |
90c84c56 | 180 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
c86f106b | 181 | GuestPanicInformation* (*get_crash_info)(CPUState *cpu); |
11cb6c15 | 182 | void (*dump_statistics)(CPUState *cpu, int flags); |
997395d3 | 183 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 184 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
185 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
186 | Error **errp); | |
f45748f1 | 187 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 188 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
da6bbf85 RH |
189 | bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, |
190 | MMUAccessType access_type, int mmu_idx, | |
191 | bool probe, uintptr_t retaddr); | |
00b941e5 | 192 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
1dc6fb1f PM |
193 | hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, |
194 | MemTxAttrs *attrs); | |
d7f25a9e | 195 | int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); |
a010bdbe | 196 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
5b50e790 | 197 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
568496c0 | 198 | bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); |
86025ee4 | 199 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 200 | |
c72bf468 JF |
201 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
202 | int cpuid, void *opaque); | |
203 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
204 | void *opaque); | |
205 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
206 | int cpuid, void *opaque); | |
207 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
208 | void *opaque); | |
a0e372f0 | 209 | |
8a9358cc | 210 | const VMStateDescription *vmsd; |
5b24c641 | 211 | const char *gdb_core_xml_file; |
b3820e6c | 212 | gchar * (*gdb_arch_name)(CPUState *cpu); |
200bf5b7 | 213 | const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); |
cffe7b32 RH |
214 | void (*cpu_exec_enter)(CPUState *cpu); |
215 | void (*cpu_exec_exit)(CPUState *cpu); | |
9585db68 | 216 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); |
37b9de46 PC |
217 | |
218 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
40612000 | 219 | vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); |
55c3ceef RH |
220 | void (*tcg_initialize)(void); |
221 | ||
222 | /* Keep non-pointer data at the end to minimize holes. */ | |
223 | int gdb_num_core_regs; | |
224 | bool gdb_stop_before_watchpoint; | |
dd83b06a AF |
225 | } CPUClass; |
226 | ||
5e140196 RH |
227 | /* |
228 | * Low 16 bits: number of cycles left, used only in icount mode. | |
229 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs | |
230 | * for this CPU and return to its top level loop (even in non-icount mode). | |
231 | * This allows a single read-compare-cbranch-write sequence to test | |
232 | * for both decrementer underflow and exceptions. | |
233 | */ | |
234 | typedef union IcountDecr { | |
235 | uint32_t u32; | |
236 | struct { | |
28ecfd7a | 237 | #ifdef HOST_WORDS_BIGENDIAN |
5e140196 RH |
238 | uint16_t high; |
239 | uint16_t low; | |
28ecfd7a | 240 | #else |
5e140196 RH |
241 | uint16_t low; |
242 | uint16_t high; | |
28ecfd7a | 243 | #endif |
5e140196 RH |
244 | } u16; |
245 | } IcountDecr; | |
28ecfd7a | 246 | |
f0c3c505 AF |
247 | typedef struct CPUBreakpoint { |
248 | vaddr pc; | |
249 | int flags; /* BP_* */ | |
250 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
251 | } CPUBreakpoint; | |
252 | ||
568496c0 | 253 | struct CPUWatchpoint { |
ff4700b0 | 254 | vaddr vaddr; |
05068c0d | 255 | vaddr len; |
08225676 | 256 | vaddr hitaddr; |
66b9b43c | 257 | MemTxAttrs hitattrs; |
ff4700b0 AF |
258 | int flags; /* BP_* */ |
259 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 260 | }; |
ff4700b0 | 261 | |
2f3a57ee AB |
262 | #ifdef CONFIG_PLUGIN |
263 | /* | |
264 | * For plugins we sometime need to save the resolved iotlb data before | |
265 | * the memory regions get moved around by io_writex. | |
266 | */ | |
267 | typedef struct SavedIOTLB { | |
268 | hwaddr addr; | |
269 | MemoryRegionSection *section; | |
270 | hwaddr mr_offset; | |
271 | } SavedIOTLB; | |
272 | #endif | |
273 | ||
a60f24b5 | 274 | struct KVMState; |
f7575c96 | 275 | struct kvm_run; |
a60f24b5 | 276 | |
b0cb0a66 VP |
277 | struct hax_vcpu_state; |
278 | ||
8cd70437 AF |
279 | #define TB_JMP_CACHE_BITS 12 |
280 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
281 | ||
4b4629d9 | 282 | /* work queue */ |
14e6fe12 PB |
283 | |
284 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
285 | * hosts in a single parameter | |
286 | */ | |
287 | typedef union { | |
288 | int host_int; | |
289 | unsigned long host_ulong; | |
290 | void *host_ptr; | |
291 | vaddr target_ptr; | |
292 | } run_on_cpu_data; | |
293 | ||
294 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
295 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
296 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
297 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
298 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
299 | ||
300 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
301 | ||
d148d90e | 302 | struct qemu_work_item; |
4b4629d9 | 303 | |
0b8497f0 | 304 | #define CPU_UNSET_NUMA_NODE_ID -1 |
d01c05c9 | 305 | #define CPU_TRACE_DSTATE_MAX_EVENTS 32 |
0b8497f0 | 306 | |
dd83b06a AF |
307 | /** |
308 | * CPUState: | |
55e5c285 | 309 | * @cpu_index: CPU index (informative). |
7ea7b9ad PM |
310 | * @cluster_index: Identifies which cluster this CPU is in. |
311 | * For boards which don't define clusters or for "loose" CPUs not assigned | |
312 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will | |
313 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER | |
314 | * QOM parent. | |
ce3960eb AF |
315 | * @nr_cores: Number of cores within this CPU package. |
316 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
317 | * @running: #true if CPU is currently running (lockless). |
318 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 319 | * valid under cpu_list_lock. |
61a46217 | 320 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
321 | * @interrupt_request: Indicates a pending interrupt request. |
322 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 323 | * @stop: Indicates a pending stop request. |
f324e766 | 324 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 325 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 326 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 327 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 328 | * @icount_extra: Instructions until next timer event. |
414b15c9 PB |
329 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
330 | * requires that IO only be performed on the last instruction of a TB | |
331 | * so that interrupts take effect immediately. | |
32857f4d PM |
332 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
333 | * AddressSpaces this CPU has) | |
12ebc9a7 | 334 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
335 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
336 | * only have a single AddressSpace | |
c05efcb1 | 337 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
5e140196 | 338 | * @icount_decr_ptr: Pointer to IcountDecr field within subclass. |
eac8b355 | 339 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 340 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 341 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 342 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 343 | * @opaque: User data. |
93afeade | 344 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
8737c51c | 345 | * @kvm_fd: vCPU file descriptor for KVM. |
0c0fcc20 EC |
346 | * @work_mutex: Lock to prevent multiple access to @work_list. |
347 | * @work_list: List of pending asynchronous work. | |
d4381116 LV |
348 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
349 | * to @trace_dstate). | |
48151859 | 350 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
54cb65d8 | 351 | * @plugin_mask: Plugin event bitmap. Modified only via async work. |
ed860129 PM |
352 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
353 | * flag of the same name: allows the board to suppress calling of the | |
354 | * CPU do_transaction_failed hook function. | |
dd83b06a AF |
355 | * |
356 | * State of one CPU core or thread. | |
357 | */ | |
358 | struct CPUState { | |
359 | /*< private >*/ | |
961f8395 | 360 | DeviceState parent_obj; |
dd83b06a AF |
361 | /*< public >*/ |
362 | ||
ce3960eb AF |
363 | int nr_cores; |
364 | int nr_threads; | |
365 | ||
814e612e | 366 | struct QemuThread *thread; |
bcba2a72 AF |
367 | #ifdef _WIN32 |
368 | HANDLE hThread; | |
369 | #endif | |
9f09e18a | 370 | int thread_id; |
c265e976 | 371 | bool running, has_waiter; |
f5c121b8 | 372 | struct QemuCond *halt_cond; |
216fc9a4 | 373 | bool thread_kicked; |
61a46217 | 374 | bool created; |
4fdeee7c | 375 | bool stop; |
f324e766 | 376 | bool stopped; |
4c055ab5 | 377 | bool unplug; |
bac05aa9 | 378 | bool crash_occurred; |
e0c38211 | 379 | bool exit_request; |
cfbc3c60 | 380 | bool in_exclusive_context; |
9b990ee5 | 381 | uint32_t cflags_next_tb; |
8d04fb55 | 382 | /* updates protected by BQL */ |
259186a7 | 383 | uint32_t interrupt_request; |
ed2803da | 384 | int singlestep_enabled; |
e4cd9657 | 385 | int64_t icount_budget; |
efee7340 | 386 | int64_t icount_extra; |
9c09a251 | 387 | uint64_t random_seed; |
6f03bef0 | 388 | sigjmp_buf jmp_env; |
bcba2a72 | 389 | |
376692b9 | 390 | QemuMutex work_mutex; |
0c0fcc20 | 391 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
376692b9 | 392 | |
32857f4d | 393 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 394 | int num_ases; |
09daed84 | 395 | AddressSpace *as; |
6731d864 | 396 | MemoryRegion *memory; |
09daed84 | 397 | |
c05efcb1 | 398 | void *env_ptr; /* CPUArchState */ |
5e140196 | 399 | IcountDecr *icount_decr_ptr; |
7d7500d9 | 400 | |
f3ced3c5 | 401 | /* Accessed in parallel; all accesses must be atomic */ |
8cd70437 | 402 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
7d7500d9 | 403 | |
eac8b355 | 404 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 405 | int gdb_num_regs; |
35143f01 | 406 | int gdb_num_g_regs; |
bdc44640 | 407 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 408 | |
f0c3c505 | 409 | /* ice debug support */ |
b58deb34 | 410 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
f0c3c505 | 411 | |
b58deb34 | 412 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
ff4700b0 AF |
413 | CPUWatchpoint *watchpoint_hit; |
414 | ||
0429a971 AF |
415 | void *opaque; |
416 | ||
93afeade AF |
417 | /* In order to avoid passing too many arguments to the MMIO helpers, |
418 | * we store some rarely used information in the CPU context. | |
419 | */ | |
420 | uintptr_t mem_io_pc; | |
93afeade | 421 | |
8737c51c | 422 | int kvm_fd; |
a60f24b5 | 423 | struct KVMState *kvm_state; |
f7575c96 | 424 | struct kvm_run *kvm_run; |
8737c51c | 425 | |
d01c05c9 | 426 | /* Used for events with 'vcpu' and *without* the 'disabled' properties */ |
d4381116 | 427 | DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); |
d01c05c9 | 428 | DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); |
48151859 | 429 | |
54cb65d8 EC |
430 | DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); |
431 | ||
2f3a57ee | 432 | #ifdef CONFIG_PLUGIN |
54cb65d8 | 433 | GArray *plugin_mem_cbs; |
2f3a57ee AB |
434 | /* saved iotlb data from io_writex */ |
435 | SavedIOTLB saved_iotlb; | |
436 | #endif | |
54cb65d8 | 437 | |
f5df5baf | 438 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e | 439 | int cpu_index; |
7ea7b9ad | 440 | int cluster_index; |
6fda014e | 441 | uint32_t halted; |
99df7dce | 442 | uint32_t can_do_io; |
6fda014e | 443 | int32_t exception_index; |
7e4fb26d | 444 | |
99f31832 SAGDR |
445 | /* shared by kvm, hax and hvf */ |
446 | bool vcpu_dirty; | |
447 | ||
2adcc85d JH |
448 | /* Used to keep track of an outstanding cpu throttle thread for migration |
449 | * autoconverge | |
450 | */ | |
451 | bool throttle_thread_scheduled; | |
452 | ||
ed860129 PM |
453 | bool ignore_memory_transaction_failures; |
454 | ||
b0cb0a66 | 455 | struct hax_vcpu_state *hax_vcpu; |
e3b9ca81 | 456 | |
c97d6d2c | 457 | int hvf_fd; |
1f871c5e PM |
458 | |
459 | /* track IOMMUs whose translations we've cached in the TCG TLB */ | |
460 | GArray *iommu_notifiers; | |
dd83b06a AF |
461 | }; |
462 | ||
f481ee2d PB |
463 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
464 | extern CPUTailQ cpus; | |
465 | ||
068a5ea0 EC |
466 | #define first_cpu QTAILQ_FIRST_RCU(&cpus) |
467 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) | |
468 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) | |
bdc44640 | 469 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
068a5ea0 | 470 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) |
182735ef | 471 | |
f240eb6f | 472 | extern __thread CPUState *current_cpu; |
4917cf44 | 473 | |
f3ced3c5 EC |
474 | static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) |
475 | { | |
476 | unsigned int i; | |
477 | ||
478 | for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { | |
479 | atomic_set(&cpu->tb_jmp_cache[i], NULL); | |
480 | } | |
481 | } | |
482 | ||
8d4e9146 FK |
483 | /** |
484 | * qemu_tcg_mttcg_enabled: | |
485 | * Check whether we are running MultiThread TCG or not. | |
486 | * | |
487 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
488 | */ | |
489 | extern bool mttcg_enabled; | |
490 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
491 | ||
444d5590 AF |
492 | /** |
493 | * cpu_paging_enabled: | |
494 | * @cpu: The CPU whose state is to be inspected. | |
495 | * | |
496 | * Returns: %true if paging is enabled, %false otherwise. | |
497 | */ | |
498 | bool cpu_paging_enabled(const CPUState *cpu); | |
499 | ||
a23bbfda AF |
500 | /** |
501 | * cpu_get_memory_mapping: | |
502 | * @cpu: The CPU whose memory mappings are to be obtained. | |
503 | * @list: Where to write the memory mappings to. | |
504 | * @errp: Pointer for reporting an #Error. | |
505 | */ | |
506 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
507 | Error **errp); | |
508 | ||
cfe35d48 PMD |
509 | #if !defined(CONFIG_USER_ONLY) |
510 | ||
c72bf468 JF |
511 | /** |
512 | * cpu_write_elf64_note: | |
513 | * @f: pointer to a function that writes memory to a file | |
514 | * @cpu: The CPU whose memory is to be dumped | |
515 | * @cpuid: ID number of the CPU | |
516 | * @opaque: pointer to the CPUState struct | |
517 | */ | |
518 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
519 | int cpuid, void *opaque); | |
520 | ||
521 | /** | |
522 | * cpu_write_elf64_qemunote: | |
523 | * @f: pointer to a function that writes memory to a file | |
524 | * @cpu: The CPU whose memory is to be dumped | |
525 | * @cpuid: ID number of the CPU | |
526 | * @opaque: pointer to the CPUState struct | |
527 | */ | |
528 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
529 | void *opaque); | |
530 | ||
531 | /** | |
532 | * cpu_write_elf32_note: | |
533 | * @f: pointer to a function that writes memory to a file | |
534 | * @cpu: The CPU whose memory is to be dumped | |
535 | * @cpuid: ID number of the CPU | |
536 | * @opaque: pointer to the CPUState struct | |
537 | */ | |
538 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
539 | int cpuid, void *opaque); | |
540 | ||
541 | /** | |
542 | * cpu_write_elf32_qemunote: | |
543 | * @f: pointer to a function that writes memory to a file | |
544 | * @cpu: The CPU whose memory is to be dumped | |
545 | * @cpuid: ID number of the CPU | |
546 | * @opaque: pointer to the CPUState struct | |
547 | */ | |
548 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
549 | void *opaque); | |
dd83b06a | 550 | |
c86f106b AN |
551 | /** |
552 | * cpu_get_crash_info: | |
553 | * @cpu: The CPU to get crash information for | |
554 | * | |
555 | * Gets the previously saved crash information. | |
556 | * Caller is responsible for freeing the data. | |
557 | */ | |
558 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
559 | ||
cfe35d48 PMD |
560 | #endif /* !CONFIG_USER_ONLY */ |
561 | ||
878096ee AF |
562 | /** |
563 | * CPUDumpFlags: | |
564 | * @CPU_DUMP_CODE: | |
565 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
566 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
567 | */ | |
568 | enum CPUDumpFlags { | |
569 | CPU_DUMP_CODE = 0x00010000, | |
570 | CPU_DUMP_FPU = 0x00020000, | |
571 | CPU_DUMP_CCOP = 0x00040000, | |
572 | }; | |
573 | ||
574 | /** | |
575 | * cpu_dump_state: | |
576 | * @cpu: The CPU whose state is to be dumped. | |
90c84c56 | 577 | * @f: If non-null, dump to this stream, else to current print sink. |
878096ee AF |
578 | * |
579 | * Dumps CPU state. | |
580 | */ | |
90c84c56 | 581 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
878096ee AF |
582 | |
583 | /** | |
584 | * cpu_dump_statistics: | |
585 | * @cpu: The CPU whose state is to be dumped. | |
878096ee AF |
586 | * @flags: Flags what to dump. |
587 | * | |
11cb6c15 MA |
588 | * Dump CPU statistics to the current monitor if we have one, else to |
589 | * stdout. | |
878096ee | 590 | */ |
11cb6c15 | 591 | void cpu_dump_statistics(CPUState *cpu, int flags); |
878096ee | 592 | |
00b941e5 | 593 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
594 | /** |
595 | * cpu_get_phys_page_attrs_debug: | |
596 | * @cpu: The CPU to obtain the physical page address for. | |
597 | * @addr: The virtual address. | |
598 | * @attrs: Updated on return with the memory transaction attributes to use | |
599 | * for this access. | |
600 | * | |
601 | * Obtains the physical page corresponding to a virtual one, together | |
602 | * with the corresponding memory transaction attributes to use for the access. | |
603 | * Use it only for debugging because no protection checks are done. | |
604 | * | |
605 | * Returns: Corresponding physical page address or -1 if no page found. | |
606 | */ | |
607 | static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
608 | MemTxAttrs *attrs) | |
609 | { | |
610 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
611 | ||
612 | if (cc->get_phys_page_attrs_debug) { | |
613 | return cc->get_phys_page_attrs_debug(cpu, addr, attrs); | |
614 | } | |
615 | /* Fallback for CPUs which don't implement the _attrs_ hook */ | |
616 | *attrs = MEMTXATTRS_UNSPECIFIED; | |
617 | return cc->get_phys_page_debug(cpu, addr); | |
618 | } | |
619 | ||
00b941e5 AF |
620 | /** |
621 | * cpu_get_phys_page_debug: | |
622 | * @cpu: The CPU to obtain the physical page address for. | |
623 | * @addr: The virtual address. | |
624 | * | |
625 | * Obtains the physical page corresponding to a virtual one. | |
626 | * Use it only for debugging because no protection checks are done. | |
627 | * | |
628 | * Returns: Corresponding physical page address or -1 if no page found. | |
629 | */ | |
630 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
631 | { | |
1dc6fb1f | 632 | MemTxAttrs attrs = {}; |
00b941e5 | 633 | |
1dc6fb1f | 634 | return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); |
00b941e5 | 635 | } |
d7f25a9e PM |
636 | |
637 | /** cpu_asidx_from_attrs: | |
638 | * @cpu: CPU | |
639 | * @attrs: memory transaction attributes | |
640 | * | |
641 | * Returns the address space index specifying the CPU AddressSpace | |
642 | * to use for a memory access with the given transaction attributes. | |
643 | */ | |
644 | static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) | |
645 | { | |
646 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
9c8c334b | 647 | int ret = 0; |
d7f25a9e PM |
648 | |
649 | if (cc->asidx_from_attrs) { | |
9c8c334b RH |
650 | ret = cc->asidx_from_attrs(cpu, attrs); |
651 | assert(ret < cpu->num_ases && ret >= 0); | |
d7f25a9e | 652 | } |
9c8c334b | 653 | return ret; |
d7f25a9e | 654 | } |
cfe35d48 PMD |
655 | |
656 | #endif /* CONFIG_USER_ONLY */ | |
00b941e5 | 657 | |
267f685b PB |
658 | /** |
659 | * cpu_list_add: | |
660 | * @cpu: The CPU to be added to the list of CPUs. | |
661 | */ | |
662 | void cpu_list_add(CPUState *cpu); | |
663 | ||
664 | /** | |
665 | * cpu_list_remove: | |
666 | * @cpu: The CPU to be removed from the list of CPUs. | |
667 | */ | |
668 | void cpu_list_remove(CPUState *cpu); | |
669 | ||
dd83b06a AF |
670 | /** |
671 | * cpu_reset: | |
672 | * @cpu: The CPU whose state is to be reset. | |
673 | */ | |
674 | void cpu_reset(CPUState *cpu); | |
675 | ||
2b8c2754 AF |
676 | /** |
677 | * cpu_class_by_name: | |
678 | * @typename: The CPU base type. | |
679 | * @cpu_model: The model string without any parameters. | |
680 | * | |
681 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
682 | * | |
683 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
684 | */ | |
685 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
686 | ||
3c72234c IM |
687 | /** |
688 | * cpu_create: | |
689 | * @typename: The CPU type. | |
690 | * | |
691 | * Instantiates a CPU and realizes the CPU. | |
692 | * | |
693 | * Returns: A #CPUState or %NULL if an error occurred. | |
694 | */ | |
695 | CPUState *cpu_create(const char *typename); | |
696 | ||
697 | /** | |
c1c8cfe5 EH |
698 | * parse_cpu_option: |
699 | * @cpu_option: The -cpu option including optional parameters. | |
3c72234c IM |
700 | * |
701 | * processes optional parameters and registers them as global properties | |
702 | * | |
4482e05c IM |
703 | * Returns: type of CPU to create or prints error and terminates process |
704 | * if an error occurred. | |
3c72234c | 705 | */ |
c1c8cfe5 | 706 | const char *parse_cpu_option(const char *cpu_option); |
9262685b | 707 | |
3993c6bd | 708 | /** |
8c2e1b00 | 709 | * cpu_has_work: |
3993c6bd AF |
710 | * @cpu: The vCPU to check. |
711 | * | |
712 | * Checks whether the CPU has work to do. | |
713 | * | |
714 | * Returns: %true if the CPU has work, %false otherwise. | |
715 | */ | |
8c2e1b00 AF |
716 | static inline bool cpu_has_work(CPUState *cpu) |
717 | { | |
718 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
719 | ||
720 | g_assert(cc->has_work); | |
721 | return cc->has_work(cpu); | |
722 | } | |
3993c6bd | 723 | |
60e82579 AF |
724 | /** |
725 | * qemu_cpu_is_self: | |
726 | * @cpu: The vCPU to check against. | |
727 | * | |
728 | * Checks whether the caller is executing on the vCPU thread. | |
729 | * | |
730 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
731 | */ | |
732 | bool qemu_cpu_is_self(CPUState *cpu); | |
733 | ||
c08d7424 AF |
734 | /** |
735 | * qemu_cpu_kick: | |
736 | * @cpu: The vCPU to kick. | |
737 | * | |
738 | * Kicks @cpu's thread. | |
739 | */ | |
740 | void qemu_cpu_kick(CPUState *cpu); | |
741 | ||
2fa45344 AF |
742 | /** |
743 | * cpu_is_stopped: | |
744 | * @cpu: The CPU to check. | |
745 | * | |
746 | * Checks whether the CPU is stopped. | |
747 | * | |
748 | * Returns: %true if run state is not running or if artificially stopped; | |
749 | * %false otherwise. | |
750 | */ | |
751 | bool cpu_is_stopped(CPUState *cpu); | |
752 | ||
d148d90e SF |
753 | /** |
754 | * do_run_on_cpu: | |
755 | * @cpu: The vCPU to run on. | |
756 | * @func: The function to be executed. | |
757 | * @data: Data to pass to the function. | |
758 | * @mutex: Mutex to release while waiting for @func to run. | |
759 | * | |
760 | * Used internally in the implementation of run_on_cpu. | |
761 | */ | |
14e6fe12 | 762 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
763 | QemuMutex *mutex); |
764 | ||
f100f0b3 AF |
765 | /** |
766 | * run_on_cpu: | |
767 | * @cpu: The vCPU to run on. | |
768 | * @func: The function to be executed. | |
769 | * @data: Data to pass to the function. | |
770 | * | |
771 | * Schedules the function @func for execution on the vCPU @cpu. | |
772 | */ | |
14e6fe12 | 773 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 774 | |
3c02270d CV |
775 | /** |
776 | * async_run_on_cpu: | |
777 | * @cpu: The vCPU to run on. | |
778 | * @func: The function to be executed. | |
779 | * @data: Data to pass to the function. | |
780 | * | |
781 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
782 | */ | |
14e6fe12 | 783 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 784 | |
53f5ed95 PB |
785 | /** |
786 | * async_safe_run_on_cpu: | |
787 | * @cpu: The vCPU to run on. | |
788 | * @func: The function to be executed. | |
789 | * @data: Data to pass to the function. | |
790 | * | |
791 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
792 | * while all other vCPUs are sleeping. | |
793 | * | |
794 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
795 | * BQL. | |
796 | */ | |
14e6fe12 | 797 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 798 | |
cfbc3c60 EC |
799 | /** |
800 | * cpu_in_exclusive_context() | |
801 | * @cpu: The vCPU to check | |
802 | * | |
803 | * Returns true if @cpu is an exclusive context, for example running | |
804 | * something which has previously been queued via async_safe_run_on_cpu(). | |
805 | */ | |
806 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) | |
807 | { | |
808 | return cpu->in_exclusive_context; | |
809 | } | |
810 | ||
38d8f5c8 AF |
811 | /** |
812 | * qemu_get_cpu: | |
813 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
814 | * | |
815 | * Gets a CPU matching @index. | |
816 | * | |
817 | * Returns: The CPU or %NULL if there is no matching CPU. | |
818 | */ | |
819 | CPUState *qemu_get_cpu(int index); | |
820 | ||
69e5ff06 IM |
821 | /** |
822 | * cpu_exists: | |
823 | * @id: Guest-exposed CPU ID to lookup. | |
824 | * | |
825 | * Search for CPU with specified ID. | |
826 | * | |
827 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
828 | */ | |
829 | bool cpu_exists(int64_t id); | |
830 | ||
5ce46cb3 EH |
831 | /** |
832 | * cpu_by_arch_id: | |
833 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
834 | * | |
835 | * Get a CPU with matching @id. | |
836 | * | |
837 | * Returns: The CPU or %NULL if there is no matching CPU. | |
838 | */ | |
839 | CPUState *cpu_by_arch_id(int64_t id); | |
840 | ||
c3affe56 AF |
841 | #ifndef CONFIG_USER_ONLY |
842 | ||
843 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
844 | ||
845 | extern CPUInterruptHandler cpu_interrupt_handler; | |
846 | ||
847 | /** | |
848 | * cpu_interrupt: | |
849 | * @cpu: The CPU to set an interrupt on. | |
7e63bc38 | 850 | * @mask: The interrupts to set. |
c3affe56 AF |
851 | * |
852 | * Invokes the interrupt handler. | |
853 | */ | |
854 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
855 | { | |
856 | cpu_interrupt_handler(cpu, mask); | |
857 | } | |
858 | ||
859 | #else /* USER_ONLY */ | |
860 | ||
861 | void cpu_interrupt(CPUState *cpu, int mask); | |
862 | ||
863 | #endif /* USER_ONLY */ | |
864 | ||
47507383 TH |
865 | #ifdef NEED_CPU_H |
866 | ||
93e22326 | 867 | #ifdef CONFIG_SOFTMMU |
93e22326 | 868 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
b35399bb SS |
869 | MMUAccessType access_type, |
870 | int mmu_idx, uintptr_t retaddr) | |
93e22326 PB |
871 | { |
872 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
873 | ||
b35399bb | 874 | cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); |
93e22326 | 875 | } |
0dff0939 PM |
876 | |
877 | static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | |
878 | vaddr addr, unsigned size, | |
879 | MMUAccessType access_type, | |
880 | int mmu_idx, MemTxAttrs attrs, | |
881 | MemTxResult response, | |
882 | uintptr_t retaddr) | |
883 | { | |
884 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
885 | ||
ed860129 | 886 | if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { |
0dff0939 PM |
887 | cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, |
888 | mmu_idx, attrs, response, retaddr); | |
889 | } | |
890 | } | |
c658b94f AF |
891 | #endif |
892 | ||
47507383 TH |
893 | #endif /* NEED_CPU_H */ |
894 | ||
2991b890 PC |
895 | /** |
896 | * cpu_set_pc: | |
897 | * @cpu: The CPU to set the program counter for. | |
898 | * @addr: Program counter value. | |
899 | * | |
900 | * Sets the program counter for a CPU. | |
901 | */ | |
902 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
903 | { | |
904 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
905 | ||
906 | cc->set_pc(cpu, addr); | |
907 | } | |
908 | ||
d8ed887b AF |
909 | /** |
910 | * cpu_reset_interrupt: | |
911 | * @cpu: The CPU to clear the interrupt on. | |
912 | * @mask: The interrupt mask to clear. | |
913 | * | |
914 | * Resets interrupts on the vCPU @cpu. | |
915 | */ | |
916 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
917 | ||
60a3e17a AF |
918 | /** |
919 | * cpu_exit: | |
920 | * @cpu: The CPU to exit. | |
921 | * | |
922 | * Requests the CPU @cpu to exit execution. | |
923 | */ | |
924 | void cpu_exit(CPUState *cpu); | |
925 | ||
2993683b IM |
926 | /** |
927 | * cpu_resume: | |
928 | * @cpu: The CPU to resume. | |
929 | * | |
930 | * Resumes CPU, i.e. puts CPU into runnable state. | |
931 | */ | |
932 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 933 | |
4c055ab5 GZ |
934 | /** |
935 | * cpu_remove: | |
936 | * @cpu: The CPU to remove. | |
937 | * | |
938 | * Requests the CPU to be removed. | |
939 | */ | |
940 | void cpu_remove(CPUState *cpu); | |
941 | ||
2c579042 BR |
942 | /** |
943 | * cpu_remove_sync: | |
944 | * @cpu: The CPU to remove. | |
945 | * | |
946 | * Requests the CPU to be removed and waits till it is removed. | |
947 | */ | |
948 | void cpu_remove_sync(CPUState *cpu); | |
949 | ||
d148d90e SF |
950 | /** |
951 | * process_queued_cpu_work() - process all items on CPU work queue | |
952 | * @cpu: The CPU which work queue to process. | |
953 | */ | |
954 | void process_queued_cpu_work(CPUState *cpu); | |
955 | ||
ab129972 PB |
956 | /** |
957 | * cpu_exec_start: | |
958 | * @cpu: The CPU for the current thread. | |
959 | * | |
960 | * Record that a CPU has started execution and can be interrupted with | |
961 | * cpu_exit. | |
962 | */ | |
963 | void cpu_exec_start(CPUState *cpu); | |
964 | ||
965 | /** | |
966 | * cpu_exec_end: | |
967 | * @cpu: The CPU for the current thread. | |
968 | * | |
969 | * Record that a CPU has stopped execution and exclusive sections | |
970 | * can be executed without interrupting it. | |
971 | */ | |
972 | void cpu_exec_end(CPUState *cpu); | |
973 | ||
974 | /** | |
975 | * start_exclusive: | |
976 | * | |
977 | * Wait for a concurrent exclusive section to end, and then start | |
978 | * a section of work that is run while other CPUs are not running | |
979 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
980 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
981 | * during the exclusive section go to sleep until this CPU calls | |
982 | * end_exclusive. | |
ab129972 PB |
983 | */ |
984 | void start_exclusive(void); | |
985 | ||
986 | /** | |
987 | * end_exclusive: | |
988 | * | |
989 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
990 | */ |
991 | void end_exclusive(void); | |
992 | ||
c643bed9 AF |
993 | /** |
994 | * qemu_init_vcpu: | |
995 | * @cpu: The vCPU to initialize. | |
996 | * | |
997 | * Initializes a vCPU. | |
998 | */ | |
999 | void qemu_init_vcpu(CPUState *cpu); | |
1000 | ||
3825b28f AF |
1001 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
1002 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
1003 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
1004 | ||
1005 | /** | |
1006 | * cpu_single_step: | |
1007 | * @cpu: CPU to the flags for. | |
1008 | * @enabled: Flags to enable. | |
1009 | * | |
1010 | * Enables or disables single-stepping for @cpu. | |
1011 | */ | |
1012 | void cpu_single_step(CPUState *cpu, int enabled); | |
1013 | ||
b3310ab3 AF |
1014 | /* Breakpoint/watchpoint flags */ |
1015 | #define BP_MEM_READ 0x01 | |
1016 | #define BP_MEM_WRITE 0x02 | |
1017 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
1018 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 1019 | /* 0x08 currently unused */ |
b3310ab3 AF |
1020 | #define BP_GDB 0x10 |
1021 | #define BP_CPU 0x20 | |
b933066a | 1022 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
1023 | #define BP_WATCHPOINT_HIT_READ 0x40 |
1024 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
1025 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
1026 | |
1027 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
1028 | CPUBreakpoint **breakpoint); | |
1029 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
1030 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
1031 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
1032 | ||
b933066a RH |
1033 | /* Return true if PC matches an installed breakpoint. */ |
1034 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
1035 | { | |
1036 | CPUBreakpoint *bp; | |
1037 | ||
1038 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
1039 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
1040 | if (bp->pc == pc && (bp->flags & mask)) { | |
1041 | return true; | |
1042 | } | |
1043 | } | |
1044 | } | |
1045 | return false; | |
1046 | } | |
1047 | ||
74841f04 RH |
1048 | #ifdef CONFIG_USER_ONLY |
1049 | static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
1050 | int flags, CPUWatchpoint **watchpoint) | |
1051 | { | |
1052 | return -ENOSYS; | |
1053 | } | |
1054 | ||
1055 | static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
1056 | vaddr len, int flags) | |
1057 | { | |
1058 | return -ENOSYS; | |
1059 | } | |
1060 | ||
1061 | static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, | |
1062 | CPUWatchpoint *wp) | |
1063 | { | |
1064 | } | |
1065 | ||
1066 | static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
1067 | { | |
1068 | } | |
0026348b DH |
1069 | |
1070 | static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, | |
1071 | MemTxAttrs atr, int fl, uintptr_t ra) | |
1072 | { | |
1073 | } | |
56ad8b00 RH |
1074 | |
1075 | static inline int cpu_watchpoint_address_matches(CPUState *cpu, | |
1076 | vaddr addr, vaddr len) | |
1077 | { | |
1078 | return 0; | |
1079 | } | |
74841f04 | 1080 | #else |
75a34036 AF |
1081 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
1082 | int flags, CPUWatchpoint **watchpoint); | |
1083 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
1084 | vaddr len, int flags); | |
1085 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
1086 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
390734a4 RH |
1087 | |
1088 | /** | |
1089 | * cpu_check_watchpoint: | |
1090 | * @cpu: cpu context | |
1091 | * @addr: guest virtual address | |
1092 | * @len: access length | |
1093 | * @attrs: memory access attributes | |
1094 | * @flags: watchpoint access type | |
1095 | * @ra: unwind return address | |
1096 | * | |
1097 | * Check for a watchpoint hit in [addr, addr+len) of the type | |
1098 | * specified by @flags. Exit via exception with a hit. | |
1099 | */ | |
0026348b DH |
1100 | void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, |
1101 | MemTxAttrs attrs, int flags, uintptr_t ra); | |
390734a4 RH |
1102 | |
1103 | /** | |
1104 | * cpu_watchpoint_address_matches: | |
1105 | * @cpu: cpu context | |
1106 | * @addr: guest virtual address | |
1107 | * @len: access length | |
1108 | * | |
1109 | * Return the watchpoint flags that apply to [addr, addr+len). | |
1110 | * If no watchpoint is registered for the range, the result is 0. | |
1111 | */ | |
56ad8b00 | 1112 | int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); |
74841f04 | 1113 | #endif |
75a34036 | 1114 | |
63c91552 PB |
1115 | /** |
1116 | * cpu_get_address_space: | |
1117 | * @cpu: CPU to get address space from | |
1118 | * @asidx: index identifying which address space to get | |
1119 | * | |
1120 | * Return the requested address space of this CPU. @asidx | |
1121 | * specifies which address space to read. | |
1122 | */ | |
1123 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
1124 | ||
a47dddd7 AF |
1125 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
1126 | GCC_FMT_ATTR(2, 3); | |
c7e002c5 | 1127 | extern Property cpu_common_props[]; |
39e329e3 | 1128 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 1129 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 1130 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1131 | |
c95ac103 TH |
1132 | /** |
1133 | * target_words_bigendian: | |
1134 | * Returns true if the (default) endianness of the target is big endian, | |
1135 | * false otherwise. Note that in target-specific code, you can use | |
1136 | * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common | |
1137 | * code should normally never need to know about the endianness of the | |
1138 | * target, so please do *not* use this function unless you know very well | |
1139 | * what you are doing! | |
1140 | */ | |
1141 | bool target_words_bigendian(void); | |
1142 | ||
47507383 TH |
1143 | #ifdef NEED_CPU_H |
1144 | ||
1a1562f5 | 1145 | #ifdef CONFIG_SOFTMMU |
8a9358cc | 1146 | extern const VMStateDescription vmstate_cpu_common; |
1a1562f5 AF |
1147 | #else |
1148 | #define vmstate_cpu_common vmstate_dummy | |
1149 | #endif | |
1150 | ||
1151 | #define VMSTATE_CPU() { \ | |
1152 | .name = "parent_obj", \ | |
1153 | .size = sizeof(CPUState), \ | |
1154 | .vmsd = &vmstate_cpu_common, \ | |
1155 | .flags = VMS_STRUCT, \ | |
1156 | .offset = 0, \ | |
1157 | } | |
1158 | ||
47507383 TH |
1159 | #endif /* NEED_CPU_H */ |
1160 | ||
a07f953e | 1161 | #define UNASSIGNED_CPU_INDEX -1 |
7ea7b9ad | 1162 | #define UNASSIGNED_CLUSTER_INDEX -1 |
a07f953e | 1163 | |
dd83b06a | 1164 | #endif |