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[mirror_qemu.git] / include / hw / core / cpu.h
CommitLineData
dd83b06a
AF
1/*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20#ifndef QEMU_CPU_H
21#define QEMU_CPU_H
22
961f8395 23#include "hw/qdev-core.h"
3979fca4 24#include "disas/dis-asm.h"
06445fbd 25#include "exec/cpu-common.h"
c658b94f 26#include "exec/hwaddr.h"
66b9b43c 27#include "exec/memattrs.h"
9af23989 28#include "qapi/qapi-types-run-state.h"
48151859 29#include "qemu/bitmap.h"
068a5ea0 30#include "qemu/rcu_queue.h"
bdc44640 31#include "qemu/queue.h"
1de7afc9 32#include "qemu/thread.h"
aa4cf6eb 33#include "qemu/plugin-event.h"
db1015e9 34#include "qom/object.h"
dd83b06a 35
b5ba1cc6
QN
36typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
37 void *opaque);
c72bf468 38
dd83b06a
AF
39/**
40 * SECTION:cpu
41 * @section_id: QEMU-cpu
42 * @title: CPU Class
43 * @short_description: Base class for all CPUs
44 */
45
46#define TYPE_CPU "cpu"
47
0d6d1ab4
AF
48/* Since this macro is used a lot in hot code paths and in conjunction with
49 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
50 * an unchecked cast.
51 */
52#define CPU(obj) ((CPUState *)(obj))
53
6fbdff87
AB
54/*
55 * The class checkers bring in CPU_GET_CLASS() which is potentially
56 * expensive given the eventual call to
57 * object_class_dynamic_cast_assert(). Because of this the CPUState
58 * has a cached value for the class in cs->cc which is set up in
59 * cpu_exec_realizefn() for use in hot code paths.
60 */
db1015e9 61typedef struct CPUClass CPUClass;
8110fa1d
EH
62DECLARE_CLASS_CHECKERS(CPUClass, CPU,
63 TYPE_CPU)
dd83b06a 64
9295b1aa
PMD
65/**
66 * OBJECT_DECLARE_CPU_TYPE:
67 * @CpuInstanceType: instance struct name
68 * @CpuClassType: class struct name
69 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
70 *
71 * This macro is typically used in "cpu-qom.h" header file, and will:
72 *
73 * - create the typedefs for the CPU object and class structs
74 * - register the type for use with g_autoptr
75 * - provide three standard type cast functions
76 *
77 * The object struct and class struct need to be declared manually.
78 */
79#define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
b36e239e
PMD
80 typedef struct ArchCPU CpuInstanceType; \
81 OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
9295b1aa 82
b35399bb
SS
83typedef enum MMUAccessType {
84 MMU_DATA_LOAD = 0,
85 MMU_DATA_STORE = 1,
86 MMU_INST_FETCH = 2
58e8f1f6 87#define MMU_ACCESS_COUNT 3
b35399bb
SS
88} MMUAccessType;
89
568496c0 90typedef struct CPUWatchpoint CPUWatchpoint;
dd83b06a 91
78271684
CF
92/* see tcg-cpu-ops.h */
93struct TCGCPUOps;
e9e51b71 94
fb6916dd
CF
95/* see accel-cpu.h */
96struct AccelCPUClass;
97
8b80bd28
PMD
98/* see sysemu-cpu-ops.h */
99struct SysemuCPUOps;
100
dd83b06a
AF
101/**
102 * CPUClass:
2b8c2754
AF
103 * @class_by_name: Callback to map -cpu command line model name to an
104 * instantiatable CPU type.
94a444b2 105 * @parse_features: Callback to parse command line arguments.
91b1df8c 106 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
8c2e1b00 107 * @has_work: Callback for checking if there is work to do.
f3659eee 108 * @memory_rw_debug: Callback for GDB memory access.
878096ee 109 * @dump_state: Callback for dumping state.
5503da4a
TH
110 * @query_cpu_fast:
111 * Fill in target specific information for the "query-cpus-fast"
112 * QAPI call.
997395d3 113 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
42f6ed91
JS
114 * @set_pc: Callback for setting the Program Counter register. This
115 * should have the semantics used by the target architecture when
116 * setting the PC from a source such as an ELF file entry point;
117 * for example on Arm it will also set the Thumb mode bit based
118 * on the least significant bit of the new PC value.
119 * If the target behaviour here is anything other than "set
120 * the PC register to the value passed in" then the target must
121 * also implement the synchronize_from_tb hook.
e4fdf9df
RH
122 * @get_pc: Callback for getting the Program Counter register.
123 * As above, with the semantics of the target architecture.
5b50e790
AF
124 * @gdb_read_register: Callback for letting GDB read a register.
125 * @gdb_write_register: Callback for letting GDB write a register.
5bc31e94
RH
126 * @gdb_adjust_breakpoint: Callback for adjusting the address of a
127 * breakpoint. Used by AVR to handle a gdb mis-feature with
128 * its Harvard architecture split code and data.
a0e372f0 129 * @gdb_num_core_regs: Number of core registers accessible to GDB.
5b24c641 130 * @gdb_core_xml_file: File name for core registers GDB XML description.
2472b6c0
PM
131 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
132 * before the insn which triggers a watchpoint rather than after it.
b3820e6c
DH
133 * @gdb_arch_name: Optional callback that returns the architecture name known
134 * to GDB. The caller must free the returned string with g_free.
200bf5b7
AB
135 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
136 * gdb stub. Returns a pointer to the XML contents for the specified XML file
137 * or NULL if the CPU doesn't have a dynamically generated content for it.
37b9de46 138 * @disas_set_info: Setup architecture specific components of disassembly info
40612000
JB
139 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
140 * address before attempting to match it against watchpoints.
61ad65d0
RH
141 * @deprecation_note: If this CPUClass is deprecated, this field provides
142 * related information.
dd83b06a
AF
143 *
144 * Represents a CPU family or model.
145 */
db1015e9 146struct CPUClass {
dd83b06a 147 /*< private >*/
961f8395 148 DeviceClass parent_class;
dd83b06a
AF
149 /*< public >*/
150
2b8c2754 151 ObjectClass *(*class_by_name)(const char *cpu_model);
62a48a2a 152 void (*parse_features)(const char *typename, char *str, Error **errp);
2b8c2754 153
8c2e1b00 154 bool (*has_work)(CPUState *cpu);
f3659eee
AF
155 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
156 uint8_t *buf, int len, bool is_write);
90c84c56 157 void (*dump_state)(CPUState *cpu, FILE *, int flags);
5503da4a 158 void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value);
997395d3 159 int64_t (*get_arch_id)(CPUState *cpu);
f45748f1 160 void (*set_pc)(CPUState *cpu, vaddr value);
e4fdf9df 161 vaddr (*get_pc)(CPUState *cpu);
a010bdbe 162 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
5b50e790 163 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
5bc31e94 164 vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
b170fce3 165
5b24c641 166 const char *gdb_core_xml_file;
b3820e6c 167 gchar * (*gdb_arch_name)(CPUState *cpu);
200bf5b7 168 const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
37b9de46
PC
169
170 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
55c3ceef 171
61ad65d0 172 const char *deprecation_note;
fb6916dd 173 struct AccelCPUClass *accel_cpu;
e9e51b71 174
8b80bd28
PMD
175 /* when system emulation is not available, this pointer is NULL */
176 const struct SysemuCPUOps *sysemu_ops;
177
78271684 178 /* when TCG is not available, this pointer is NULL */
11906557 179 const struct TCGCPUOps *tcg_ops;
cc3f2be6
CF
180
181 /*
182 * if not NULL, this is called in order for the CPUClass to initialize
183 * class data that depends on the accelerator, see accel/accel-common.c.
184 */
185 void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
dc29f474
RH
186
187 /*
188 * Keep non-pointer data at the end to minimize holes.
189 */
190 int reset_dump_flags;
191 int gdb_num_core_regs;
192 bool gdb_stop_before_watchpoint;
db1015e9 193};
dd83b06a 194
5e140196
RH
195/*
196 * Low 16 bits: number of cycles left, used only in icount mode.
197 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
198 * for this CPU and return to its top level loop (even in non-icount mode).
199 * This allows a single read-compare-cbranch-write sequence to test
200 * for both decrementer underflow and exceptions.
201 */
202typedef union IcountDecr {
203 uint32_t u32;
204 struct {
e03b5686 205#if HOST_BIG_ENDIAN
5e140196
RH
206 uint16_t high;
207 uint16_t low;
28ecfd7a 208#else
5e140196
RH
209 uint16_t low;
210 uint16_t high;
28ecfd7a 211#endif
5e140196
RH
212 } u16;
213} IcountDecr;
28ecfd7a 214
f0c3c505
AF
215typedef struct CPUBreakpoint {
216 vaddr pc;
217 int flags; /* BP_* */
218 QTAILQ_ENTRY(CPUBreakpoint) entry;
219} CPUBreakpoint;
220
568496c0 221struct CPUWatchpoint {
ff4700b0 222 vaddr vaddr;
05068c0d 223 vaddr len;
08225676 224 vaddr hitaddr;
66b9b43c 225 MemTxAttrs hitattrs;
ff4700b0
AF
226 int flags; /* BP_* */
227 QTAILQ_ENTRY(CPUWatchpoint) entry;
568496c0 228};
ff4700b0 229
c5ffd16b 230#ifdef CONFIG_PLUGIN
2f3a57ee
AB
231/*
232 * For plugins we sometime need to save the resolved iotlb data before
233 * the memory regions get moved around by io_writex.
234 */
235typedef struct SavedIOTLB {
2f3a57ee
AB
236 MemoryRegionSection *section;
237 hwaddr mr_offset;
238} SavedIOTLB;
239#endif
240
a60f24b5 241struct KVMState;
f7575c96 242struct kvm_run;
a60f24b5 243
4b4629d9 244/* work queue */
14e6fe12
PB
245
246/* The union type allows passing of 64 bit target pointers on 32 bit
247 * hosts in a single parameter
248 */
249typedef union {
250 int host_int;
251 unsigned long host_ulong;
252 void *host_ptr;
253 vaddr target_ptr;
254} run_on_cpu_data;
255
256#define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
257#define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
258#define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
259#define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
260#define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
261
262typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
263
d148d90e 264struct qemu_work_item;
4b4629d9 265
0b8497f0
IM
266#define CPU_UNSET_NUMA_NODE_ID -1
267
dd83b06a
AF
268/**
269 * CPUState:
55e5c285 270 * @cpu_index: CPU index (informative).
7ea7b9ad
PM
271 * @cluster_index: Identifies which cluster this CPU is in.
272 * For boards which don't define clusters or for "loose" CPUs not assigned
273 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
274 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
275 * QOM parent.
a371975e
PMD
276 * Under TCG this value is propagated to @tcg_cflags.
277 * See TranslationBlock::TCG CF_CLUSTER_MASK.
6cc9d67c 278 * @tcg_cflags: Pre-computed cflags for this cpu.
ce3960eb
AF
279 * @nr_cores: Number of cores within this CPU package.
280 * @nr_threads: Number of threads within this CPU.
c265e976
PB
281 * @running: #true if CPU is currently running (lockless).
282 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
ab129972 283 * valid under cpu_list_lock.
61a46217 284 * @created: Indicates whether the CPU thread has been successfully created.
259186a7
AF
285 * @interrupt_request: Indicates a pending interrupt request.
286 * @halted: Nonzero if the CPU is in suspended state.
4fdeee7c 287 * @stop: Indicates a pending stop request.
f324e766 288 * @stopped: Indicates the CPU has been artificially stopped.
4c055ab5 289 * @unplug: Indicates a pending CPU unplug request.
bac05aa9 290 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
ed2803da 291 * @singlestep_enabled: Flags for single-stepping.
efee7340 292 * @icount_extra: Instructions until next timer event.
414b15c9
PB
293 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
294 * requires that IO only be performed on the last instruction of a TB
295 * so that interrupts take effect immediately.
32857f4d
PM
296 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
297 * AddressSpaces this CPU has)
12ebc9a7 298 * @num_ases: number of CPUAddressSpaces in @cpu_ases
32857f4d
PM
299 * @as: Pointer to the first AddressSpace, for the convenience of targets which
300 * only have a single AddressSpace
c05efcb1 301 * @env_ptr: Pointer to subclass-specific CPUArchState field.
5e140196 302 * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
eac8b355 303 * @gdb_regs: Additional GDB registers.
a0e372f0 304 * @gdb_num_regs: Number of total registers accessible to GDB.
35143f01 305 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
182735ef 306 * @next_cpu: Next CPU sharing TB cache.
0429a971 307 * @opaque: User data.
93afeade 308 * @mem_io_pc: Host Program Counter at which the memory was accessed.
f861b3f3 309 * @accel: Pointer to accelerator specific state.
8737c51c 310 * @kvm_fd: vCPU file descriptor for KVM.
0c0fcc20
EC
311 * @work_mutex: Lock to prevent multiple access to @work_list.
312 * @work_list: List of pending asynchronous work.
d4381116
LV
313 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
314 * to @trace_dstate).
48151859 315 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
54cb65d8 316 * @plugin_mask: Plugin event bitmap. Modified only via async work.
ed860129
PM
317 * @ignore_memory_transaction_failures: Cached copy of the MachineState
318 * flag of the same name: allows the board to suppress calling of the
319 * CPU do_transaction_failed hook function.
b4420f19
PX
320 * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty
321 * ring is enabled.
322 * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU
323 * dirty ring structure.
dd83b06a
AF
324 *
325 * State of one CPU core or thread.
326 */
327struct CPUState {
328 /*< private >*/
961f8395 329 DeviceState parent_obj;
6fbdff87
AB
330 /* cache to avoid expensive CPU_GET_CLASS */
331 CPUClass *cc;
dd83b06a
AF
332 /*< public >*/
333
ce3960eb
AF
334 int nr_cores;
335 int nr_threads;
336
814e612e 337 struct QemuThread *thread;
bcba2a72 338#ifdef _WIN32
c9923550 339 QemuSemaphore sem;
bcba2a72 340#endif
9f09e18a 341 int thread_id;
c265e976 342 bool running, has_waiter;
f5c121b8 343 struct QemuCond *halt_cond;
216fc9a4 344 bool thread_kicked;
61a46217 345 bool created;
4fdeee7c 346 bool stop;
f324e766 347 bool stopped;
c1b70158
TJB
348
349 /* Should CPU start in powered-off state? */
350 bool start_powered_off;
351
4c055ab5 352 bool unplug;
bac05aa9 353 bool crash_occurred;
e0c38211 354 bool exit_request;
df8a6880 355 int exclusive_context_count;
9b990ee5 356 uint32_t cflags_next_tb;
8d04fb55 357 /* updates protected by BQL */
259186a7 358 uint32_t interrupt_request;
ed2803da 359 int singlestep_enabled;
e4cd9657 360 int64_t icount_budget;
efee7340 361 int64_t icount_extra;
9c09a251 362 uint64_t random_seed;
6f03bef0 363 sigjmp_buf jmp_env;
bcba2a72 364
376692b9 365 QemuMutex work_mutex;
0c0fcc20 366 QSIMPLEQ_HEAD(, qemu_work_item) work_list;
376692b9 367
32857f4d 368 CPUAddressSpace *cpu_ases;
12ebc9a7 369 int num_ases;
09daed84 370 AddressSpace *as;
6731d864 371 MemoryRegion *memory;
09daed84 372
1ea4a06a 373 CPUArchState *env_ptr;
5e140196 374 IcountDecr *icount_decr_ptr;
7d7500d9 375
a976a99a 376 CPUJumpCache *tb_jmp_cache;
7d7500d9 377
eac8b355 378 struct GDBRegisterState *gdb_regs;
a0e372f0 379 int gdb_num_regs;
35143f01 380 int gdb_num_g_regs;
bdc44640 381 QTAILQ_ENTRY(CPUState) node;
d77953b9 382
f0c3c505 383 /* ice debug support */
b58deb34 384 QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
f0c3c505 385
b58deb34 386 QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
ff4700b0
AF
387 CPUWatchpoint *watchpoint_hit;
388
0429a971
AF
389 void *opaque;
390
93afeade
AF
391 /* In order to avoid passing too many arguments to the MMIO helpers,
392 * we store some rarely used information in the CPU context.
393 */
394 uintptr_t mem_io_pc;
93afeade 395
b4420f19 396 /* Only used in KVM */
8737c51c 397 int kvm_fd;
a60f24b5 398 struct KVMState *kvm_state;
f7575c96 399 struct kvm_run *kvm_run;
b4420f19
PX
400 struct kvm_dirty_gfn *kvm_dirty_gfns;
401 uint32_t kvm_fetch_index;
7786ae40 402 uint64_t dirty_pages;
3b6f4852 403 int kvm_vcpu_stats_fd;
8737c51c 404
bd688fc9
EGE
405 /* Use by accel-block: CPU is executing an ioctl() */
406 QemuLockCnt in_ioctl_lock;
407
54cb65d8
EC
408 DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX);
409
2f3a57ee 410#ifdef CONFIG_PLUGIN
54cb65d8 411 GArray *plugin_mem_cbs;
2f3a57ee
AB
412 /* saved iotlb data from io_writex */
413 SavedIOTLB saved_iotlb;
c5ffd16b 414#endif
54cb65d8 415
f5df5baf 416 /* TODO Move common fields from CPUArchState here. */
6fda014e 417 int cpu_index;
7ea7b9ad 418 int cluster_index;
6cc9d67c 419 uint32_t tcg_cflags;
6fda014e 420 uint32_t halted;
99df7dce 421 uint32_t can_do_io;
6fda014e 422 int32_t exception_index;
7e4fb26d 423
f861b3f3 424 AccelCPUState *accel;
99f31832
SAGDR
425 /* shared by kvm, hax and hvf */
426 bool vcpu_dirty;
427
2adcc85d
JH
428 /* Used to keep track of an outstanding cpu throttle thread for migration
429 * autoconverge
430 */
431 bool throttle_thread_scheduled;
432
baa60983
HH
433 /*
434 * Sleep throttle_us_per_full microseconds once dirty ring is full
435 * if dirty page rate limit is enabled.
436 */
437 int64_t throttle_us_per_full;
438
ed860129
PM
439 bool ignore_memory_transaction_failures;
440
6e8dcacd
RH
441 /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
442 bool prctl_unalign_sigbus;
443
1f871c5e
PM
444 /* track IOMMUs whose translations we've cached in the TCG TLB */
445 GArray *iommu_notifiers;
dd83b06a
AF
446};
447
f481ee2d
PB
448typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
449extern CPUTailQ cpus;
450
068a5ea0
EC
451#define first_cpu QTAILQ_FIRST_RCU(&cpus)
452#define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
453#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
bdc44640 454#define CPU_FOREACH_SAFE(cpu, next_cpu) \
068a5ea0 455 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
182735ef 456
f240eb6f 457extern __thread CPUState *current_cpu;
4917cf44 458
8d4e9146
FK
459/**
460 * qemu_tcg_mttcg_enabled:
461 * Check whether we are running MultiThread TCG or not.
462 *
463 * Returns: %true if we are in MTTCG mode %false otherwise.
464 */
465extern bool mttcg_enabled;
466#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
467
444d5590
AF
468/**
469 * cpu_paging_enabled:
470 * @cpu: The CPU whose state is to be inspected.
471 *
472 * Returns: %true if paging is enabled, %false otherwise.
473 */
474bool cpu_paging_enabled(const CPUState *cpu);
475
a23bbfda
AF
476/**
477 * cpu_get_memory_mapping:
478 * @cpu: The CPU whose memory mappings are to be obtained.
479 * @list: Where to write the memory mappings to.
480 * @errp: Pointer for reporting an #Error.
481 */
482void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
483 Error **errp);
484
cfe35d48
PMD
485#if !defined(CONFIG_USER_ONLY)
486
c72bf468
JF
487/**
488 * cpu_write_elf64_note:
489 * @f: pointer to a function that writes memory to a file
490 * @cpu: The CPU whose memory is to be dumped
491 * @cpuid: ID number of the CPU
492 * @opaque: pointer to the CPUState struct
493 */
494int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
495 int cpuid, void *opaque);
496
497/**
498 * cpu_write_elf64_qemunote:
499 * @f: pointer to a function that writes memory to a file
500 * @cpu: The CPU whose memory is to be dumped
501 * @cpuid: ID number of the CPU
502 * @opaque: pointer to the CPUState struct
503 */
504int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
505 void *opaque);
506
507/**
508 * cpu_write_elf32_note:
509 * @f: pointer to a function that writes memory to a file
510 * @cpu: The CPU whose memory is to be dumped
511 * @cpuid: ID number of the CPU
512 * @opaque: pointer to the CPUState struct
513 */
514int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
515 int cpuid, void *opaque);
516
517/**
518 * cpu_write_elf32_qemunote:
519 * @f: pointer to a function that writes memory to a file
520 * @cpu: The CPU whose memory is to be dumped
521 * @cpuid: ID number of the CPU
522 * @opaque: pointer to the CPUState struct
523 */
524int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
525 void *opaque);
dd83b06a 526
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527/**
528 * cpu_get_crash_info:
529 * @cpu: The CPU to get crash information for
530 *
531 * Gets the previously saved crash information.
532 * Caller is responsible for freeing the data.
533 */
534GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
535
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536#endif /* !CONFIG_USER_ONLY */
537
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538/**
539 * CPUDumpFlags:
540 * @CPU_DUMP_CODE:
541 * @CPU_DUMP_FPU: dump FPU register state, not just integer
542 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
b84694de 543 * @CPU_DUMP_VPU: dump VPU registers
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544 */
545enum CPUDumpFlags {
546 CPU_DUMP_CODE = 0x00010000,
547 CPU_DUMP_FPU = 0x00020000,
548 CPU_DUMP_CCOP = 0x00040000,
b84694de 549 CPU_DUMP_VPU = 0x00080000,
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550};
551
552/**
553 * cpu_dump_state:
554 * @cpu: The CPU whose state is to be dumped.
90c84c56 555 * @f: If non-null, dump to this stream, else to current print sink.
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556 *
557 * Dumps CPU state.
558 */
90c84c56 559void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
878096ee 560
00b941e5 561#ifndef CONFIG_USER_ONLY
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562/**
563 * cpu_get_phys_page_attrs_debug:
564 * @cpu: The CPU to obtain the physical page address for.
565 * @addr: The virtual address.
566 * @attrs: Updated on return with the memory transaction attributes to use
567 * for this access.
568 *
569 * Obtains the physical page corresponding to a virtual one, together
570 * with the corresponding memory transaction attributes to use for the access.
571 * Use it only for debugging because no protection checks are done.
572 *
573 * Returns: Corresponding physical page address or -1 if no page found.
574 */
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575hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
576 MemTxAttrs *attrs);
1dc6fb1f 577
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578/**
579 * cpu_get_phys_page_debug:
580 * @cpu: The CPU to obtain the physical page address for.
581 * @addr: The virtual address.
582 *
583 * Obtains the physical page corresponding to a virtual one.
584 * Use it only for debugging because no protection checks are done.
585 *
586 * Returns: Corresponding physical page address or -1 if no page found.
587 */
a41d3aae 588hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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589
590/** cpu_asidx_from_attrs:
591 * @cpu: CPU
592 * @attrs: memory transaction attributes
593 *
594 * Returns the address space index specifying the CPU AddressSpace
595 * to use for a memory access with the given transaction attributes.
596 */
a41d3aae 597int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
d7f25a9e 598
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599/**
600 * cpu_virtio_is_big_endian:
601 * @cpu: CPU
602
603 * Returns %true if a CPU which supports runtime configurable endianness
604 * is currently big-endian.
605 */
606bool cpu_virtio_is_big_endian(CPUState *cpu);
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607
608#endif /* CONFIG_USER_ONLY */
00b941e5 609
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610/**
611 * cpu_list_add:
612 * @cpu: The CPU to be added to the list of CPUs.
613 */
614void cpu_list_add(CPUState *cpu);
615
616/**
617 * cpu_list_remove:
618 * @cpu: The CPU to be removed from the list of CPUs.
619 */
620void cpu_list_remove(CPUState *cpu);
621
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622/**
623 * cpu_reset:
624 * @cpu: The CPU whose state is to be reset.
625 */
626void cpu_reset(CPUState *cpu);
627
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628/**
629 * cpu_class_by_name:
630 * @typename: The CPU base type.
631 * @cpu_model: The model string without any parameters.
632 *
633 * Looks up a CPU #ObjectClass matching name @cpu_model.
634 *
635 * Returns: A #CPUClass or %NULL if not matching class is found.
636 */
637ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
638
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639/**
640 * cpu_create:
641 * @typename: The CPU type.
642 *
643 * Instantiates a CPU and realizes the CPU.
644 *
645 * Returns: A #CPUState or %NULL if an error occurred.
646 */
647CPUState *cpu_create(const char *typename);
648
649/**
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650 * parse_cpu_option:
651 * @cpu_option: The -cpu option including optional parameters.
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652 *
653 * processes optional parameters and registers them as global properties
654 *
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655 * Returns: type of CPU to create or prints error and terminates process
656 * if an error occurred.
3c72234c 657 */
c1c8cfe5 658const char *parse_cpu_option(const char *cpu_option);
9262685b 659
3993c6bd 660/**
8c2e1b00 661 * cpu_has_work:
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662 * @cpu: The vCPU to check.
663 *
664 * Checks whether the CPU has work to do.
665 *
666 * Returns: %true if the CPU has work, %false otherwise.
667 */
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668static inline bool cpu_has_work(CPUState *cpu)
669{
670 CPUClass *cc = CPU_GET_CLASS(cpu);
671
672 g_assert(cc->has_work);
673 return cc->has_work(cpu);
674}
3993c6bd 675
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676/**
677 * qemu_cpu_is_self:
678 * @cpu: The vCPU to check against.
679 *
680 * Checks whether the caller is executing on the vCPU thread.
681 *
682 * Returns: %true if called from @cpu's thread, %false otherwise.
683 */
684bool qemu_cpu_is_self(CPUState *cpu);
685
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686/**
687 * qemu_cpu_kick:
688 * @cpu: The vCPU to kick.
689 *
690 * Kicks @cpu's thread.
691 */
692void qemu_cpu_kick(CPUState *cpu);
693
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694/**
695 * cpu_is_stopped:
696 * @cpu: The CPU to check.
697 *
698 * Checks whether the CPU is stopped.
699 *
700 * Returns: %true if run state is not running or if artificially stopped;
701 * %false otherwise.
702 */
703bool cpu_is_stopped(CPUState *cpu);
704
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705/**
706 * do_run_on_cpu:
707 * @cpu: The vCPU to run on.
708 * @func: The function to be executed.
709 * @data: Data to pass to the function.
710 * @mutex: Mutex to release while waiting for @func to run.
711 *
712 * Used internally in the implementation of run_on_cpu.
713 */
14e6fe12 714void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
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715 QemuMutex *mutex);
716
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717/**
718 * run_on_cpu:
719 * @cpu: The vCPU to run on.
720 * @func: The function to be executed.
721 * @data: Data to pass to the function.
722 *
723 * Schedules the function @func for execution on the vCPU @cpu.
724 */
14e6fe12 725void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
f100f0b3 726
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727/**
728 * async_run_on_cpu:
729 * @cpu: The vCPU to run on.
730 * @func: The function to be executed.
731 * @data: Data to pass to the function.
732 *
733 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
734 */
14e6fe12 735void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
3c02270d 736
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737/**
738 * async_safe_run_on_cpu:
739 * @cpu: The vCPU to run on.
740 * @func: The function to be executed.
741 * @data: Data to pass to the function.
742 *
743 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
744 * while all other vCPUs are sleeping.
745 *
746 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
747 * BQL.
748 */
14e6fe12 749void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
53f5ed95 750
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751/**
752 * cpu_in_exclusive_context()
753 * @cpu: The vCPU to check
754 *
755 * Returns true if @cpu is an exclusive context, for example running
756 * something which has previously been queued via async_safe_run_on_cpu().
757 */
758static inline bool cpu_in_exclusive_context(const CPUState *cpu)
759{
df8a6880 760 return cpu->exclusive_context_count;
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761}
762
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763/**
764 * qemu_get_cpu:
765 * @index: The CPUState@cpu_index value of the CPU to obtain.
766 *
767 * Gets a CPU matching @index.
768 *
769 * Returns: The CPU or %NULL if there is no matching CPU.
770 */
771CPUState *qemu_get_cpu(int index);
772
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773/**
774 * cpu_exists:
775 * @id: Guest-exposed CPU ID to lookup.
776 *
777 * Search for CPU with specified ID.
778 *
779 * Returns: %true - CPU is found, %false - CPU isn't found.
780 */
781bool cpu_exists(int64_t id);
782
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783/**
784 * cpu_by_arch_id:
785 * @id: Guest-exposed CPU ID of the CPU to obtain.
786 *
787 * Get a CPU with matching @id.
788 *
789 * Returns: The CPU or %NULL if there is no matching CPU.
790 */
791CPUState *cpu_by_arch_id(int64_t id);
792
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793/**
794 * cpu_interrupt:
795 * @cpu: The CPU to set an interrupt on.
7e63bc38 796 * @mask: The interrupts to set.
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797 *
798 * Invokes the interrupt handler.
799 */
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800
801void cpu_interrupt(CPUState *cpu, int mask);
802
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803/**
804 * cpu_set_pc:
805 * @cpu: The CPU to set the program counter for.
806 * @addr: Program counter value.
807 *
808 * Sets the program counter for a CPU.
809 */
810static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
811{
812 CPUClass *cc = CPU_GET_CLASS(cpu);
813
814 cc->set_pc(cpu, addr);
815}
816
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817/**
818 * cpu_reset_interrupt:
819 * @cpu: The CPU to clear the interrupt on.
820 * @mask: The interrupt mask to clear.
821 *
822 * Resets interrupts on the vCPU @cpu.
823 */
824void cpu_reset_interrupt(CPUState *cpu, int mask);
825
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826/**
827 * cpu_exit:
828 * @cpu: The CPU to exit.
829 *
830 * Requests the CPU @cpu to exit execution.
831 */
832void cpu_exit(CPUState *cpu);
833
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834/**
835 * cpu_resume:
836 * @cpu: The CPU to resume.
837 *
838 * Resumes CPU, i.e. puts CPU into runnable state.
839 */
840void cpu_resume(CPUState *cpu);
dd83b06a 841
4c055ab5 842/**
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843 * cpu_remove_sync:
844 * @cpu: The CPU to remove.
845 *
846 * Requests the CPU to be removed and waits till it is removed.
847 */
848void cpu_remove_sync(CPUState *cpu);
849
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850/**
851 * process_queued_cpu_work() - process all items on CPU work queue
852 * @cpu: The CPU which work queue to process.
853 */
854void process_queued_cpu_work(CPUState *cpu);
855
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856/**
857 * cpu_exec_start:
858 * @cpu: The CPU for the current thread.
859 *
860 * Record that a CPU has started execution and can be interrupted with
861 * cpu_exit.
862 */
863void cpu_exec_start(CPUState *cpu);
864
865/**
866 * cpu_exec_end:
867 * @cpu: The CPU for the current thread.
868 *
869 * Record that a CPU has stopped execution and exclusive sections
870 * can be executed without interrupting it.
871 */
872void cpu_exec_end(CPUState *cpu);
873
874/**
875 * start_exclusive:
876 *
877 * Wait for a concurrent exclusive section to end, and then start
878 * a section of work that is run while other CPUs are not running
879 * between cpu_exec_start and cpu_exec_end. CPUs that are running
880 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
881 * during the exclusive section go to sleep until this CPU calls
882 * end_exclusive.
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883 */
884void start_exclusive(void);
885
886/**
887 * end_exclusive:
888 *
889 * Concludes an exclusive execution section started by start_exclusive.
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890 */
891void end_exclusive(void);
892
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893/**
894 * qemu_init_vcpu:
895 * @cpu: The vCPU to initialize.
896 *
897 * Initializes a vCPU.
898 */
899void qemu_init_vcpu(CPUState *cpu);
900
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901#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
902#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
903#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
904
905/**
906 * cpu_single_step:
907 * @cpu: CPU to the flags for.
908 * @enabled: Flags to enable.
909 *
910 * Enables or disables single-stepping for @cpu.
911 */
912void cpu_single_step(CPUState *cpu, int enabled);
913
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914/* Breakpoint/watchpoint flags */
915#define BP_MEM_READ 0x01
916#define BP_MEM_WRITE 0x02
917#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
918#define BP_STOP_BEFORE_ACCESS 0x04
08225676 919/* 0x08 currently unused */
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920#define BP_GDB 0x10
921#define BP_CPU 0x20
b933066a 922#define BP_ANY (BP_GDB | BP_CPU)
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923#define BP_HIT_SHIFT 6
924#define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT)
925#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT)
926#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT)
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927
928int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
929 CPUBreakpoint **breakpoint);
930int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
931void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
932void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
933
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934/* Return true if PC matches an installed breakpoint. */
935static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
936{
937 CPUBreakpoint *bp;
938
939 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
940 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
941 if (bp->pc == pc && (bp->flags & mask)) {
942 return true;
943 }
944 }
945 }
946 return false;
947}
948
87e303de 949#if defined(CONFIG_USER_ONLY)
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950static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
951 int flags, CPUWatchpoint **watchpoint)
952{
953 return -ENOSYS;
954}
955
956static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
957 vaddr len, int flags)
958{
959 return -ENOSYS;
960}
961
962static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
963 CPUWatchpoint *wp)
964{
965}
966
967static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
968{
969}
970#else
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971int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
972 int flags, CPUWatchpoint **watchpoint);
973int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
974 vaddr len, int flags);
975void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
976void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
74841f04 977#endif
75a34036 978
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979/**
980 * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled?
981 * @cs: CPUState pointer
982 *
983 * The memory callbacks are installed if a plugin has instrumented an
984 * instruction for memory. This can be useful to know if you want to
985 * force a slow path for a series of memory accesses.
986 */
987static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu)
988{
989#ifdef CONFIG_PLUGIN
990 return !!cpu->plugin_mem_cbs;
991#else
992 return false;
993#endif
994}
995
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996/**
997 * cpu_get_address_space:
998 * @cpu: CPU to get address space from
999 * @asidx: index identifying which address space to get
1000 *
1001 * Return the requested address space of this CPU. @asidx
1002 * specifies which address space to read.
1003 */
1004AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
1005
8905770b 1006G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
9edc6313 1007 G_GNUC_PRINTF(2, 3);
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1008
1009/* $(top_srcdir)/cpu.c */
995b87de 1010void cpu_class_init_props(DeviceClass *dc);
39e329e3 1011void cpu_exec_initfn(CPUState *cpu);
ce5b1bbf 1012void cpu_exec_realizefn(CPUState *cpu, Error **errp);
7bbc124e 1013void cpu_exec_unrealizefn(CPUState *cpu);
a47dddd7 1014
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1015/**
1016 * target_words_bigendian:
1017 * Returns true if the (default) endianness of the target is big endian,
1018 * false otherwise. Note that in target-specific code, you can use
ee3eb3a7 1019 * TARGET_BIG_ENDIAN directly instead. On the other hand, common
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1020 * code should normally never need to know about the endianness of the
1021 * target, so please do *not* use this function unless you know very well
1022 * what you are doing!
1023 */
1024bool target_words_bigendian(void);
1025
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1026const char *target_name(void);
1027
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1028void page_size_init(void);
1029
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1030#ifdef NEED_CPU_H
1031
75fe97b4 1032#ifndef CONFIG_USER_ONLY
feece4d0 1033
8a9358cc 1034extern const VMStateDescription vmstate_cpu_common;
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1035
1036#define VMSTATE_CPU() { \
1037 .name = "parent_obj", \
1038 .size = sizeof(CPUState), \
1039 .vmsd = &vmstate_cpu_common, \
1040 .flags = VMS_STRUCT, \
1041 .offset = 0, \
1042}
75fe97b4 1043#endif /* !CONFIG_USER_ONLY */
1a1562f5 1044
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1045#endif /* NEED_CPU_H */
1046
a07f953e 1047#define UNASSIGNED_CPU_INDEX -1
7ea7b9ad 1048#define UNASSIGNED_CLUSTER_INDEX -1
a07f953e 1049
dd83b06a 1050#endif