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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
3979fca4 | 24 | #include "disas/dis-asm.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
66b9b43c | 26 | #include "exec/memattrs.h" |
9af23989 | 27 | #include "qapi/qapi-types-run-state.h" |
48151859 | 28 | #include "qemu/bitmap.h" |
068a5ea0 | 29 | #include "qemu/rcu_queue.h" |
bdc44640 | 30 | #include "qemu/queue.h" |
1de7afc9 | 31 | #include "qemu/thread.h" |
54cb65d8 | 32 | #include "qemu/plugin.h" |
db1015e9 | 33 | #include "qom/object.h" |
dd83b06a | 34 | |
b5ba1cc6 QN |
35 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
36 | void *opaque); | |
c72bf468 | 37 | |
577f42c0 AF |
38 | /** |
39 | * vaddr: | |
40 | * Type wide enough to contain any #target_ulong virtual address. | |
41 | */ | |
42 | typedef uint64_t vaddr; | |
43 | #define VADDR_PRId PRId64 | |
44 | #define VADDR_PRIu PRIu64 | |
45 | #define VADDR_PRIo PRIo64 | |
46 | #define VADDR_PRIx PRIx64 | |
47 | #define VADDR_PRIX PRIX64 | |
48 | #define VADDR_MAX UINT64_MAX | |
49 | ||
dd83b06a AF |
50 | /** |
51 | * SECTION:cpu | |
52 | * @section_id: QEMU-cpu | |
53 | * @title: CPU Class | |
54 | * @short_description: Base class for all CPUs | |
55 | */ | |
56 | ||
57 | #define TYPE_CPU "cpu" | |
58 | ||
0d6d1ab4 AF |
59 | /* Since this macro is used a lot in hot code paths and in conjunction with |
60 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
61 | * an unchecked cast. | |
62 | */ | |
63 | #define CPU(obj) ((CPUState *)(obj)) | |
64 | ||
db1015e9 | 65 | typedef struct CPUClass CPUClass; |
8110fa1d EH |
66 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, |
67 | TYPE_CPU) | |
dd83b06a | 68 | |
b35399bb SS |
69 | typedef enum MMUAccessType { |
70 | MMU_DATA_LOAD = 0, | |
71 | MMU_DATA_STORE = 1, | |
72 | MMU_INST_FETCH = 2 | |
73 | } MMUAccessType; | |
74 | ||
568496c0 | 75 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 76 | |
78271684 CF |
77 | /* see tcg-cpu-ops.h */ |
78 | struct TCGCPUOps; | |
e9e51b71 | 79 | |
fb6916dd CF |
80 | /* see accel-cpu.h */ |
81 | struct AccelCPUClass; | |
82 | ||
8b80bd28 PMD |
83 | /* see sysemu-cpu-ops.h */ |
84 | struct SysemuCPUOps; | |
85 | ||
dd83b06a AF |
86 | /** |
87 | * CPUClass: | |
2b8c2754 AF |
88 | * @class_by_name: Callback to map -cpu command line model name to an |
89 | * instantiatable CPU type. | |
94a444b2 | 90 | * @parse_features: Callback to parse command line arguments. |
91b1df8c | 91 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 92 | * @has_work: Callback for checking if there is work to do. |
f3659eee | 93 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee | 94 | * @dump_state: Callback for dumping state. |
997395d3 | 95 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
42f6ed91 JS |
96 | * @set_pc: Callback for setting the Program Counter register. This |
97 | * should have the semantics used by the target architecture when | |
98 | * setting the PC from a source such as an ELF file entry point; | |
99 | * for example on Arm it will also set the Thumb mode bit based | |
100 | * on the least significant bit of the new PC value. | |
101 | * If the target behaviour here is anything other than "set | |
102 | * the PC register to the value passed in" then the target must | |
103 | * also implement the synchronize_from_tb hook. | |
5b50e790 AF |
104 | * @gdb_read_register: Callback for letting GDB read a register. |
105 | * @gdb_write_register: Callback for letting GDB write a register. | |
5bc31e94 RH |
106 | * @gdb_adjust_breakpoint: Callback for adjusting the address of a |
107 | * breakpoint. Used by AVR to handle a gdb mis-feature with | |
108 | * its Harvard architecture split code and data. | |
a0e372f0 | 109 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 110 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
111 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
112 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
113 | * @gdb_arch_name: Optional callback that returns the architecture name known |
114 | * to GDB. The caller must free the returned string with g_free. | |
200bf5b7 AB |
115 | * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the |
116 | * gdb stub. Returns a pointer to the XML contents for the specified XML file | |
117 | * or NULL if the CPU doesn't have a dynamically generated content for it. | |
37b9de46 | 118 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
119 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
120 | * address before attempting to match it against watchpoints. | |
61ad65d0 RH |
121 | * @deprecation_note: If this CPUClass is deprecated, this field provides |
122 | * related information. | |
dd83b06a AF |
123 | * |
124 | * Represents a CPU family or model. | |
125 | */ | |
db1015e9 | 126 | struct CPUClass { |
dd83b06a | 127 | /*< private >*/ |
961f8395 | 128 | DeviceClass parent_class; |
dd83b06a AF |
129 | /*< public >*/ |
130 | ||
2b8c2754 | 131 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 132 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 133 | |
8c2e1b00 | 134 | bool (*has_work)(CPUState *cpu); |
f3659eee AF |
135 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
136 | uint8_t *buf, int len, bool is_write); | |
90c84c56 | 137 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
997395d3 | 138 | int64_t (*get_arch_id)(CPUState *cpu); |
f45748f1 | 139 | void (*set_pc)(CPUState *cpu, vaddr value); |
a010bdbe | 140 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
5b50e790 | 141 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
5bc31e94 | 142 | vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); |
b170fce3 | 143 | |
5b24c641 | 144 | const char *gdb_core_xml_file; |
b3820e6c | 145 | gchar * (*gdb_arch_name)(CPUState *cpu); |
200bf5b7 | 146 | const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); |
37b9de46 PC |
147 | |
148 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
55c3ceef | 149 | |
61ad65d0 | 150 | const char *deprecation_note; |
fb6916dd | 151 | struct AccelCPUClass *accel_cpu; |
e9e51b71 | 152 | |
8b80bd28 PMD |
153 | /* when system emulation is not available, this pointer is NULL */ |
154 | const struct SysemuCPUOps *sysemu_ops; | |
155 | ||
78271684 | 156 | /* when TCG is not available, this pointer is NULL */ |
11906557 | 157 | const struct TCGCPUOps *tcg_ops; |
cc3f2be6 CF |
158 | |
159 | /* | |
160 | * if not NULL, this is called in order for the CPUClass to initialize | |
161 | * class data that depends on the accelerator, see accel/accel-common.c. | |
162 | */ | |
163 | void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc); | |
dc29f474 RH |
164 | |
165 | /* | |
166 | * Keep non-pointer data at the end to minimize holes. | |
167 | */ | |
168 | int reset_dump_flags; | |
169 | int gdb_num_core_regs; | |
170 | bool gdb_stop_before_watchpoint; | |
db1015e9 | 171 | }; |
dd83b06a | 172 | |
5e140196 RH |
173 | /* |
174 | * Low 16 bits: number of cycles left, used only in icount mode. | |
175 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs | |
176 | * for this CPU and return to its top level loop (even in non-icount mode). | |
177 | * This allows a single read-compare-cbranch-write sequence to test | |
178 | * for both decrementer underflow and exceptions. | |
179 | */ | |
180 | typedef union IcountDecr { | |
181 | uint32_t u32; | |
182 | struct { | |
28ecfd7a | 183 | #ifdef HOST_WORDS_BIGENDIAN |
5e140196 RH |
184 | uint16_t high; |
185 | uint16_t low; | |
28ecfd7a | 186 | #else |
5e140196 RH |
187 | uint16_t low; |
188 | uint16_t high; | |
28ecfd7a | 189 | #endif |
5e140196 RH |
190 | } u16; |
191 | } IcountDecr; | |
28ecfd7a | 192 | |
f0c3c505 AF |
193 | typedef struct CPUBreakpoint { |
194 | vaddr pc; | |
195 | int flags; /* BP_* */ | |
196 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
197 | } CPUBreakpoint; | |
198 | ||
568496c0 | 199 | struct CPUWatchpoint { |
ff4700b0 | 200 | vaddr vaddr; |
05068c0d | 201 | vaddr len; |
08225676 | 202 | vaddr hitaddr; |
66b9b43c | 203 | MemTxAttrs hitattrs; |
ff4700b0 AF |
204 | int flags; /* BP_* */ |
205 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 206 | }; |
ff4700b0 | 207 | |
2f3a57ee AB |
208 | #ifdef CONFIG_PLUGIN |
209 | /* | |
210 | * For plugins we sometime need to save the resolved iotlb data before | |
211 | * the memory regions get moved around by io_writex. | |
212 | */ | |
213 | typedef struct SavedIOTLB { | |
214 | hwaddr addr; | |
215 | MemoryRegionSection *section; | |
216 | hwaddr mr_offset; | |
217 | } SavedIOTLB; | |
218 | #endif | |
219 | ||
a60f24b5 | 220 | struct KVMState; |
f7575c96 | 221 | struct kvm_run; |
a60f24b5 | 222 | |
b0cb0a66 | 223 | struct hax_vcpu_state; |
b533450e | 224 | struct hvf_vcpu_state; |
b0cb0a66 | 225 | |
8cd70437 AF |
226 | #define TB_JMP_CACHE_BITS 12 |
227 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
228 | ||
4b4629d9 | 229 | /* work queue */ |
14e6fe12 PB |
230 | |
231 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
232 | * hosts in a single parameter | |
233 | */ | |
234 | typedef union { | |
235 | int host_int; | |
236 | unsigned long host_ulong; | |
237 | void *host_ptr; | |
238 | vaddr target_ptr; | |
239 | } run_on_cpu_data; | |
240 | ||
241 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
242 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
243 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
244 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
245 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
246 | ||
247 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
248 | ||
d148d90e | 249 | struct qemu_work_item; |
4b4629d9 | 250 | |
0b8497f0 | 251 | #define CPU_UNSET_NUMA_NODE_ID -1 |
d01c05c9 | 252 | #define CPU_TRACE_DSTATE_MAX_EVENTS 32 |
0b8497f0 | 253 | |
dd83b06a AF |
254 | /** |
255 | * CPUState: | |
55e5c285 | 256 | * @cpu_index: CPU index (informative). |
7ea7b9ad PM |
257 | * @cluster_index: Identifies which cluster this CPU is in. |
258 | * For boards which don't define clusters or for "loose" CPUs not assigned | |
259 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will | |
260 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER | |
261 | * QOM parent. | |
6cc9d67c | 262 | * @tcg_cflags: Pre-computed cflags for this cpu. |
ce3960eb AF |
263 | * @nr_cores: Number of cores within this CPU package. |
264 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
265 | * @running: #true if CPU is currently running (lockless). |
266 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 267 | * valid under cpu_list_lock. |
61a46217 | 268 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
269 | * @interrupt_request: Indicates a pending interrupt request. |
270 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 271 | * @stop: Indicates a pending stop request. |
f324e766 | 272 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 273 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 274 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 275 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 276 | * @icount_extra: Instructions until next timer event. |
414b15c9 PB |
277 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
278 | * requires that IO only be performed on the last instruction of a TB | |
279 | * so that interrupts take effect immediately. | |
32857f4d PM |
280 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
281 | * AddressSpaces this CPU has) | |
12ebc9a7 | 282 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
283 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
284 | * only have a single AddressSpace | |
c05efcb1 | 285 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
5e140196 | 286 | * @icount_decr_ptr: Pointer to IcountDecr field within subclass. |
eac8b355 | 287 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 288 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 289 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 290 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 291 | * @opaque: User data. |
93afeade | 292 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
8737c51c | 293 | * @kvm_fd: vCPU file descriptor for KVM. |
0c0fcc20 EC |
294 | * @work_mutex: Lock to prevent multiple access to @work_list. |
295 | * @work_list: List of pending asynchronous work. | |
d4381116 LV |
296 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
297 | * to @trace_dstate). | |
48151859 | 298 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
54cb65d8 | 299 | * @plugin_mask: Plugin event bitmap. Modified only via async work. |
ed860129 PM |
300 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
301 | * flag of the same name: allows the board to suppress calling of the | |
302 | * CPU do_transaction_failed hook function. | |
b4420f19 PX |
303 | * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty |
304 | * ring is enabled. | |
305 | * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU | |
306 | * dirty ring structure. | |
dd83b06a AF |
307 | * |
308 | * State of one CPU core or thread. | |
309 | */ | |
310 | struct CPUState { | |
311 | /*< private >*/ | |
961f8395 | 312 | DeviceState parent_obj; |
dd83b06a AF |
313 | /*< public >*/ |
314 | ||
ce3960eb AF |
315 | int nr_cores; |
316 | int nr_threads; | |
317 | ||
814e612e | 318 | struct QemuThread *thread; |
bcba2a72 AF |
319 | #ifdef _WIN32 |
320 | HANDLE hThread; | |
321 | #endif | |
9f09e18a | 322 | int thread_id; |
c265e976 | 323 | bool running, has_waiter; |
f5c121b8 | 324 | struct QemuCond *halt_cond; |
216fc9a4 | 325 | bool thread_kicked; |
61a46217 | 326 | bool created; |
4fdeee7c | 327 | bool stop; |
f324e766 | 328 | bool stopped; |
c1b70158 TJB |
329 | |
330 | /* Should CPU start in powered-off state? */ | |
331 | bool start_powered_off; | |
332 | ||
4c055ab5 | 333 | bool unplug; |
bac05aa9 | 334 | bool crash_occurred; |
e0c38211 | 335 | bool exit_request; |
cfbc3c60 | 336 | bool in_exclusive_context; |
9b990ee5 | 337 | uint32_t cflags_next_tb; |
8d04fb55 | 338 | /* updates protected by BQL */ |
259186a7 | 339 | uint32_t interrupt_request; |
ed2803da | 340 | int singlestep_enabled; |
e4cd9657 | 341 | int64_t icount_budget; |
efee7340 | 342 | int64_t icount_extra; |
9c09a251 | 343 | uint64_t random_seed; |
6f03bef0 | 344 | sigjmp_buf jmp_env; |
bcba2a72 | 345 | |
376692b9 | 346 | QemuMutex work_mutex; |
0c0fcc20 | 347 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
376692b9 | 348 | |
32857f4d | 349 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 350 | int num_ases; |
09daed84 | 351 | AddressSpace *as; |
6731d864 | 352 | MemoryRegion *memory; |
09daed84 | 353 | |
c05efcb1 | 354 | void *env_ptr; /* CPUArchState */ |
5e140196 | 355 | IcountDecr *icount_decr_ptr; |
7d7500d9 | 356 | |
f3ced3c5 | 357 | /* Accessed in parallel; all accesses must be atomic */ |
8349d2ae | 358 | TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
7d7500d9 | 359 | |
eac8b355 | 360 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 361 | int gdb_num_regs; |
35143f01 | 362 | int gdb_num_g_regs; |
bdc44640 | 363 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 364 | |
f0c3c505 | 365 | /* ice debug support */ |
b58deb34 | 366 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
f0c3c505 | 367 | |
b58deb34 | 368 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
ff4700b0 AF |
369 | CPUWatchpoint *watchpoint_hit; |
370 | ||
0429a971 AF |
371 | void *opaque; |
372 | ||
93afeade AF |
373 | /* In order to avoid passing too many arguments to the MMIO helpers, |
374 | * we store some rarely used information in the CPU context. | |
375 | */ | |
376 | uintptr_t mem_io_pc; | |
93afeade | 377 | |
b4420f19 | 378 | /* Only used in KVM */ |
8737c51c | 379 | int kvm_fd; |
a60f24b5 | 380 | struct KVMState *kvm_state; |
f7575c96 | 381 | struct kvm_run *kvm_run; |
b4420f19 PX |
382 | struct kvm_dirty_gfn *kvm_dirty_gfns; |
383 | uint32_t kvm_fetch_index; | |
7786ae40 | 384 | uint64_t dirty_pages; |
8737c51c | 385 | |
d01c05c9 | 386 | /* Used for events with 'vcpu' and *without* the 'disabled' properties */ |
d4381116 | 387 | DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); |
d01c05c9 | 388 | DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); |
48151859 | 389 | |
54cb65d8 EC |
390 | DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); |
391 | ||
2f3a57ee | 392 | #ifdef CONFIG_PLUGIN |
54cb65d8 | 393 | GArray *plugin_mem_cbs; |
2f3a57ee AB |
394 | /* saved iotlb data from io_writex */ |
395 | SavedIOTLB saved_iotlb; | |
396 | #endif | |
54cb65d8 | 397 | |
f5df5baf | 398 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e | 399 | int cpu_index; |
7ea7b9ad | 400 | int cluster_index; |
6cc9d67c | 401 | uint32_t tcg_cflags; |
6fda014e | 402 | uint32_t halted; |
99df7dce | 403 | uint32_t can_do_io; |
6fda014e | 404 | int32_t exception_index; |
7e4fb26d | 405 | |
99f31832 SAGDR |
406 | /* shared by kvm, hax and hvf */ |
407 | bool vcpu_dirty; | |
408 | ||
2adcc85d JH |
409 | /* Used to keep track of an outstanding cpu throttle thread for migration |
410 | * autoconverge | |
411 | */ | |
412 | bool throttle_thread_scheduled; | |
413 | ||
ed860129 PM |
414 | bool ignore_memory_transaction_failures; |
415 | ||
b0cb0a66 | 416 | struct hax_vcpu_state *hax_vcpu; |
e3b9ca81 | 417 | |
b533450e | 418 | struct hvf_vcpu_state *hvf; |
1f871c5e PM |
419 | |
420 | /* track IOMMUs whose translations we've cached in the TCG TLB */ | |
421 | GArray *iommu_notifiers; | |
dd83b06a AF |
422 | }; |
423 | ||
f481ee2d PB |
424 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
425 | extern CPUTailQ cpus; | |
426 | ||
068a5ea0 EC |
427 | #define first_cpu QTAILQ_FIRST_RCU(&cpus) |
428 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) | |
429 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) | |
bdc44640 | 430 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
068a5ea0 | 431 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) |
182735ef | 432 | |
f240eb6f | 433 | extern __thread CPUState *current_cpu; |
4917cf44 | 434 | |
f3ced3c5 EC |
435 | static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) |
436 | { | |
437 | unsigned int i; | |
438 | ||
439 | for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { | |
d73415a3 | 440 | qatomic_set(&cpu->tb_jmp_cache[i], NULL); |
f3ced3c5 EC |
441 | } |
442 | } | |
443 | ||
8d4e9146 FK |
444 | /** |
445 | * qemu_tcg_mttcg_enabled: | |
446 | * Check whether we are running MultiThread TCG or not. | |
447 | * | |
448 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
449 | */ | |
450 | extern bool mttcg_enabled; | |
451 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
452 | ||
444d5590 AF |
453 | /** |
454 | * cpu_paging_enabled: | |
455 | * @cpu: The CPU whose state is to be inspected. | |
456 | * | |
457 | * Returns: %true if paging is enabled, %false otherwise. | |
458 | */ | |
459 | bool cpu_paging_enabled(const CPUState *cpu); | |
460 | ||
a23bbfda AF |
461 | /** |
462 | * cpu_get_memory_mapping: | |
463 | * @cpu: The CPU whose memory mappings are to be obtained. | |
464 | * @list: Where to write the memory mappings to. | |
465 | * @errp: Pointer for reporting an #Error. | |
466 | */ | |
467 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
468 | Error **errp); | |
469 | ||
cfe35d48 PMD |
470 | #if !defined(CONFIG_USER_ONLY) |
471 | ||
c72bf468 JF |
472 | /** |
473 | * cpu_write_elf64_note: | |
474 | * @f: pointer to a function that writes memory to a file | |
475 | * @cpu: The CPU whose memory is to be dumped | |
476 | * @cpuid: ID number of the CPU | |
477 | * @opaque: pointer to the CPUState struct | |
478 | */ | |
479 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
480 | int cpuid, void *opaque); | |
481 | ||
482 | /** | |
483 | * cpu_write_elf64_qemunote: | |
484 | * @f: pointer to a function that writes memory to a file | |
485 | * @cpu: The CPU whose memory is to be dumped | |
486 | * @cpuid: ID number of the CPU | |
487 | * @opaque: pointer to the CPUState struct | |
488 | */ | |
489 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
490 | void *opaque); | |
491 | ||
492 | /** | |
493 | * cpu_write_elf32_note: | |
494 | * @f: pointer to a function that writes memory to a file | |
495 | * @cpu: The CPU whose memory is to be dumped | |
496 | * @cpuid: ID number of the CPU | |
497 | * @opaque: pointer to the CPUState struct | |
498 | */ | |
499 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
500 | int cpuid, void *opaque); | |
501 | ||
502 | /** | |
503 | * cpu_write_elf32_qemunote: | |
504 | * @f: pointer to a function that writes memory to a file | |
505 | * @cpu: The CPU whose memory is to be dumped | |
506 | * @cpuid: ID number of the CPU | |
507 | * @opaque: pointer to the CPUState struct | |
508 | */ | |
509 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
510 | void *opaque); | |
dd83b06a | 511 | |
c86f106b AN |
512 | /** |
513 | * cpu_get_crash_info: | |
514 | * @cpu: The CPU to get crash information for | |
515 | * | |
516 | * Gets the previously saved crash information. | |
517 | * Caller is responsible for freeing the data. | |
518 | */ | |
519 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
520 | ||
cfe35d48 PMD |
521 | #endif /* !CONFIG_USER_ONLY */ |
522 | ||
878096ee AF |
523 | /** |
524 | * CPUDumpFlags: | |
525 | * @CPU_DUMP_CODE: | |
526 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
527 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
528 | */ | |
529 | enum CPUDumpFlags { | |
530 | CPU_DUMP_CODE = 0x00010000, | |
531 | CPU_DUMP_FPU = 0x00020000, | |
532 | CPU_DUMP_CCOP = 0x00040000, | |
533 | }; | |
534 | ||
535 | /** | |
536 | * cpu_dump_state: | |
537 | * @cpu: The CPU whose state is to be dumped. | |
90c84c56 | 538 | * @f: If non-null, dump to this stream, else to current print sink. |
878096ee AF |
539 | * |
540 | * Dumps CPU state. | |
541 | */ | |
90c84c56 | 542 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
878096ee | 543 | |
00b941e5 | 544 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
545 | /** |
546 | * cpu_get_phys_page_attrs_debug: | |
547 | * @cpu: The CPU to obtain the physical page address for. | |
548 | * @addr: The virtual address. | |
549 | * @attrs: Updated on return with the memory transaction attributes to use | |
550 | * for this access. | |
551 | * | |
552 | * Obtains the physical page corresponding to a virtual one, together | |
553 | * with the corresponding memory transaction attributes to use for the access. | |
554 | * Use it only for debugging because no protection checks are done. | |
555 | * | |
556 | * Returns: Corresponding physical page address or -1 if no page found. | |
557 | */ | |
a41d3aae PMD |
558 | hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
559 | MemTxAttrs *attrs); | |
1dc6fb1f | 560 | |
00b941e5 AF |
561 | /** |
562 | * cpu_get_phys_page_debug: | |
563 | * @cpu: The CPU to obtain the physical page address for. | |
564 | * @addr: The virtual address. | |
565 | * | |
566 | * Obtains the physical page corresponding to a virtual one. | |
567 | * Use it only for debugging because no protection checks are done. | |
568 | * | |
569 | * Returns: Corresponding physical page address or -1 if no page found. | |
570 | */ | |
a41d3aae | 571 | hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
d7f25a9e PM |
572 | |
573 | /** cpu_asidx_from_attrs: | |
574 | * @cpu: CPU | |
575 | * @attrs: memory transaction attributes | |
576 | * | |
577 | * Returns the address space index specifying the CPU AddressSpace | |
578 | * to use for a memory access with the given transaction attributes. | |
579 | */ | |
a41d3aae | 580 | int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); |
d7f25a9e | 581 | |
cdba7e2f PMD |
582 | /** |
583 | * cpu_virtio_is_big_endian: | |
584 | * @cpu: CPU | |
585 | ||
586 | * Returns %true if a CPU which supports runtime configurable endianness | |
587 | * is currently big-endian. | |
588 | */ | |
589 | bool cpu_virtio_is_big_endian(CPUState *cpu); | |
cfe35d48 PMD |
590 | |
591 | #endif /* CONFIG_USER_ONLY */ | |
00b941e5 | 592 | |
267f685b PB |
593 | /** |
594 | * cpu_list_add: | |
595 | * @cpu: The CPU to be added to the list of CPUs. | |
596 | */ | |
597 | void cpu_list_add(CPUState *cpu); | |
598 | ||
599 | /** | |
600 | * cpu_list_remove: | |
601 | * @cpu: The CPU to be removed from the list of CPUs. | |
602 | */ | |
603 | void cpu_list_remove(CPUState *cpu); | |
604 | ||
dd83b06a AF |
605 | /** |
606 | * cpu_reset: | |
607 | * @cpu: The CPU whose state is to be reset. | |
608 | */ | |
609 | void cpu_reset(CPUState *cpu); | |
610 | ||
2b8c2754 AF |
611 | /** |
612 | * cpu_class_by_name: | |
613 | * @typename: The CPU base type. | |
614 | * @cpu_model: The model string without any parameters. | |
615 | * | |
616 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
617 | * | |
618 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
619 | */ | |
620 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
621 | ||
3c72234c IM |
622 | /** |
623 | * cpu_create: | |
624 | * @typename: The CPU type. | |
625 | * | |
626 | * Instantiates a CPU and realizes the CPU. | |
627 | * | |
628 | * Returns: A #CPUState or %NULL if an error occurred. | |
629 | */ | |
630 | CPUState *cpu_create(const char *typename); | |
631 | ||
632 | /** | |
c1c8cfe5 EH |
633 | * parse_cpu_option: |
634 | * @cpu_option: The -cpu option including optional parameters. | |
3c72234c IM |
635 | * |
636 | * processes optional parameters and registers them as global properties | |
637 | * | |
4482e05c IM |
638 | * Returns: type of CPU to create or prints error and terminates process |
639 | * if an error occurred. | |
3c72234c | 640 | */ |
c1c8cfe5 | 641 | const char *parse_cpu_option(const char *cpu_option); |
9262685b | 642 | |
3993c6bd | 643 | /** |
8c2e1b00 | 644 | * cpu_has_work: |
3993c6bd AF |
645 | * @cpu: The vCPU to check. |
646 | * | |
647 | * Checks whether the CPU has work to do. | |
648 | * | |
649 | * Returns: %true if the CPU has work, %false otherwise. | |
650 | */ | |
8c2e1b00 AF |
651 | static inline bool cpu_has_work(CPUState *cpu) |
652 | { | |
653 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
654 | ||
655 | g_assert(cc->has_work); | |
656 | return cc->has_work(cpu); | |
657 | } | |
3993c6bd | 658 | |
60e82579 AF |
659 | /** |
660 | * qemu_cpu_is_self: | |
661 | * @cpu: The vCPU to check against. | |
662 | * | |
663 | * Checks whether the caller is executing on the vCPU thread. | |
664 | * | |
665 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
666 | */ | |
667 | bool qemu_cpu_is_self(CPUState *cpu); | |
668 | ||
c08d7424 AF |
669 | /** |
670 | * qemu_cpu_kick: | |
671 | * @cpu: The vCPU to kick. | |
672 | * | |
673 | * Kicks @cpu's thread. | |
674 | */ | |
675 | void qemu_cpu_kick(CPUState *cpu); | |
676 | ||
2fa45344 AF |
677 | /** |
678 | * cpu_is_stopped: | |
679 | * @cpu: The CPU to check. | |
680 | * | |
681 | * Checks whether the CPU is stopped. | |
682 | * | |
683 | * Returns: %true if run state is not running or if artificially stopped; | |
684 | * %false otherwise. | |
685 | */ | |
686 | bool cpu_is_stopped(CPUState *cpu); | |
687 | ||
d148d90e SF |
688 | /** |
689 | * do_run_on_cpu: | |
690 | * @cpu: The vCPU to run on. | |
691 | * @func: The function to be executed. | |
692 | * @data: Data to pass to the function. | |
693 | * @mutex: Mutex to release while waiting for @func to run. | |
694 | * | |
695 | * Used internally in the implementation of run_on_cpu. | |
696 | */ | |
14e6fe12 | 697 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
698 | QemuMutex *mutex); |
699 | ||
f100f0b3 AF |
700 | /** |
701 | * run_on_cpu: | |
702 | * @cpu: The vCPU to run on. | |
703 | * @func: The function to be executed. | |
704 | * @data: Data to pass to the function. | |
705 | * | |
706 | * Schedules the function @func for execution on the vCPU @cpu. | |
707 | */ | |
14e6fe12 | 708 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 709 | |
3c02270d CV |
710 | /** |
711 | * async_run_on_cpu: | |
712 | * @cpu: The vCPU to run on. | |
713 | * @func: The function to be executed. | |
714 | * @data: Data to pass to the function. | |
715 | * | |
716 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
717 | */ | |
14e6fe12 | 718 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 719 | |
53f5ed95 PB |
720 | /** |
721 | * async_safe_run_on_cpu: | |
722 | * @cpu: The vCPU to run on. | |
723 | * @func: The function to be executed. | |
724 | * @data: Data to pass to the function. | |
725 | * | |
726 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
727 | * while all other vCPUs are sleeping. | |
728 | * | |
729 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
730 | * BQL. | |
731 | */ | |
14e6fe12 | 732 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 733 | |
cfbc3c60 EC |
734 | /** |
735 | * cpu_in_exclusive_context() | |
736 | * @cpu: The vCPU to check | |
737 | * | |
738 | * Returns true if @cpu is an exclusive context, for example running | |
739 | * something which has previously been queued via async_safe_run_on_cpu(). | |
740 | */ | |
741 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) | |
742 | { | |
743 | return cpu->in_exclusive_context; | |
744 | } | |
745 | ||
38d8f5c8 AF |
746 | /** |
747 | * qemu_get_cpu: | |
748 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
749 | * | |
750 | * Gets a CPU matching @index. | |
751 | * | |
752 | * Returns: The CPU or %NULL if there is no matching CPU. | |
753 | */ | |
754 | CPUState *qemu_get_cpu(int index); | |
755 | ||
69e5ff06 IM |
756 | /** |
757 | * cpu_exists: | |
758 | * @id: Guest-exposed CPU ID to lookup. | |
759 | * | |
760 | * Search for CPU with specified ID. | |
761 | * | |
762 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
763 | */ | |
764 | bool cpu_exists(int64_t id); | |
765 | ||
5ce46cb3 EH |
766 | /** |
767 | * cpu_by_arch_id: | |
768 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
769 | * | |
770 | * Get a CPU with matching @id. | |
771 | * | |
772 | * Returns: The CPU or %NULL if there is no matching CPU. | |
773 | */ | |
774 | CPUState *cpu_by_arch_id(int64_t id); | |
775 | ||
c3affe56 AF |
776 | /** |
777 | * cpu_interrupt: | |
778 | * @cpu: The CPU to set an interrupt on. | |
7e63bc38 | 779 | * @mask: The interrupts to set. |
c3affe56 AF |
780 | * |
781 | * Invokes the interrupt handler. | |
782 | */ | |
c3affe56 AF |
783 | |
784 | void cpu_interrupt(CPUState *cpu, int mask); | |
785 | ||
2991b890 PC |
786 | /** |
787 | * cpu_set_pc: | |
788 | * @cpu: The CPU to set the program counter for. | |
789 | * @addr: Program counter value. | |
790 | * | |
791 | * Sets the program counter for a CPU. | |
792 | */ | |
793 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
794 | { | |
795 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
796 | ||
797 | cc->set_pc(cpu, addr); | |
798 | } | |
799 | ||
d8ed887b AF |
800 | /** |
801 | * cpu_reset_interrupt: | |
802 | * @cpu: The CPU to clear the interrupt on. | |
803 | * @mask: The interrupt mask to clear. | |
804 | * | |
805 | * Resets interrupts on the vCPU @cpu. | |
806 | */ | |
807 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
808 | ||
60a3e17a AF |
809 | /** |
810 | * cpu_exit: | |
811 | * @cpu: The CPU to exit. | |
812 | * | |
813 | * Requests the CPU @cpu to exit execution. | |
814 | */ | |
815 | void cpu_exit(CPUState *cpu); | |
816 | ||
2993683b IM |
817 | /** |
818 | * cpu_resume: | |
819 | * @cpu: The CPU to resume. | |
820 | * | |
821 | * Resumes CPU, i.e. puts CPU into runnable state. | |
822 | */ | |
823 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 824 | |
4c055ab5 | 825 | /** |
2c579042 BR |
826 | * cpu_remove_sync: |
827 | * @cpu: The CPU to remove. | |
828 | * | |
829 | * Requests the CPU to be removed and waits till it is removed. | |
830 | */ | |
831 | void cpu_remove_sync(CPUState *cpu); | |
832 | ||
d148d90e SF |
833 | /** |
834 | * process_queued_cpu_work() - process all items on CPU work queue | |
835 | * @cpu: The CPU which work queue to process. | |
836 | */ | |
837 | void process_queued_cpu_work(CPUState *cpu); | |
838 | ||
ab129972 PB |
839 | /** |
840 | * cpu_exec_start: | |
841 | * @cpu: The CPU for the current thread. | |
842 | * | |
843 | * Record that a CPU has started execution and can be interrupted with | |
844 | * cpu_exit. | |
845 | */ | |
846 | void cpu_exec_start(CPUState *cpu); | |
847 | ||
848 | /** | |
849 | * cpu_exec_end: | |
850 | * @cpu: The CPU for the current thread. | |
851 | * | |
852 | * Record that a CPU has stopped execution and exclusive sections | |
853 | * can be executed without interrupting it. | |
854 | */ | |
855 | void cpu_exec_end(CPUState *cpu); | |
856 | ||
857 | /** | |
858 | * start_exclusive: | |
859 | * | |
860 | * Wait for a concurrent exclusive section to end, and then start | |
861 | * a section of work that is run while other CPUs are not running | |
862 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
863 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
864 | * during the exclusive section go to sleep until this CPU calls | |
865 | * end_exclusive. | |
ab129972 PB |
866 | */ |
867 | void start_exclusive(void); | |
868 | ||
869 | /** | |
870 | * end_exclusive: | |
871 | * | |
872 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
873 | */ |
874 | void end_exclusive(void); | |
875 | ||
c643bed9 AF |
876 | /** |
877 | * qemu_init_vcpu: | |
878 | * @cpu: The vCPU to initialize. | |
879 | * | |
880 | * Initializes a vCPU. | |
881 | */ | |
882 | void qemu_init_vcpu(CPUState *cpu); | |
883 | ||
3825b28f AF |
884 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
885 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
886 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
887 | ||
888 | /** | |
889 | * cpu_single_step: | |
890 | * @cpu: CPU to the flags for. | |
891 | * @enabled: Flags to enable. | |
892 | * | |
893 | * Enables or disables single-stepping for @cpu. | |
894 | */ | |
895 | void cpu_single_step(CPUState *cpu, int enabled); | |
896 | ||
b3310ab3 AF |
897 | /* Breakpoint/watchpoint flags */ |
898 | #define BP_MEM_READ 0x01 | |
899 | #define BP_MEM_WRITE 0x02 | |
900 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
901 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 902 | /* 0x08 currently unused */ |
b3310ab3 AF |
903 | #define BP_GDB 0x10 |
904 | #define BP_CPU 0x20 | |
b933066a | 905 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
906 | #define BP_WATCHPOINT_HIT_READ 0x40 |
907 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
908 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
909 | |
910 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
911 | CPUBreakpoint **breakpoint); | |
912 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
913 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
914 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
915 | ||
b933066a RH |
916 | /* Return true if PC matches an installed breakpoint. */ |
917 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
918 | { | |
919 | CPUBreakpoint *bp; | |
920 | ||
921 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
922 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
923 | if (bp->pc == pc && (bp->flags & mask)) { | |
924 | return true; | |
925 | } | |
926 | } | |
927 | } | |
928 | return false; | |
929 | } | |
930 | ||
74841f04 RH |
931 | #ifdef CONFIG_USER_ONLY |
932 | static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
933 | int flags, CPUWatchpoint **watchpoint) | |
934 | { | |
935 | return -ENOSYS; | |
936 | } | |
937 | ||
938 | static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
939 | vaddr len, int flags) | |
940 | { | |
941 | return -ENOSYS; | |
942 | } | |
943 | ||
944 | static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, | |
945 | CPUWatchpoint *wp) | |
946 | { | |
947 | } | |
948 | ||
949 | static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
950 | { | |
951 | } | |
0026348b DH |
952 | |
953 | static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, | |
954 | MemTxAttrs atr, int fl, uintptr_t ra) | |
955 | { | |
956 | } | |
56ad8b00 RH |
957 | |
958 | static inline int cpu_watchpoint_address_matches(CPUState *cpu, | |
959 | vaddr addr, vaddr len) | |
960 | { | |
961 | return 0; | |
962 | } | |
74841f04 | 963 | #else |
75a34036 AF |
964 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
965 | int flags, CPUWatchpoint **watchpoint); | |
966 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
967 | vaddr len, int flags); | |
968 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
969 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
390734a4 RH |
970 | |
971 | /** | |
972 | * cpu_check_watchpoint: | |
973 | * @cpu: cpu context | |
974 | * @addr: guest virtual address | |
975 | * @len: access length | |
976 | * @attrs: memory access attributes | |
977 | * @flags: watchpoint access type | |
978 | * @ra: unwind return address | |
979 | * | |
980 | * Check for a watchpoint hit in [addr, addr+len) of the type | |
981 | * specified by @flags. Exit via exception with a hit. | |
982 | */ | |
0026348b DH |
983 | void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, |
984 | MemTxAttrs attrs, int flags, uintptr_t ra); | |
390734a4 RH |
985 | |
986 | /** | |
987 | * cpu_watchpoint_address_matches: | |
988 | * @cpu: cpu context | |
989 | * @addr: guest virtual address | |
990 | * @len: access length | |
991 | * | |
992 | * Return the watchpoint flags that apply to [addr, addr+len). | |
993 | * If no watchpoint is registered for the range, the result is 0. | |
994 | */ | |
56ad8b00 | 995 | int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); |
74841f04 | 996 | #endif |
75a34036 | 997 | |
63c91552 PB |
998 | /** |
999 | * cpu_get_address_space: | |
1000 | * @cpu: CPU to get address space from | |
1001 | * @asidx: index identifying which address space to get | |
1002 | * | |
1003 | * Return the requested address space of this CPU. @asidx | |
1004 | * specifies which address space to read. | |
1005 | */ | |
1006 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
1007 | ||
a47dddd7 AF |
1008 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
1009 | GCC_FMT_ATTR(2, 3); | |
7df5e3d6 CF |
1010 | |
1011 | /* $(top_srcdir)/cpu.c */ | |
995b87de | 1012 | void cpu_class_init_props(DeviceClass *dc); |
39e329e3 | 1013 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 1014 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 1015 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1016 | |
c95ac103 TH |
1017 | /** |
1018 | * target_words_bigendian: | |
1019 | * Returns true if the (default) endianness of the target is big endian, | |
1020 | * false otherwise. Note that in target-specific code, you can use | |
1021 | * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common | |
1022 | * code should normally never need to know about the endianness of the | |
1023 | * target, so please do *not* use this function unless you know very well | |
1024 | * what you are doing! | |
1025 | */ | |
1026 | bool target_words_bigendian(void); | |
1027 | ||
47507383 TH |
1028 | #ifdef NEED_CPU_H |
1029 | ||
1a1562f5 | 1030 | #ifdef CONFIG_SOFTMMU |
feece4d0 | 1031 | |
8a9358cc | 1032 | extern const VMStateDescription vmstate_cpu_common; |
1a1562f5 AF |
1033 | |
1034 | #define VMSTATE_CPU() { \ | |
1035 | .name = "parent_obj", \ | |
1036 | .size = sizeof(CPUState), \ | |
1037 | .vmsd = &vmstate_cpu_common, \ | |
1038 | .flags = VMS_STRUCT, \ | |
1039 | .offset = 0, \ | |
1040 | } | |
feece4d0 | 1041 | #endif /* CONFIG_SOFTMMU */ |
1a1562f5 | 1042 | |
47507383 TH |
1043 | #endif /* NEED_CPU_H */ |
1044 | ||
a07f953e | 1045 | #define UNASSIGNED_CPU_INDEX -1 |
7ea7b9ad | 1046 | #define UNASSIGNED_CLUSTER_INDEX -1 |
a07f953e | 1047 | |
dd83b06a | 1048 | #endif |