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dd83b06a
AF
1/*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20#ifndef QEMU_CPU_H
21#define QEMU_CPU_H
22
961f8395 23#include "hw/qdev-core.h"
3979fca4 24#include "disas/dis-asm.h"
c658b94f 25#include "exec/hwaddr.h"
66b9b43c 26#include "exec/memattrs.h"
9af23989 27#include "qapi/qapi-types-run-state.h"
48151859 28#include "qemu/bitmap.h"
068a5ea0 29#include "qemu/rcu_queue.h"
bdc44640 30#include "qemu/queue.h"
1de7afc9 31#include "qemu/thread.h"
54cb65d8 32#include "qemu/plugin.h"
db1015e9 33#include "qom/object.h"
dd83b06a 34
b5ba1cc6
QN
35typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
36 void *opaque);
c72bf468 37
577f42c0
AF
38/**
39 * vaddr:
40 * Type wide enough to contain any #target_ulong virtual address.
41 */
42typedef uint64_t vaddr;
43#define VADDR_PRId PRId64
44#define VADDR_PRIu PRIu64
45#define VADDR_PRIo PRIo64
46#define VADDR_PRIx PRIx64
47#define VADDR_PRIX PRIX64
48#define VADDR_MAX UINT64_MAX
49
dd83b06a
AF
50/**
51 * SECTION:cpu
52 * @section_id: QEMU-cpu
53 * @title: CPU Class
54 * @short_description: Base class for all CPUs
55 */
56
57#define TYPE_CPU "cpu"
58
0d6d1ab4
AF
59/* Since this macro is used a lot in hot code paths and in conjunction with
60 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
61 * an unchecked cast.
62 */
63#define CPU(obj) ((CPUState *)(obj))
64
db1015e9 65typedef struct CPUClass CPUClass;
8110fa1d
EH
66DECLARE_CLASS_CHECKERS(CPUClass, CPU,
67 TYPE_CPU)
dd83b06a 68
b35399bb
SS
69typedef enum MMUAccessType {
70 MMU_DATA_LOAD = 0,
71 MMU_DATA_STORE = 1,
72 MMU_INST_FETCH = 2
73} MMUAccessType;
74
568496c0 75typedef struct CPUWatchpoint CPUWatchpoint;
dd83b06a 76
bdf7ae5b
AF
77struct TranslationBlock;
78
dd83b06a
AF
79/**
80 * CPUClass:
2b8c2754
AF
81 * @class_by_name: Callback to map -cpu command line model name to an
82 * instantiatable CPU type.
94a444b2 83 * @parse_features: Callback to parse command line arguments.
91b1df8c 84 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
8c2e1b00 85 * @has_work: Callback for checking if there is work to do.
97a8ea5a 86 * @do_interrupt: Callback for interrupt handling.
93e22326 87 * @do_unaligned_access: Callback for unaligned access handling, if
52bf9771 88 * the target defines #TARGET_ALIGNED_ONLY.
0dff0939
PM
89 * @do_transaction_failed: Callback for handling failed memory transactions
90 * (ie bus faults or external aborts; not MMU faults)
c08295d4
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91 * @virtio_is_big_endian: Callback to return %true if a CPU which supports
92 * runtime configurable endianness is currently big-endian. Non-configurable
93 * CPUs can use the default implementation of this method. This method should
94 * not be used by any callers other than the pre-1.0 virtio devices.
f3659eee 95 * @memory_rw_debug: Callback for GDB memory access.
878096ee
AF
96 * @dump_state: Callback for dumping state.
97 * @dump_statistics: Callback for dumping statistics.
997395d3 98 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
444d5590 99 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
a23bbfda 100 * @get_memory_mapping: Callback for obtaining the memory mappings.
42f6ed91
JS
101 * @set_pc: Callback for setting the Program Counter register. This
102 * should have the semantics used by the target architecture when
103 * setting the PC from a source such as an ELF file entry point;
104 * for example on Arm it will also set the Thumb mode bit based
105 * on the least significant bit of the new PC value.
106 * If the target behaviour here is anything other than "set
107 * the PC register to the value passed in" then the target must
108 * also implement the synchronize_from_tb hook.
bdf7ae5b 109 * @synchronize_from_tb: Callback for synchronizing state from a TCG
42f6ed91
JS
110 * #TranslationBlock. This is called when we abandon execution
111 * of a TB before starting it, and must set all parts of the CPU
112 * state which the previous TB in the chain may not have updated.
113 * This always includes at least the program counter; some targets
114 * will need to do more. If this hook is not implemented then the
115 * default is to call @set_pc(tb->pc).
da6bbf85
RH
116 * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
117 * address fault. For system mode, if the access is valid, call
118 * tlb_set_page and return true; if the access is invalid, and
119 * probe is true, return false; otherwise raise an exception and
120 * do not return. For user-only mode, always raise an exception
121 * and do not return.
00b941e5 122 * @get_phys_page_debug: Callback for obtaining a physical address.
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123 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
124 * associated memory transaction attributes to use for the access.
125 * CPUs which use memory transaction attributes should implement this
126 * instead of get_phys_page_debug.
d7f25a9e
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127 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
128 * a memory access with the specified memory transaction attributes.
5b50e790
AF
129 * @gdb_read_register: Callback for letting GDB read a register.
130 * @gdb_write_register: Callback for letting GDB write a register.
568496c0
SF
131 * @debug_check_watchpoint: Callback: return true if the architectural
132 * watchpoint whose address has matched should really fire.
86025ee4 133 * @debug_excp_handler: Callback for handling debug exceptions.
c08295d4
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134 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
135 * 64-bit VM coredump.
136 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
137 * note to a 32-bit VM coredump.
138 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
139 * 32-bit VM coredump.
140 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
141 * note to a 32-bit VM coredump.
b170fce3 142 * @vmsd: State description for migration.
a0e372f0 143 * @gdb_num_core_regs: Number of core registers accessible to GDB.
5b24c641 144 * @gdb_core_xml_file: File name for core registers GDB XML description.
2472b6c0
PM
145 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
146 * before the insn which triggers a watchpoint rather than after it.
b3820e6c
DH
147 * @gdb_arch_name: Optional callback that returns the architecture name known
148 * to GDB. The caller must free the returned string with g_free.
200bf5b7
AB
149 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
150 * gdb stub. Returns a pointer to the XML contents for the specified XML file
151 * or NULL if the CPU doesn't have a dynamically generated content for it.
cffe7b32
RH
152 * @cpu_exec_enter: Callback for cpu_exec preparation.
153 * @cpu_exec_exit: Callback for cpu_exec cleanup.
9585db68 154 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
37b9de46 155 * @disas_set_info: Setup architecture specific components of disassembly info
40612000
JB
156 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
157 * address before attempting to match it against watchpoints.
61ad65d0
RH
158 * @deprecation_note: If this CPUClass is deprecated, this field provides
159 * related information.
dd83b06a
AF
160 *
161 * Represents a CPU family or model.
162 */
db1015e9 163struct CPUClass {
dd83b06a 164 /*< private >*/
961f8395 165 DeviceClass parent_class;
dd83b06a
AF
166 /*< public >*/
167
2b8c2754 168 ObjectClass *(*class_by_name)(const char *cpu_model);
62a48a2a 169 void (*parse_features)(const char *typename, char *str, Error **errp);
2b8c2754 170
91b1df8c 171 int reset_dump_flags;
8c2e1b00 172 bool (*has_work)(CPUState *cpu);
97a8ea5a 173 void (*do_interrupt)(CPUState *cpu);
93e22326 174 void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
b35399bb
SS
175 MMUAccessType access_type,
176 int mmu_idx, uintptr_t retaddr);
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177 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
178 unsigned size, MMUAccessType access_type,
179 int mmu_idx, MemTxAttrs attrs,
180 MemTxResult response, uintptr_t retaddr);
bf7663c4 181 bool (*virtio_is_big_endian)(CPUState *cpu);
f3659eee
AF
182 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
183 uint8_t *buf, int len, bool is_write);
90c84c56 184 void (*dump_state)(CPUState *cpu, FILE *, int flags);
c86f106b 185 GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
11cb6c15 186 void (*dump_statistics)(CPUState *cpu, int flags);
997395d3 187 int64_t (*get_arch_id)(CPUState *cpu);
444d5590 188 bool (*get_paging_enabled)(const CPUState *cpu);
a23bbfda
AF
189 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
190 Error **errp);
f45748f1 191 void (*set_pc)(CPUState *cpu, vaddr value);
04a37d4c
RH
192 void (*synchronize_from_tb)(CPUState *cpu,
193 const struct TranslationBlock *tb);
da6bbf85
RH
194 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
195 MMUAccessType access_type, int mmu_idx,
196 bool probe, uintptr_t retaddr);
00b941e5 197 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
1dc6fb1f
PM
198 hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
199 MemTxAttrs *attrs);
d7f25a9e 200 int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
a010bdbe 201 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
5b50e790 202 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
568496c0 203 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
86025ee4 204 void (*debug_excp_handler)(CPUState *cpu);
b170fce3 205
c72bf468
JF
206 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
207 int cpuid, void *opaque);
208 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
209 void *opaque);
210 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
211 int cpuid, void *opaque);
212 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
213 void *opaque);
a0e372f0 214
8a9358cc 215 const VMStateDescription *vmsd;
5b24c641 216 const char *gdb_core_xml_file;
b3820e6c 217 gchar * (*gdb_arch_name)(CPUState *cpu);
200bf5b7 218 const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
cffe7b32
RH
219 void (*cpu_exec_enter)(CPUState *cpu);
220 void (*cpu_exec_exit)(CPUState *cpu);
9585db68 221 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
37b9de46
PC
222
223 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
40612000 224 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
55c3ceef
RH
225 void (*tcg_initialize)(void);
226
61ad65d0 227 const char *deprecation_note;
55c3ceef
RH
228 /* Keep non-pointer data at the end to minimize holes. */
229 int gdb_num_core_regs;
230 bool gdb_stop_before_watchpoint;
db1015e9 231};
dd83b06a 232
5e140196
RH
233/*
234 * Low 16 bits: number of cycles left, used only in icount mode.
235 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
236 * for this CPU and return to its top level loop (even in non-icount mode).
237 * This allows a single read-compare-cbranch-write sequence to test
238 * for both decrementer underflow and exceptions.
239 */
240typedef union IcountDecr {
241 uint32_t u32;
242 struct {
28ecfd7a 243#ifdef HOST_WORDS_BIGENDIAN
5e140196
RH
244 uint16_t high;
245 uint16_t low;
28ecfd7a 246#else
5e140196
RH
247 uint16_t low;
248 uint16_t high;
28ecfd7a 249#endif
5e140196
RH
250 } u16;
251} IcountDecr;
28ecfd7a 252
f0c3c505
AF
253typedef struct CPUBreakpoint {
254 vaddr pc;
255 int flags; /* BP_* */
256 QTAILQ_ENTRY(CPUBreakpoint) entry;
257} CPUBreakpoint;
258
568496c0 259struct CPUWatchpoint {
ff4700b0 260 vaddr vaddr;
05068c0d 261 vaddr len;
08225676 262 vaddr hitaddr;
66b9b43c 263 MemTxAttrs hitattrs;
ff4700b0
AF
264 int flags; /* BP_* */
265 QTAILQ_ENTRY(CPUWatchpoint) entry;
568496c0 266};
ff4700b0 267
2f3a57ee
AB
268#ifdef CONFIG_PLUGIN
269/*
270 * For plugins we sometime need to save the resolved iotlb data before
271 * the memory regions get moved around by io_writex.
272 */
273typedef struct SavedIOTLB {
274 hwaddr addr;
275 MemoryRegionSection *section;
276 hwaddr mr_offset;
277} SavedIOTLB;
278#endif
279
a60f24b5 280struct KVMState;
f7575c96 281struct kvm_run;
a60f24b5 282
b0cb0a66
VP
283struct hax_vcpu_state;
284
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AF
285#define TB_JMP_CACHE_BITS 12
286#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
287
4b4629d9 288/* work queue */
14e6fe12
PB
289
290/* The union type allows passing of 64 bit target pointers on 32 bit
291 * hosts in a single parameter
292 */
293typedef union {
294 int host_int;
295 unsigned long host_ulong;
296 void *host_ptr;
297 vaddr target_ptr;
298} run_on_cpu_data;
299
300#define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
301#define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
302#define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
303#define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
304#define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
305
306typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
307
d148d90e 308struct qemu_work_item;
4b4629d9 309
0b8497f0 310#define CPU_UNSET_NUMA_NODE_ID -1
d01c05c9 311#define CPU_TRACE_DSTATE_MAX_EVENTS 32
0b8497f0 312
dd83b06a
AF
313/**
314 * CPUState:
55e5c285 315 * @cpu_index: CPU index (informative).
7ea7b9ad
PM
316 * @cluster_index: Identifies which cluster this CPU is in.
317 * For boards which don't define clusters or for "loose" CPUs not assigned
318 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
319 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
320 * QOM parent.
ce3960eb
AF
321 * @nr_cores: Number of cores within this CPU package.
322 * @nr_threads: Number of threads within this CPU.
c265e976
PB
323 * @running: #true if CPU is currently running (lockless).
324 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
ab129972 325 * valid under cpu_list_lock.
61a46217 326 * @created: Indicates whether the CPU thread has been successfully created.
259186a7
AF
327 * @interrupt_request: Indicates a pending interrupt request.
328 * @halted: Nonzero if the CPU is in suspended state.
4fdeee7c 329 * @stop: Indicates a pending stop request.
f324e766 330 * @stopped: Indicates the CPU has been artificially stopped.
4c055ab5 331 * @unplug: Indicates a pending CPU unplug request.
bac05aa9 332 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
ed2803da 333 * @singlestep_enabled: Flags for single-stepping.
efee7340 334 * @icount_extra: Instructions until next timer event.
414b15c9
PB
335 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
336 * requires that IO only be performed on the last instruction of a TB
337 * so that interrupts take effect immediately.
32857f4d
PM
338 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
339 * AddressSpaces this CPU has)
12ebc9a7 340 * @num_ases: number of CPUAddressSpaces in @cpu_ases
32857f4d
PM
341 * @as: Pointer to the first AddressSpace, for the convenience of targets which
342 * only have a single AddressSpace
c05efcb1 343 * @env_ptr: Pointer to subclass-specific CPUArchState field.
5e140196 344 * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
eac8b355 345 * @gdb_regs: Additional GDB registers.
a0e372f0 346 * @gdb_num_regs: Number of total registers accessible to GDB.
35143f01 347 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
182735ef 348 * @next_cpu: Next CPU sharing TB cache.
0429a971 349 * @opaque: User data.
93afeade 350 * @mem_io_pc: Host Program Counter at which the memory was accessed.
8737c51c 351 * @kvm_fd: vCPU file descriptor for KVM.
0c0fcc20
EC
352 * @work_mutex: Lock to prevent multiple access to @work_list.
353 * @work_list: List of pending asynchronous work.
d4381116
LV
354 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
355 * to @trace_dstate).
48151859 356 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
54cb65d8 357 * @plugin_mask: Plugin event bitmap. Modified only via async work.
ed860129
PM
358 * @ignore_memory_transaction_failures: Cached copy of the MachineState
359 * flag of the same name: allows the board to suppress calling of the
360 * CPU do_transaction_failed hook function.
dd83b06a
AF
361 *
362 * State of one CPU core or thread.
363 */
364struct CPUState {
365 /*< private >*/
961f8395 366 DeviceState parent_obj;
dd83b06a
AF
367 /*< public >*/
368
ce3960eb
AF
369 int nr_cores;
370 int nr_threads;
371
814e612e 372 struct QemuThread *thread;
bcba2a72
AF
373#ifdef _WIN32
374 HANDLE hThread;
375#endif
9f09e18a 376 int thread_id;
c265e976 377 bool running, has_waiter;
f5c121b8 378 struct QemuCond *halt_cond;
216fc9a4 379 bool thread_kicked;
61a46217 380 bool created;
4fdeee7c 381 bool stop;
f324e766 382 bool stopped;
c1b70158
TJB
383
384 /* Should CPU start in powered-off state? */
385 bool start_powered_off;
386
4c055ab5 387 bool unplug;
bac05aa9 388 bool crash_occurred;
e0c38211 389 bool exit_request;
cfbc3c60 390 bool in_exclusive_context;
9b990ee5 391 uint32_t cflags_next_tb;
8d04fb55 392 /* updates protected by BQL */
259186a7 393 uint32_t interrupt_request;
ed2803da 394 int singlestep_enabled;
e4cd9657 395 int64_t icount_budget;
efee7340 396 int64_t icount_extra;
9c09a251 397 uint64_t random_seed;
6f03bef0 398 sigjmp_buf jmp_env;
bcba2a72 399
376692b9 400 QemuMutex work_mutex;
0c0fcc20 401 QSIMPLEQ_HEAD(, qemu_work_item) work_list;
376692b9 402
32857f4d 403 CPUAddressSpace *cpu_ases;
12ebc9a7 404 int num_ases;
09daed84 405 AddressSpace *as;
6731d864 406 MemoryRegion *memory;
09daed84 407
c05efcb1 408 void *env_ptr; /* CPUArchState */
5e140196 409 IcountDecr *icount_decr_ptr;
7d7500d9 410
f3ced3c5 411 /* Accessed in parallel; all accesses must be atomic */
8cd70437 412 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
7d7500d9 413
eac8b355 414 struct GDBRegisterState *gdb_regs;
a0e372f0 415 int gdb_num_regs;
35143f01 416 int gdb_num_g_regs;
bdc44640 417 QTAILQ_ENTRY(CPUState) node;
d77953b9 418
f0c3c505 419 /* ice debug support */
b58deb34 420 QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
f0c3c505 421
b58deb34 422 QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
ff4700b0
AF
423 CPUWatchpoint *watchpoint_hit;
424
0429a971
AF
425 void *opaque;
426
93afeade
AF
427 /* In order to avoid passing too many arguments to the MMIO helpers,
428 * we store some rarely used information in the CPU context.
429 */
430 uintptr_t mem_io_pc;
93afeade 431
8737c51c 432 int kvm_fd;
a60f24b5 433 struct KVMState *kvm_state;
f7575c96 434 struct kvm_run *kvm_run;
8737c51c 435
d01c05c9 436 /* Used for events with 'vcpu' and *without* the 'disabled' properties */
d4381116 437 DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS);
d01c05c9 438 DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS);
48151859 439
54cb65d8
EC
440 DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX);
441
2f3a57ee 442#ifdef CONFIG_PLUGIN
54cb65d8 443 GArray *plugin_mem_cbs;
2f3a57ee
AB
444 /* saved iotlb data from io_writex */
445 SavedIOTLB saved_iotlb;
446#endif
54cb65d8 447
f5df5baf 448 /* TODO Move common fields from CPUArchState here. */
6fda014e 449 int cpu_index;
7ea7b9ad 450 int cluster_index;
6fda014e 451 uint32_t halted;
99df7dce 452 uint32_t can_do_io;
6fda014e 453 int32_t exception_index;
7e4fb26d 454
99f31832
SAGDR
455 /* shared by kvm, hax and hvf */
456 bool vcpu_dirty;
457
2adcc85d
JH
458 /* Used to keep track of an outstanding cpu throttle thread for migration
459 * autoconverge
460 */
461 bool throttle_thread_scheduled;
462
ed860129
PM
463 bool ignore_memory_transaction_failures;
464
b0cb0a66 465 struct hax_vcpu_state *hax_vcpu;
e3b9ca81 466
c97d6d2c 467 int hvf_fd;
1f871c5e
PM
468
469 /* track IOMMUs whose translations we've cached in the TCG TLB */
470 GArray *iommu_notifiers;
dd83b06a
AF
471};
472
f481ee2d
PB
473typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
474extern CPUTailQ cpus;
475
068a5ea0
EC
476#define first_cpu QTAILQ_FIRST_RCU(&cpus)
477#define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
478#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
bdc44640 479#define CPU_FOREACH_SAFE(cpu, next_cpu) \
068a5ea0 480 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
182735ef 481
f240eb6f 482extern __thread CPUState *current_cpu;
4917cf44 483
f3ced3c5
EC
484static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
485{
486 unsigned int i;
487
488 for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
d73415a3 489 qatomic_set(&cpu->tb_jmp_cache[i], NULL);
f3ced3c5
EC
490 }
491}
492
8d4e9146
FK
493/**
494 * qemu_tcg_mttcg_enabled:
495 * Check whether we are running MultiThread TCG or not.
496 *
497 * Returns: %true if we are in MTTCG mode %false otherwise.
498 */
499extern bool mttcg_enabled;
500#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
501
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AF
502/**
503 * cpu_paging_enabled:
504 * @cpu: The CPU whose state is to be inspected.
505 *
506 * Returns: %true if paging is enabled, %false otherwise.
507 */
508bool cpu_paging_enabled(const CPUState *cpu);
509
a23bbfda
AF
510/**
511 * cpu_get_memory_mapping:
512 * @cpu: The CPU whose memory mappings are to be obtained.
513 * @list: Where to write the memory mappings to.
514 * @errp: Pointer for reporting an #Error.
515 */
516void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
517 Error **errp);
518
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519#if !defined(CONFIG_USER_ONLY)
520
c72bf468
JF
521/**
522 * cpu_write_elf64_note:
523 * @f: pointer to a function that writes memory to a file
524 * @cpu: The CPU whose memory is to be dumped
525 * @cpuid: ID number of the CPU
526 * @opaque: pointer to the CPUState struct
527 */
528int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
529 int cpuid, void *opaque);
530
531/**
532 * cpu_write_elf64_qemunote:
533 * @f: pointer to a function that writes memory to a file
534 * @cpu: The CPU whose memory is to be dumped
535 * @cpuid: ID number of the CPU
536 * @opaque: pointer to the CPUState struct
537 */
538int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
539 void *opaque);
540
541/**
542 * cpu_write_elf32_note:
543 * @f: pointer to a function that writes memory to a file
544 * @cpu: The CPU whose memory is to be dumped
545 * @cpuid: ID number of the CPU
546 * @opaque: pointer to the CPUState struct
547 */
548int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
549 int cpuid, void *opaque);
550
551/**
552 * cpu_write_elf32_qemunote:
553 * @f: pointer to a function that writes memory to a file
554 * @cpu: The CPU whose memory is to be dumped
555 * @cpuid: ID number of the CPU
556 * @opaque: pointer to the CPUState struct
557 */
558int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
559 void *opaque);
dd83b06a 560
c86f106b
AN
561/**
562 * cpu_get_crash_info:
563 * @cpu: The CPU to get crash information for
564 *
565 * Gets the previously saved crash information.
566 * Caller is responsible for freeing the data.
567 */
568GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
569
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570#endif /* !CONFIG_USER_ONLY */
571
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AF
572/**
573 * CPUDumpFlags:
574 * @CPU_DUMP_CODE:
575 * @CPU_DUMP_FPU: dump FPU register state, not just integer
576 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
577 */
578enum CPUDumpFlags {
579 CPU_DUMP_CODE = 0x00010000,
580 CPU_DUMP_FPU = 0x00020000,
581 CPU_DUMP_CCOP = 0x00040000,
582};
583
584/**
585 * cpu_dump_state:
586 * @cpu: The CPU whose state is to be dumped.
90c84c56 587 * @f: If non-null, dump to this stream, else to current print sink.
878096ee
AF
588 *
589 * Dumps CPU state.
590 */
90c84c56 591void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
878096ee
AF
592
593/**
594 * cpu_dump_statistics:
595 * @cpu: The CPU whose state is to be dumped.
878096ee
AF
596 * @flags: Flags what to dump.
597 *
11cb6c15
MA
598 * Dump CPU statistics to the current monitor if we have one, else to
599 * stdout.
878096ee 600 */
11cb6c15 601void cpu_dump_statistics(CPUState *cpu, int flags);
878096ee 602
00b941e5 603#ifndef CONFIG_USER_ONLY
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604/**
605 * cpu_get_phys_page_attrs_debug:
606 * @cpu: The CPU to obtain the physical page address for.
607 * @addr: The virtual address.
608 * @attrs: Updated on return with the memory transaction attributes to use
609 * for this access.
610 *
611 * Obtains the physical page corresponding to a virtual one, together
612 * with the corresponding memory transaction attributes to use for the access.
613 * Use it only for debugging because no protection checks are done.
614 *
615 * Returns: Corresponding physical page address or -1 if no page found.
616 */
617static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
618 MemTxAttrs *attrs)
619{
620 CPUClass *cc = CPU_GET_CLASS(cpu);
621
622 if (cc->get_phys_page_attrs_debug) {
623 return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
624 }
625 /* Fallback for CPUs which don't implement the _attrs_ hook */
626 *attrs = MEMTXATTRS_UNSPECIFIED;
627 return cc->get_phys_page_debug(cpu, addr);
628}
629
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AF
630/**
631 * cpu_get_phys_page_debug:
632 * @cpu: The CPU to obtain the physical page address for.
633 * @addr: The virtual address.
634 *
635 * Obtains the physical page corresponding to a virtual one.
636 * Use it only for debugging because no protection checks are done.
637 *
638 * Returns: Corresponding physical page address or -1 if no page found.
639 */
640static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
641{
1dc6fb1f 642 MemTxAttrs attrs = {};
00b941e5 643
1dc6fb1f 644 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
00b941e5 645}
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646
647/** cpu_asidx_from_attrs:
648 * @cpu: CPU
649 * @attrs: memory transaction attributes
650 *
651 * Returns the address space index specifying the CPU AddressSpace
652 * to use for a memory access with the given transaction attributes.
653 */
654static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
655{
656 CPUClass *cc = CPU_GET_CLASS(cpu);
9c8c334b 657 int ret = 0;
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658
659 if (cc->asidx_from_attrs) {
9c8c334b
RH
660 ret = cc->asidx_from_attrs(cpu, attrs);
661 assert(ret < cpu->num_ases && ret >= 0);
d7f25a9e 662 }
9c8c334b 663 return ret;
d7f25a9e 664}
cfe35d48
PMD
665
666#endif /* CONFIG_USER_ONLY */
00b941e5 667
267f685b
PB
668/**
669 * cpu_list_add:
670 * @cpu: The CPU to be added to the list of CPUs.
671 */
672void cpu_list_add(CPUState *cpu);
673
674/**
675 * cpu_list_remove:
676 * @cpu: The CPU to be removed from the list of CPUs.
677 */
678void cpu_list_remove(CPUState *cpu);
679
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AF
680/**
681 * cpu_reset:
682 * @cpu: The CPU whose state is to be reset.
683 */
684void cpu_reset(CPUState *cpu);
685
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AF
686/**
687 * cpu_class_by_name:
688 * @typename: The CPU base type.
689 * @cpu_model: The model string without any parameters.
690 *
691 * Looks up a CPU #ObjectClass matching name @cpu_model.
692 *
693 * Returns: A #CPUClass or %NULL if not matching class is found.
694 */
695ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
696
3c72234c
IM
697/**
698 * cpu_create:
699 * @typename: The CPU type.
700 *
701 * Instantiates a CPU and realizes the CPU.
702 *
703 * Returns: A #CPUState or %NULL if an error occurred.
704 */
705CPUState *cpu_create(const char *typename);
706
707/**
c1c8cfe5
EH
708 * parse_cpu_option:
709 * @cpu_option: The -cpu option including optional parameters.
3c72234c
IM
710 *
711 * processes optional parameters and registers them as global properties
712 *
4482e05c
IM
713 * Returns: type of CPU to create or prints error and terminates process
714 * if an error occurred.
3c72234c 715 */
c1c8cfe5 716const char *parse_cpu_option(const char *cpu_option);
9262685b 717
3993c6bd 718/**
8c2e1b00 719 * cpu_has_work:
3993c6bd
AF
720 * @cpu: The vCPU to check.
721 *
722 * Checks whether the CPU has work to do.
723 *
724 * Returns: %true if the CPU has work, %false otherwise.
725 */
8c2e1b00
AF
726static inline bool cpu_has_work(CPUState *cpu)
727{
728 CPUClass *cc = CPU_GET_CLASS(cpu);
729
730 g_assert(cc->has_work);
731 return cc->has_work(cpu);
732}
3993c6bd 733
60e82579
AF
734/**
735 * qemu_cpu_is_self:
736 * @cpu: The vCPU to check against.
737 *
738 * Checks whether the caller is executing on the vCPU thread.
739 *
740 * Returns: %true if called from @cpu's thread, %false otherwise.
741 */
742bool qemu_cpu_is_self(CPUState *cpu);
743
c08d7424
AF
744/**
745 * qemu_cpu_kick:
746 * @cpu: The vCPU to kick.
747 *
748 * Kicks @cpu's thread.
749 */
750void qemu_cpu_kick(CPUState *cpu);
751
2fa45344
AF
752/**
753 * cpu_is_stopped:
754 * @cpu: The CPU to check.
755 *
756 * Checks whether the CPU is stopped.
757 *
758 * Returns: %true if run state is not running or if artificially stopped;
759 * %false otherwise.
760 */
761bool cpu_is_stopped(CPUState *cpu);
762
d148d90e
SF
763/**
764 * do_run_on_cpu:
765 * @cpu: The vCPU to run on.
766 * @func: The function to be executed.
767 * @data: Data to pass to the function.
768 * @mutex: Mutex to release while waiting for @func to run.
769 *
770 * Used internally in the implementation of run_on_cpu.
771 */
14e6fe12 772void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
d148d90e
SF
773 QemuMutex *mutex);
774
f100f0b3
AF
775/**
776 * run_on_cpu:
777 * @cpu: The vCPU to run on.
778 * @func: The function to be executed.
779 * @data: Data to pass to the function.
780 *
781 * Schedules the function @func for execution on the vCPU @cpu.
782 */
14e6fe12 783void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
f100f0b3 784
3c02270d
CV
785/**
786 * async_run_on_cpu:
787 * @cpu: The vCPU to run on.
788 * @func: The function to be executed.
789 * @data: Data to pass to the function.
790 *
791 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
792 */
14e6fe12 793void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
3c02270d 794
53f5ed95
PB
795/**
796 * async_safe_run_on_cpu:
797 * @cpu: The vCPU to run on.
798 * @func: The function to be executed.
799 * @data: Data to pass to the function.
800 *
801 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
802 * while all other vCPUs are sleeping.
803 *
804 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
805 * BQL.
806 */
14e6fe12 807void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
53f5ed95 808
cfbc3c60
EC
809/**
810 * cpu_in_exclusive_context()
811 * @cpu: The vCPU to check
812 *
813 * Returns true if @cpu is an exclusive context, for example running
814 * something which has previously been queued via async_safe_run_on_cpu().
815 */
816static inline bool cpu_in_exclusive_context(const CPUState *cpu)
817{
818 return cpu->in_exclusive_context;
819}
820
38d8f5c8
AF
821/**
822 * qemu_get_cpu:
823 * @index: The CPUState@cpu_index value of the CPU to obtain.
824 *
825 * Gets a CPU matching @index.
826 *
827 * Returns: The CPU or %NULL if there is no matching CPU.
828 */
829CPUState *qemu_get_cpu(int index);
830
69e5ff06
IM
831/**
832 * cpu_exists:
833 * @id: Guest-exposed CPU ID to lookup.
834 *
835 * Search for CPU with specified ID.
836 *
837 * Returns: %true - CPU is found, %false - CPU isn't found.
838 */
839bool cpu_exists(int64_t id);
840
5ce46cb3
EH
841/**
842 * cpu_by_arch_id:
843 * @id: Guest-exposed CPU ID of the CPU to obtain.
844 *
845 * Get a CPU with matching @id.
846 *
847 * Returns: The CPU or %NULL if there is no matching CPU.
848 */
849CPUState *cpu_by_arch_id(int64_t id);
850
c3affe56
AF
851/**
852 * cpu_interrupt:
853 * @cpu: The CPU to set an interrupt on.
7e63bc38 854 * @mask: The interrupts to set.
c3affe56
AF
855 *
856 * Invokes the interrupt handler.
857 */
c3affe56
AF
858
859void cpu_interrupt(CPUState *cpu, int mask);
860
47507383
TH
861#ifdef NEED_CPU_H
862
93e22326 863#ifdef CONFIG_SOFTMMU
93e22326 864static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
b35399bb
SS
865 MMUAccessType access_type,
866 int mmu_idx, uintptr_t retaddr)
93e22326
PB
867{
868 CPUClass *cc = CPU_GET_CLASS(cpu);
869
b35399bb 870 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
93e22326 871}
0dff0939
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872
873static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
874 vaddr addr, unsigned size,
875 MMUAccessType access_type,
876 int mmu_idx, MemTxAttrs attrs,
877 MemTxResult response,
878 uintptr_t retaddr)
879{
880 CPUClass *cc = CPU_GET_CLASS(cpu);
881
ed860129 882 if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
0dff0939
PM
883 cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
884 mmu_idx, attrs, response, retaddr);
885 }
886}
c658b94f
AF
887#endif
888
47507383
TH
889#endif /* NEED_CPU_H */
890
2991b890
PC
891/**
892 * cpu_set_pc:
893 * @cpu: The CPU to set the program counter for.
894 * @addr: Program counter value.
895 *
896 * Sets the program counter for a CPU.
897 */
898static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
899{
900 CPUClass *cc = CPU_GET_CLASS(cpu);
901
902 cc->set_pc(cpu, addr);
903}
904
d8ed887b
AF
905/**
906 * cpu_reset_interrupt:
907 * @cpu: The CPU to clear the interrupt on.
908 * @mask: The interrupt mask to clear.
909 *
910 * Resets interrupts on the vCPU @cpu.
911 */
912void cpu_reset_interrupt(CPUState *cpu, int mask);
913
60a3e17a
AF
914/**
915 * cpu_exit:
916 * @cpu: The CPU to exit.
917 *
918 * Requests the CPU @cpu to exit execution.
919 */
920void cpu_exit(CPUState *cpu);
921
2993683b
IM
922/**
923 * cpu_resume:
924 * @cpu: The CPU to resume.
925 *
926 * Resumes CPU, i.e. puts CPU into runnable state.
927 */
928void cpu_resume(CPUState *cpu);
dd83b06a 929
4c055ab5 930/**
2c579042
BR
931 * cpu_remove_sync:
932 * @cpu: The CPU to remove.
933 *
934 * Requests the CPU to be removed and waits till it is removed.
935 */
936void cpu_remove_sync(CPUState *cpu);
937
d148d90e
SF
938/**
939 * process_queued_cpu_work() - process all items on CPU work queue
940 * @cpu: The CPU which work queue to process.
941 */
942void process_queued_cpu_work(CPUState *cpu);
943
ab129972
PB
944/**
945 * cpu_exec_start:
946 * @cpu: The CPU for the current thread.
947 *
948 * Record that a CPU has started execution and can be interrupted with
949 * cpu_exit.
950 */
951void cpu_exec_start(CPUState *cpu);
952
953/**
954 * cpu_exec_end:
955 * @cpu: The CPU for the current thread.
956 *
957 * Record that a CPU has stopped execution and exclusive sections
958 * can be executed without interrupting it.
959 */
960void cpu_exec_end(CPUState *cpu);
961
962/**
963 * start_exclusive:
964 *
965 * Wait for a concurrent exclusive section to end, and then start
966 * a section of work that is run while other CPUs are not running
967 * between cpu_exec_start and cpu_exec_end. CPUs that are running
968 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
969 * during the exclusive section go to sleep until this CPU calls
970 * end_exclusive.
ab129972
PB
971 */
972void start_exclusive(void);
973
974/**
975 * end_exclusive:
976 *
977 * Concludes an exclusive execution section started by start_exclusive.
ab129972
PB
978 */
979void end_exclusive(void);
980
c643bed9
AF
981/**
982 * qemu_init_vcpu:
983 * @cpu: The vCPU to initialize.
984 *
985 * Initializes a vCPU.
986 */
987void qemu_init_vcpu(CPUState *cpu);
988
3825b28f
AF
989#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
990#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
991#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
992
993/**
994 * cpu_single_step:
995 * @cpu: CPU to the flags for.
996 * @enabled: Flags to enable.
997 *
998 * Enables or disables single-stepping for @cpu.
999 */
1000void cpu_single_step(CPUState *cpu, int enabled);
1001
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1002/* Breakpoint/watchpoint flags */
1003#define BP_MEM_READ 0x01
1004#define BP_MEM_WRITE 0x02
1005#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
1006#define BP_STOP_BEFORE_ACCESS 0x04
08225676 1007/* 0x08 currently unused */
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AF
1008#define BP_GDB 0x10
1009#define BP_CPU 0x20
b933066a 1010#define BP_ANY (BP_GDB | BP_CPU)
08225676
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1011#define BP_WATCHPOINT_HIT_READ 0x40
1012#define BP_WATCHPOINT_HIT_WRITE 0x80
1013#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
b3310ab3
AF
1014
1015int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1016 CPUBreakpoint **breakpoint);
1017int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
1018void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
1019void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
1020
b933066a
RH
1021/* Return true if PC matches an installed breakpoint. */
1022static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
1023{
1024 CPUBreakpoint *bp;
1025
1026 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
1027 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1028 if (bp->pc == pc && (bp->flags & mask)) {
1029 return true;
1030 }
1031 }
1032 }
1033 return false;
1034}
1035
74841f04
RH
1036#ifdef CONFIG_USER_ONLY
1037static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1038 int flags, CPUWatchpoint **watchpoint)
1039{
1040 return -ENOSYS;
1041}
1042
1043static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1044 vaddr len, int flags)
1045{
1046 return -ENOSYS;
1047}
1048
1049static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
1050 CPUWatchpoint *wp)
1051{
1052}
1053
1054static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1055{
1056}
0026348b
DH
1057
1058static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
1059 MemTxAttrs atr, int fl, uintptr_t ra)
1060{
1061}
56ad8b00
RH
1062
1063static inline int cpu_watchpoint_address_matches(CPUState *cpu,
1064 vaddr addr, vaddr len)
1065{
1066 return 0;
1067}
74841f04 1068#else
75a34036
AF
1069int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1070 int flags, CPUWatchpoint **watchpoint);
1071int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1072 vaddr len, int flags);
1073void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
1074void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
390734a4
RH
1075
1076/**
1077 * cpu_check_watchpoint:
1078 * @cpu: cpu context
1079 * @addr: guest virtual address
1080 * @len: access length
1081 * @attrs: memory access attributes
1082 * @flags: watchpoint access type
1083 * @ra: unwind return address
1084 *
1085 * Check for a watchpoint hit in [addr, addr+len) of the type
1086 * specified by @flags. Exit via exception with a hit.
1087 */
0026348b
DH
1088void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
1089 MemTxAttrs attrs, int flags, uintptr_t ra);
390734a4
RH
1090
1091/**
1092 * cpu_watchpoint_address_matches:
1093 * @cpu: cpu context
1094 * @addr: guest virtual address
1095 * @len: access length
1096 *
1097 * Return the watchpoint flags that apply to [addr, addr+len).
1098 * If no watchpoint is registered for the range, the result is 0.
1099 */
56ad8b00 1100int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
74841f04 1101#endif
75a34036 1102
63c91552
PB
1103/**
1104 * cpu_get_address_space:
1105 * @cpu: CPU to get address space from
1106 * @asidx: index identifying which address space to get
1107 *
1108 * Return the requested address space of this CPU. @asidx
1109 * specifies which address space to read.
1110 */
1111AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
1112
a47dddd7
AF
1113void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
1114 GCC_FMT_ATTR(2, 3);
39e329e3 1115void cpu_exec_initfn(CPUState *cpu);
ce5b1bbf 1116void cpu_exec_realizefn(CPUState *cpu, Error **errp);
7bbc124e 1117void cpu_exec_unrealizefn(CPUState *cpu);
a47dddd7 1118
c95ac103
TH
1119/**
1120 * target_words_bigendian:
1121 * Returns true if the (default) endianness of the target is big endian,
1122 * false otherwise. Note that in target-specific code, you can use
1123 * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common
1124 * code should normally never need to know about the endianness of the
1125 * target, so please do *not* use this function unless you know very well
1126 * what you are doing!
1127 */
1128bool target_words_bigendian(void);
1129
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1130#ifdef NEED_CPU_H
1131
1a1562f5 1132#ifdef CONFIG_SOFTMMU
8a9358cc 1133extern const VMStateDescription vmstate_cpu_common;
1a1562f5
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1134#else
1135#define vmstate_cpu_common vmstate_dummy
1136#endif
1137
1138#define VMSTATE_CPU() { \
1139 .name = "parent_obj", \
1140 .size = sizeof(CPUState), \
1141 .vmsd = &vmstate_cpu_common, \
1142 .flags = VMS_STRUCT, \
1143 .offset = 0, \
1144}
1145
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1146#endif /* NEED_CPU_H */
1147
a07f953e 1148#define UNASSIGNED_CPU_INDEX -1
7ea7b9ad 1149#define UNASSIGNED_CLUSTER_INDEX -1
a07f953e 1150
dd83b06a 1151#endif