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[mirror_qemu.git] / include / hw / core / cpu.h
CommitLineData
dd83b06a
AF
1/*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20#ifndef QEMU_CPU_H
21#define QEMU_CPU_H
22
961f8395 23#include "hw/qdev-core.h"
3979fca4 24#include "disas/dis-asm.h"
06445fbd 25#include "exec/cpu-common.h"
c658b94f 26#include "exec/hwaddr.h"
66b9b43c 27#include "exec/memattrs.h"
9af23989 28#include "qapi/qapi-types-run-state.h"
48151859 29#include "qemu/bitmap.h"
068a5ea0 30#include "qemu/rcu_queue.h"
bdc44640 31#include "qemu/queue.h"
1de7afc9 32#include "qemu/thread.h"
aa4cf6eb 33#include "qemu/plugin-event.h"
db1015e9 34#include "qom/object.h"
dd83b06a 35
b5ba1cc6
QN
36typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
37 void *opaque);
c72bf468 38
dd83b06a
AF
39/**
40 * SECTION:cpu
41 * @section_id: QEMU-cpu
42 * @title: CPU Class
43 * @short_description: Base class for all CPUs
44 */
45
46#define TYPE_CPU "cpu"
47
0d6d1ab4
AF
48/* Since this macro is used a lot in hot code paths and in conjunction with
49 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
50 * an unchecked cast.
51 */
52#define CPU(obj) ((CPUState *)(obj))
53
6fbdff87
AB
54/*
55 * The class checkers bring in CPU_GET_CLASS() which is potentially
56 * expensive given the eventual call to
57 * object_class_dynamic_cast_assert(). Because of this the CPUState
58 * has a cached value for the class in cs->cc which is set up in
59 * cpu_exec_realizefn() for use in hot code paths.
60 */
db1015e9 61typedef struct CPUClass CPUClass;
8110fa1d
EH
62DECLARE_CLASS_CHECKERS(CPUClass, CPU,
63 TYPE_CPU)
dd83b06a 64
9295b1aa
PMD
65/**
66 * OBJECT_DECLARE_CPU_TYPE:
67 * @CpuInstanceType: instance struct name
68 * @CpuClassType: class struct name
69 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
70 *
71 * This macro is typically used in "cpu-qom.h" header file, and will:
72 *
73 * - create the typedefs for the CPU object and class structs
74 * - register the type for use with g_autoptr
75 * - provide three standard type cast functions
76 *
77 * The object struct and class struct need to be declared manually.
78 */
79#define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
b36e239e
PMD
80 typedef struct ArchCPU CpuInstanceType; \
81 OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
9295b1aa 82
b35399bb
SS
83typedef enum MMUAccessType {
84 MMU_DATA_LOAD = 0,
85 MMU_DATA_STORE = 1,
86 MMU_INST_FETCH = 2
87} MMUAccessType;
88
568496c0 89typedef struct CPUWatchpoint CPUWatchpoint;
dd83b06a 90
78271684
CF
91/* see tcg-cpu-ops.h */
92struct TCGCPUOps;
e9e51b71 93
fb6916dd
CF
94/* see accel-cpu.h */
95struct AccelCPUClass;
96
8b80bd28
PMD
97/* see sysemu-cpu-ops.h */
98struct SysemuCPUOps;
99
dd83b06a
AF
100/**
101 * CPUClass:
2b8c2754
AF
102 * @class_by_name: Callback to map -cpu command line model name to an
103 * instantiatable CPU type.
94a444b2 104 * @parse_features: Callback to parse command line arguments.
91b1df8c 105 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
8c2e1b00 106 * @has_work: Callback for checking if there is work to do.
f3659eee 107 * @memory_rw_debug: Callback for GDB memory access.
878096ee 108 * @dump_state: Callback for dumping state.
5503da4a
TH
109 * @query_cpu_fast:
110 * Fill in target specific information for the "query-cpus-fast"
111 * QAPI call.
997395d3 112 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
42f6ed91
JS
113 * @set_pc: Callback for setting the Program Counter register. This
114 * should have the semantics used by the target architecture when
115 * setting the PC from a source such as an ELF file entry point;
116 * for example on Arm it will also set the Thumb mode bit based
117 * on the least significant bit of the new PC value.
118 * If the target behaviour here is anything other than "set
119 * the PC register to the value passed in" then the target must
120 * also implement the synchronize_from_tb hook.
e4fdf9df
RH
121 * @get_pc: Callback for getting the Program Counter register.
122 * As above, with the semantics of the target architecture.
5b50e790
AF
123 * @gdb_read_register: Callback for letting GDB read a register.
124 * @gdb_write_register: Callback for letting GDB write a register.
5bc31e94
RH
125 * @gdb_adjust_breakpoint: Callback for adjusting the address of a
126 * breakpoint. Used by AVR to handle a gdb mis-feature with
127 * its Harvard architecture split code and data.
a0e372f0 128 * @gdb_num_core_regs: Number of core registers accessible to GDB.
5b24c641 129 * @gdb_core_xml_file: File name for core registers GDB XML description.
2472b6c0
PM
130 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
131 * before the insn which triggers a watchpoint rather than after it.
b3820e6c
DH
132 * @gdb_arch_name: Optional callback that returns the architecture name known
133 * to GDB. The caller must free the returned string with g_free.
200bf5b7
AB
134 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
135 * gdb stub. Returns a pointer to the XML contents for the specified XML file
136 * or NULL if the CPU doesn't have a dynamically generated content for it.
37b9de46 137 * @disas_set_info: Setup architecture specific components of disassembly info
40612000
JB
138 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
139 * address before attempting to match it against watchpoints.
61ad65d0
RH
140 * @deprecation_note: If this CPUClass is deprecated, this field provides
141 * related information.
dd83b06a
AF
142 *
143 * Represents a CPU family or model.
144 */
db1015e9 145struct CPUClass {
dd83b06a 146 /*< private >*/
961f8395 147 DeviceClass parent_class;
dd83b06a
AF
148 /*< public >*/
149
2b8c2754 150 ObjectClass *(*class_by_name)(const char *cpu_model);
62a48a2a 151 void (*parse_features)(const char *typename, char *str, Error **errp);
2b8c2754 152
8c2e1b00 153 bool (*has_work)(CPUState *cpu);
f3659eee
AF
154 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
155 uint8_t *buf, int len, bool is_write);
90c84c56 156 void (*dump_state)(CPUState *cpu, FILE *, int flags);
5503da4a 157 void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value);
997395d3 158 int64_t (*get_arch_id)(CPUState *cpu);
f45748f1 159 void (*set_pc)(CPUState *cpu, vaddr value);
e4fdf9df 160 vaddr (*get_pc)(CPUState *cpu);
a010bdbe 161 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
5b50e790 162 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
5bc31e94 163 vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
b170fce3 164
5b24c641 165 const char *gdb_core_xml_file;
b3820e6c 166 gchar * (*gdb_arch_name)(CPUState *cpu);
200bf5b7 167 const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
37b9de46
PC
168
169 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
55c3ceef 170
61ad65d0 171 const char *deprecation_note;
fb6916dd 172 struct AccelCPUClass *accel_cpu;
e9e51b71 173
8b80bd28
PMD
174 /* when system emulation is not available, this pointer is NULL */
175 const struct SysemuCPUOps *sysemu_ops;
176
78271684 177 /* when TCG is not available, this pointer is NULL */
11906557 178 const struct TCGCPUOps *tcg_ops;
cc3f2be6
CF
179
180 /*
181 * if not NULL, this is called in order for the CPUClass to initialize
182 * class data that depends on the accelerator, see accel/accel-common.c.
183 */
184 void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
dc29f474
RH
185
186 /*
187 * Keep non-pointer data at the end to minimize holes.
188 */
189 int reset_dump_flags;
190 int gdb_num_core_regs;
191 bool gdb_stop_before_watchpoint;
db1015e9 192};
dd83b06a 193
5e140196
RH
194/*
195 * Low 16 bits: number of cycles left, used only in icount mode.
196 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
197 * for this CPU and return to its top level loop (even in non-icount mode).
198 * This allows a single read-compare-cbranch-write sequence to test
199 * for both decrementer underflow and exceptions.
200 */
201typedef union IcountDecr {
202 uint32_t u32;
203 struct {
e03b5686 204#if HOST_BIG_ENDIAN
5e140196
RH
205 uint16_t high;
206 uint16_t low;
28ecfd7a 207#else
5e140196
RH
208 uint16_t low;
209 uint16_t high;
28ecfd7a 210#endif
5e140196
RH
211 } u16;
212} IcountDecr;
28ecfd7a 213
f0c3c505
AF
214typedef struct CPUBreakpoint {
215 vaddr pc;
216 int flags; /* BP_* */
217 QTAILQ_ENTRY(CPUBreakpoint) entry;
218} CPUBreakpoint;
219
568496c0 220struct CPUWatchpoint {
ff4700b0 221 vaddr vaddr;
05068c0d 222 vaddr len;
08225676 223 vaddr hitaddr;
66b9b43c 224 MemTxAttrs hitattrs;
ff4700b0
AF
225 int flags; /* BP_* */
226 QTAILQ_ENTRY(CPUWatchpoint) entry;
568496c0 227};
ff4700b0 228
2f3a57ee
AB
229#ifdef CONFIG_PLUGIN
230/*
231 * For plugins we sometime need to save the resolved iotlb data before
232 * the memory regions get moved around by io_writex.
233 */
234typedef struct SavedIOTLB {
2f3a57ee
AB
235 MemoryRegionSection *section;
236 hwaddr mr_offset;
237} SavedIOTLB;
238#endif
239
a60f24b5 240struct KVMState;
f7575c96 241struct kvm_run;
a60f24b5 242
b0cb0a66 243struct hax_vcpu_state;
b533450e 244struct hvf_vcpu_state;
b0cb0a66 245
4b4629d9 246/* work queue */
14e6fe12
PB
247
248/* The union type allows passing of 64 bit target pointers on 32 bit
249 * hosts in a single parameter
250 */
251typedef union {
252 int host_int;
253 unsigned long host_ulong;
254 void *host_ptr;
255 vaddr target_ptr;
256} run_on_cpu_data;
257
258#define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
259#define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
260#define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
261#define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
262#define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
263
264typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
265
d148d90e 266struct qemu_work_item;
4b4629d9 267
0b8497f0 268#define CPU_UNSET_NUMA_NODE_ID -1
d01c05c9 269#define CPU_TRACE_DSTATE_MAX_EVENTS 32
0b8497f0 270
dd83b06a
AF
271/**
272 * CPUState:
55e5c285 273 * @cpu_index: CPU index (informative).
7ea7b9ad
PM
274 * @cluster_index: Identifies which cluster this CPU is in.
275 * For boards which don't define clusters or for "loose" CPUs not assigned
276 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
277 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
278 * QOM parent.
a371975e
PMD
279 * Under TCG this value is propagated to @tcg_cflags.
280 * See TranslationBlock::TCG CF_CLUSTER_MASK.
6cc9d67c 281 * @tcg_cflags: Pre-computed cflags for this cpu.
ce3960eb
AF
282 * @nr_cores: Number of cores within this CPU package.
283 * @nr_threads: Number of threads within this CPU.
c265e976
PB
284 * @running: #true if CPU is currently running (lockless).
285 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
ab129972 286 * valid under cpu_list_lock.
61a46217 287 * @created: Indicates whether the CPU thread has been successfully created.
259186a7
AF
288 * @interrupt_request: Indicates a pending interrupt request.
289 * @halted: Nonzero if the CPU is in suspended state.
4fdeee7c 290 * @stop: Indicates a pending stop request.
f324e766 291 * @stopped: Indicates the CPU has been artificially stopped.
4c055ab5 292 * @unplug: Indicates a pending CPU unplug request.
bac05aa9 293 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
ed2803da 294 * @singlestep_enabled: Flags for single-stepping.
efee7340 295 * @icount_extra: Instructions until next timer event.
414b15c9
PB
296 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
297 * requires that IO only be performed on the last instruction of a TB
298 * so that interrupts take effect immediately.
32857f4d
PM
299 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
300 * AddressSpaces this CPU has)
12ebc9a7 301 * @num_ases: number of CPUAddressSpaces in @cpu_ases
32857f4d
PM
302 * @as: Pointer to the first AddressSpace, for the convenience of targets which
303 * only have a single AddressSpace
c05efcb1 304 * @env_ptr: Pointer to subclass-specific CPUArchState field.
5e140196 305 * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
eac8b355 306 * @gdb_regs: Additional GDB registers.
a0e372f0 307 * @gdb_num_regs: Number of total registers accessible to GDB.
35143f01 308 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
182735ef 309 * @next_cpu: Next CPU sharing TB cache.
0429a971 310 * @opaque: User data.
93afeade 311 * @mem_io_pc: Host Program Counter at which the memory was accessed.
8737c51c 312 * @kvm_fd: vCPU file descriptor for KVM.
0c0fcc20
EC
313 * @work_mutex: Lock to prevent multiple access to @work_list.
314 * @work_list: List of pending asynchronous work.
d4381116
LV
315 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
316 * to @trace_dstate).
48151859 317 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
54cb65d8 318 * @plugin_mask: Plugin event bitmap. Modified only via async work.
ed860129
PM
319 * @ignore_memory_transaction_failures: Cached copy of the MachineState
320 * flag of the same name: allows the board to suppress calling of the
321 * CPU do_transaction_failed hook function.
b4420f19
PX
322 * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty
323 * ring is enabled.
324 * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU
325 * dirty ring structure.
dd83b06a
AF
326 *
327 * State of one CPU core or thread.
328 */
329struct CPUState {
330 /*< private >*/
961f8395 331 DeviceState parent_obj;
6fbdff87
AB
332 /* cache to avoid expensive CPU_GET_CLASS */
333 CPUClass *cc;
dd83b06a
AF
334 /*< public >*/
335
ce3960eb
AF
336 int nr_cores;
337 int nr_threads;
338
814e612e 339 struct QemuThread *thread;
bcba2a72
AF
340#ifdef _WIN32
341 HANDLE hThread;
c9923550 342 QemuSemaphore sem;
bcba2a72 343#endif
9f09e18a 344 int thread_id;
c265e976 345 bool running, has_waiter;
f5c121b8 346 struct QemuCond *halt_cond;
216fc9a4 347 bool thread_kicked;
61a46217 348 bool created;
4fdeee7c 349 bool stop;
f324e766 350 bool stopped;
c1b70158
TJB
351
352 /* Should CPU start in powered-off state? */
353 bool start_powered_off;
354
4c055ab5 355 bool unplug;
bac05aa9 356 bool crash_occurred;
e0c38211 357 bool exit_request;
df8a6880 358 int exclusive_context_count;
9b990ee5 359 uint32_t cflags_next_tb;
8d04fb55 360 /* updates protected by BQL */
259186a7 361 uint32_t interrupt_request;
ed2803da 362 int singlestep_enabled;
e4cd9657 363 int64_t icount_budget;
efee7340 364 int64_t icount_extra;
9c09a251 365 uint64_t random_seed;
6f03bef0 366 sigjmp_buf jmp_env;
bcba2a72 367
376692b9 368 QemuMutex work_mutex;
0c0fcc20 369 QSIMPLEQ_HEAD(, qemu_work_item) work_list;
376692b9 370
32857f4d 371 CPUAddressSpace *cpu_ases;
12ebc9a7 372 int num_ases;
09daed84 373 AddressSpace *as;
6731d864 374 MemoryRegion *memory;
09daed84 375
1ea4a06a 376 CPUArchState *env_ptr;
5e140196 377 IcountDecr *icount_decr_ptr;
7d7500d9 378
a976a99a 379 CPUJumpCache *tb_jmp_cache;
7d7500d9 380
eac8b355 381 struct GDBRegisterState *gdb_regs;
a0e372f0 382 int gdb_num_regs;
35143f01 383 int gdb_num_g_regs;
bdc44640 384 QTAILQ_ENTRY(CPUState) node;
d77953b9 385
f0c3c505 386 /* ice debug support */
b58deb34 387 QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
f0c3c505 388
b58deb34 389 QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
ff4700b0
AF
390 CPUWatchpoint *watchpoint_hit;
391
0429a971
AF
392 void *opaque;
393
93afeade
AF
394 /* In order to avoid passing too many arguments to the MMIO helpers,
395 * we store some rarely used information in the CPU context.
396 */
397 uintptr_t mem_io_pc;
93afeade 398
b4420f19 399 /* Only used in KVM */
8737c51c 400 int kvm_fd;
a60f24b5 401 struct KVMState *kvm_state;
f7575c96 402 struct kvm_run *kvm_run;
b4420f19
PX
403 struct kvm_dirty_gfn *kvm_dirty_gfns;
404 uint32_t kvm_fetch_index;
7786ae40 405 uint64_t dirty_pages;
8737c51c 406
bd688fc9
EGE
407 /* Use by accel-block: CPU is executing an ioctl() */
408 QemuLockCnt in_ioctl_lock;
409
d01c05c9 410 /* Used for events with 'vcpu' and *without* the 'disabled' properties */
d4381116 411 DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS);
d01c05c9 412 DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS);
48151859 413
54cb65d8
EC
414 DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX);
415
2f3a57ee 416#ifdef CONFIG_PLUGIN
54cb65d8 417 GArray *plugin_mem_cbs;
2f3a57ee
AB
418 /* saved iotlb data from io_writex */
419 SavedIOTLB saved_iotlb;
420#endif
54cb65d8 421
f5df5baf 422 /* TODO Move common fields from CPUArchState here. */
6fda014e 423 int cpu_index;
7ea7b9ad 424 int cluster_index;
6cc9d67c 425 uint32_t tcg_cflags;
6fda014e 426 uint32_t halted;
99df7dce 427 uint32_t can_do_io;
6fda014e 428 int32_t exception_index;
7e4fb26d 429
99f31832
SAGDR
430 /* shared by kvm, hax and hvf */
431 bool vcpu_dirty;
432
2adcc85d
JH
433 /* Used to keep track of an outstanding cpu throttle thread for migration
434 * autoconverge
435 */
436 bool throttle_thread_scheduled;
437
baa60983
HH
438 /*
439 * Sleep throttle_us_per_full microseconds once dirty ring is full
440 * if dirty page rate limit is enabled.
441 */
442 int64_t throttle_us_per_full;
443
ed860129
PM
444 bool ignore_memory_transaction_failures;
445
6e8dcacd
RH
446 /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
447 bool prctl_unalign_sigbus;
448
b0cb0a66 449 struct hax_vcpu_state *hax_vcpu;
e3b9ca81 450
b533450e 451 struct hvf_vcpu_state *hvf;
1f871c5e
PM
452
453 /* track IOMMUs whose translations we've cached in the TCG TLB */
454 GArray *iommu_notifiers;
dd83b06a
AF
455};
456
f481ee2d
PB
457typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
458extern CPUTailQ cpus;
459
068a5ea0
EC
460#define first_cpu QTAILQ_FIRST_RCU(&cpus)
461#define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
462#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
bdc44640 463#define CPU_FOREACH_SAFE(cpu, next_cpu) \
068a5ea0 464 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
182735ef 465
f240eb6f 466extern __thread CPUState *current_cpu;
4917cf44 467
8d4e9146
FK
468/**
469 * qemu_tcg_mttcg_enabled:
470 * Check whether we are running MultiThread TCG or not.
471 *
472 * Returns: %true if we are in MTTCG mode %false otherwise.
473 */
474extern bool mttcg_enabled;
475#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
476
444d5590
AF
477/**
478 * cpu_paging_enabled:
479 * @cpu: The CPU whose state is to be inspected.
480 *
481 * Returns: %true if paging is enabled, %false otherwise.
482 */
483bool cpu_paging_enabled(const CPUState *cpu);
484
a23bbfda
AF
485/**
486 * cpu_get_memory_mapping:
487 * @cpu: The CPU whose memory mappings are to be obtained.
488 * @list: Where to write the memory mappings to.
489 * @errp: Pointer for reporting an #Error.
490 */
491void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
492 Error **errp);
493
cfe35d48
PMD
494#if !defined(CONFIG_USER_ONLY)
495
c72bf468
JF
496/**
497 * cpu_write_elf64_note:
498 * @f: pointer to a function that writes memory to a file
499 * @cpu: The CPU whose memory is to be dumped
500 * @cpuid: ID number of the CPU
501 * @opaque: pointer to the CPUState struct
502 */
503int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
504 int cpuid, void *opaque);
505
506/**
507 * cpu_write_elf64_qemunote:
508 * @f: pointer to a function that writes memory to a file
509 * @cpu: The CPU whose memory is to be dumped
510 * @cpuid: ID number of the CPU
511 * @opaque: pointer to the CPUState struct
512 */
513int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
514 void *opaque);
515
516/**
517 * cpu_write_elf32_note:
518 * @f: pointer to a function that writes memory to a file
519 * @cpu: The CPU whose memory is to be dumped
520 * @cpuid: ID number of the CPU
521 * @opaque: pointer to the CPUState struct
522 */
523int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
524 int cpuid, void *opaque);
525
526/**
527 * cpu_write_elf32_qemunote:
528 * @f: pointer to a function that writes memory to a file
529 * @cpu: The CPU whose memory is to be dumped
530 * @cpuid: ID number of the CPU
531 * @opaque: pointer to the CPUState struct
532 */
533int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
534 void *opaque);
dd83b06a 535
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536/**
537 * cpu_get_crash_info:
538 * @cpu: The CPU to get crash information for
539 *
540 * Gets the previously saved crash information.
541 * Caller is responsible for freeing the data.
542 */
543GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
544
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545#endif /* !CONFIG_USER_ONLY */
546
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547/**
548 * CPUDumpFlags:
549 * @CPU_DUMP_CODE:
550 * @CPU_DUMP_FPU: dump FPU register state, not just integer
551 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
552 */
553enum CPUDumpFlags {
554 CPU_DUMP_CODE = 0x00010000,
555 CPU_DUMP_FPU = 0x00020000,
556 CPU_DUMP_CCOP = 0x00040000,
557};
558
559/**
560 * cpu_dump_state:
561 * @cpu: The CPU whose state is to be dumped.
90c84c56 562 * @f: If non-null, dump to this stream, else to current print sink.
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563 *
564 * Dumps CPU state.
565 */
90c84c56 566void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
878096ee 567
00b941e5 568#ifndef CONFIG_USER_ONLY
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569/**
570 * cpu_get_phys_page_attrs_debug:
571 * @cpu: The CPU to obtain the physical page address for.
572 * @addr: The virtual address.
573 * @attrs: Updated on return with the memory transaction attributes to use
574 * for this access.
575 *
576 * Obtains the physical page corresponding to a virtual one, together
577 * with the corresponding memory transaction attributes to use for the access.
578 * Use it only for debugging because no protection checks are done.
579 *
580 * Returns: Corresponding physical page address or -1 if no page found.
581 */
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582hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
583 MemTxAttrs *attrs);
1dc6fb1f 584
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585/**
586 * cpu_get_phys_page_debug:
587 * @cpu: The CPU to obtain the physical page address for.
588 * @addr: The virtual address.
589 *
590 * Obtains the physical page corresponding to a virtual one.
591 * Use it only for debugging because no protection checks are done.
592 *
593 * Returns: Corresponding physical page address or -1 if no page found.
594 */
a41d3aae 595hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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596
597/** cpu_asidx_from_attrs:
598 * @cpu: CPU
599 * @attrs: memory transaction attributes
600 *
601 * Returns the address space index specifying the CPU AddressSpace
602 * to use for a memory access with the given transaction attributes.
603 */
a41d3aae 604int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
d7f25a9e 605
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606/**
607 * cpu_virtio_is_big_endian:
608 * @cpu: CPU
609
610 * Returns %true if a CPU which supports runtime configurable endianness
611 * is currently big-endian.
612 */
613bool cpu_virtio_is_big_endian(CPUState *cpu);
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614
615#endif /* CONFIG_USER_ONLY */
00b941e5 616
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617/**
618 * cpu_list_add:
619 * @cpu: The CPU to be added to the list of CPUs.
620 */
621void cpu_list_add(CPUState *cpu);
622
623/**
624 * cpu_list_remove:
625 * @cpu: The CPU to be removed from the list of CPUs.
626 */
627void cpu_list_remove(CPUState *cpu);
628
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629/**
630 * cpu_reset:
631 * @cpu: The CPU whose state is to be reset.
632 */
633void cpu_reset(CPUState *cpu);
634
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635/**
636 * cpu_class_by_name:
637 * @typename: The CPU base type.
638 * @cpu_model: The model string without any parameters.
639 *
640 * Looks up a CPU #ObjectClass matching name @cpu_model.
641 *
642 * Returns: A #CPUClass or %NULL if not matching class is found.
643 */
644ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
645
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646/**
647 * cpu_create:
648 * @typename: The CPU type.
649 *
650 * Instantiates a CPU and realizes the CPU.
651 *
652 * Returns: A #CPUState or %NULL if an error occurred.
653 */
654CPUState *cpu_create(const char *typename);
655
656/**
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657 * parse_cpu_option:
658 * @cpu_option: The -cpu option including optional parameters.
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659 *
660 * processes optional parameters and registers them as global properties
661 *
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662 * Returns: type of CPU to create or prints error and terminates process
663 * if an error occurred.
3c72234c 664 */
c1c8cfe5 665const char *parse_cpu_option(const char *cpu_option);
9262685b 666
3993c6bd 667/**
8c2e1b00 668 * cpu_has_work:
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669 * @cpu: The vCPU to check.
670 *
671 * Checks whether the CPU has work to do.
672 *
673 * Returns: %true if the CPU has work, %false otherwise.
674 */
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675static inline bool cpu_has_work(CPUState *cpu)
676{
677 CPUClass *cc = CPU_GET_CLASS(cpu);
678
679 g_assert(cc->has_work);
680 return cc->has_work(cpu);
681}
3993c6bd 682
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683/**
684 * qemu_cpu_is_self:
685 * @cpu: The vCPU to check against.
686 *
687 * Checks whether the caller is executing on the vCPU thread.
688 *
689 * Returns: %true if called from @cpu's thread, %false otherwise.
690 */
691bool qemu_cpu_is_self(CPUState *cpu);
692
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693/**
694 * qemu_cpu_kick:
695 * @cpu: The vCPU to kick.
696 *
697 * Kicks @cpu's thread.
698 */
699void qemu_cpu_kick(CPUState *cpu);
700
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701/**
702 * cpu_is_stopped:
703 * @cpu: The CPU to check.
704 *
705 * Checks whether the CPU is stopped.
706 *
707 * Returns: %true if run state is not running or if artificially stopped;
708 * %false otherwise.
709 */
710bool cpu_is_stopped(CPUState *cpu);
711
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712/**
713 * do_run_on_cpu:
714 * @cpu: The vCPU to run on.
715 * @func: The function to be executed.
716 * @data: Data to pass to the function.
717 * @mutex: Mutex to release while waiting for @func to run.
718 *
719 * Used internally in the implementation of run_on_cpu.
720 */
14e6fe12 721void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
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722 QemuMutex *mutex);
723
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724/**
725 * run_on_cpu:
726 * @cpu: The vCPU to run on.
727 * @func: The function to be executed.
728 * @data: Data to pass to the function.
729 *
730 * Schedules the function @func for execution on the vCPU @cpu.
731 */
14e6fe12 732void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
f100f0b3 733
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734/**
735 * async_run_on_cpu:
736 * @cpu: The vCPU to run on.
737 * @func: The function to be executed.
738 * @data: Data to pass to the function.
739 *
740 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
741 */
14e6fe12 742void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
3c02270d 743
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744/**
745 * async_safe_run_on_cpu:
746 * @cpu: The vCPU to run on.
747 * @func: The function to be executed.
748 * @data: Data to pass to the function.
749 *
750 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
751 * while all other vCPUs are sleeping.
752 *
753 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
754 * BQL.
755 */
14e6fe12 756void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
53f5ed95 757
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758/**
759 * cpu_in_exclusive_context()
760 * @cpu: The vCPU to check
761 *
762 * Returns true if @cpu is an exclusive context, for example running
763 * something which has previously been queued via async_safe_run_on_cpu().
764 */
765static inline bool cpu_in_exclusive_context(const CPUState *cpu)
766{
df8a6880 767 return cpu->exclusive_context_count;
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768}
769
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770/**
771 * qemu_get_cpu:
772 * @index: The CPUState@cpu_index value of the CPU to obtain.
773 *
774 * Gets a CPU matching @index.
775 *
776 * Returns: The CPU or %NULL if there is no matching CPU.
777 */
778CPUState *qemu_get_cpu(int index);
779
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780/**
781 * cpu_exists:
782 * @id: Guest-exposed CPU ID to lookup.
783 *
784 * Search for CPU with specified ID.
785 *
786 * Returns: %true - CPU is found, %false - CPU isn't found.
787 */
788bool cpu_exists(int64_t id);
789
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790/**
791 * cpu_by_arch_id:
792 * @id: Guest-exposed CPU ID of the CPU to obtain.
793 *
794 * Get a CPU with matching @id.
795 *
796 * Returns: The CPU or %NULL if there is no matching CPU.
797 */
798CPUState *cpu_by_arch_id(int64_t id);
799
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800/**
801 * cpu_interrupt:
802 * @cpu: The CPU to set an interrupt on.
7e63bc38 803 * @mask: The interrupts to set.
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804 *
805 * Invokes the interrupt handler.
806 */
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807
808void cpu_interrupt(CPUState *cpu, int mask);
809
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810/**
811 * cpu_set_pc:
812 * @cpu: The CPU to set the program counter for.
813 * @addr: Program counter value.
814 *
815 * Sets the program counter for a CPU.
816 */
817static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
818{
819 CPUClass *cc = CPU_GET_CLASS(cpu);
820
821 cc->set_pc(cpu, addr);
822}
823
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824/**
825 * cpu_reset_interrupt:
826 * @cpu: The CPU to clear the interrupt on.
827 * @mask: The interrupt mask to clear.
828 *
829 * Resets interrupts on the vCPU @cpu.
830 */
831void cpu_reset_interrupt(CPUState *cpu, int mask);
832
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833/**
834 * cpu_exit:
835 * @cpu: The CPU to exit.
836 *
837 * Requests the CPU @cpu to exit execution.
838 */
839void cpu_exit(CPUState *cpu);
840
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841/**
842 * cpu_resume:
843 * @cpu: The CPU to resume.
844 *
845 * Resumes CPU, i.e. puts CPU into runnable state.
846 */
847void cpu_resume(CPUState *cpu);
dd83b06a 848
4c055ab5 849/**
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850 * cpu_remove_sync:
851 * @cpu: The CPU to remove.
852 *
853 * Requests the CPU to be removed and waits till it is removed.
854 */
855void cpu_remove_sync(CPUState *cpu);
856
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857/**
858 * process_queued_cpu_work() - process all items on CPU work queue
859 * @cpu: The CPU which work queue to process.
860 */
861void process_queued_cpu_work(CPUState *cpu);
862
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863/**
864 * cpu_exec_start:
865 * @cpu: The CPU for the current thread.
866 *
867 * Record that a CPU has started execution and can be interrupted with
868 * cpu_exit.
869 */
870void cpu_exec_start(CPUState *cpu);
871
872/**
873 * cpu_exec_end:
874 * @cpu: The CPU for the current thread.
875 *
876 * Record that a CPU has stopped execution and exclusive sections
877 * can be executed without interrupting it.
878 */
879void cpu_exec_end(CPUState *cpu);
880
881/**
882 * start_exclusive:
883 *
884 * Wait for a concurrent exclusive section to end, and then start
885 * a section of work that is run while other CPUs are not running
886 * between cpu_exec_start and cpu_exec_end. CPUs that are running
887 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
888 * during the exclusive section go to sleep until this CPU calls
889 * end_exclusive.
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890 */
891void start_exclusive(void);
892
893/**
894 * end_exclusive:
895 *
896 * Concludes an exclusive execution section started by start_exclusive.
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897 */
898void end_exclusive(void);
899
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900/**
901 * qemu_init_vcpu:
902 * @cpu: The vCPU to initialize.
903 *
904 * Initializes a vCPU.
905 */
906void qemu_init_vcpu(CPUState *cpu);
907
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908#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
909#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
910#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
911
912/**
913 * cpu_single_step:
914 * @cpu: CPU to the flags for.
915 * @enabled: Flags to enable.
916 *
917 * Enables or disables single-stepping for @cpu.
918 */
919void cpu_single_step(CPUState *cpu, int enabled);
920
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921/* Breakpoint/watchpoint flags */
922#define BP_MEM_READ 0x01
923#define BP_MEM_WRITE 0x02
924#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
925#define BP_STOP_BEFORE_ACCESS 0x04
08225676 926/* 0x08 currently unused */
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927#define BP_GDB 0x10
928#define BP_CPU 0x20
b933066a 929#define BP_ANY (BP_GDB | BP_CPU)
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930#define BP_HIT_SHIFT 6
931#define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT)
932#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT)
933#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT)
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934
935int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
936 CPUBreakpoint **breakpoint);
937int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
938void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
939void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
940
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941/* Return true if PC matches an installed breakpoint. */
942static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
943{
944 CPUBreakpoint *bp;
945
946 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
947 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
948 if (bp->pc == pc && (bp->flags & mask)) {
949 return true;
950 }
951 }
952 }
953 return false;
954}
955
87e303de 956#if defined(CONFIG_USER_ONLY)
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957static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
958 int flags, CPUWatchpoint **watchpoint)
959{
960 return -ENOSYS;
961}
962
963static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
964 vaddr len, int flags)
965{
966 return -ENOSYS;
967}
968
969static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
970 CPUWatchpoint *wp)
971{
972}
973
974static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
975{
976}
977#else
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978int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
979 int flags, CPUWatchpoint **watchpoint);
980int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
981 vaddr len, int flags);
982void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
983void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
74841f04 984#endif
75a34036 985
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986/**
987 * cpu_get_address_space:
988 * @cpu: CPU to get address space from
989 * @asidx: index identifying which address space to get
990 *
991 * Return the requested address space of this CPU. @asidx
992 * specifies which address space to read.
993 */
994AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
995
8905770b 996G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...)
9edc6313 997 G_GNUC_PRINTF(2, 3);
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998
999/* $(top_srcdir)/cpu.c */
995b87de 1000void cpu_class_init_props(DeviceClass *dc);
39e329e3 1001void cpu_exec_initfn(CPUState *cpu);
ce5b1bbf 1002void cpu_exec_realizefn(CPUState *cpu, Error **errp);
7bbc124e 1003void cpu_exec_unrealizefn(CPUState *cpu);
a47dddd7 1004
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1005/**
1006 * target_words_bigendian:
1007 * Returns true if the (default) endianness of the target is big endian,
1008 * false otherwise. Note that in target-specific code, you can use
ee3eb3a7 1009 * TARGET_BIG_ENDIAN directly instead. On the other hand, common
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1010 * code should normally never need to know about the endianness of the
1011 * target, so please do *not* use this function unless you know very well
1012 * what you are doing!
1013 */
1014bool target_words_bigendian(void);
1015
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1016const char *target_name(void);
1017
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1018void page_size_init(void);
1019
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1020#ifdef NEED_CPU_H
1021
1a1562f5 1022#ifdef CONFIG_SOFTMMU
feece4d0 1023
8a9358cc 1024extern const VMStateDescription vmstate_cpu_common;
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1025
1026#define VMSTATE_CPU() { \
1027 .name = "parent_obj", \
1028 .size = sizeof(CPUState), \
1029 .vmsd = &vmstate_cpu_common, \
1030 .flags = VMS_STRUCT, \
1031 .offset = 0, \
1032}
feece4d0 1033#endif /* CONFIG_SOFTMMU */
1a1562f5 1034
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1035#endif /* NEED_CPU_H */
1036
a07f953e 1037#define UNASSIGNED_CPU_INDEX -1
7ea7b9ad 1038#define UNASSIGNED_CLUSTER_INDEX -1
a07f953e 1039
dd83b06a 1040#endif