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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
3979fca4 | 24 | #include "disas/dis-asm.h" |
06445fbd | 25 | #include "exec/cpu-common.h" |
c658b94f | 26 | #include "exec/hwaddr.h" |
66b9b43c | 27 | #include "exec/memattrs.h" |
ef6d8210 | 28 | #include "exec/tlb-common.h" |
9af23989 | 29 | #include "qapi/qapi-types-run-state.h" |
48151859 | 30 | #include "qemu/bitmap.h" |
068a5ea0 | 31 | #include "qemu/rcu_queue.h" |
bdc44640 | 32 | #include "qemu/queue.h" |
1de7afc9 | 33 | #include "qemu/thread.h" |
aa4cf6eb | 34 | #include "qemu/plugin-event.h" |
db1015e9 | 35 | #include "qom/object.h" |
dd83b06a | 36 | |
b5ba1cc6 QN |
37 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
38 | void *opaque); | |
c72bf468 | 39 | |
dd83b06a AF |
40 | /** |
41 | * SECTION:cpu | |
42 | * @section_id: QEMU-cpu | |
43 | * @title: CPU Class | |
44 | * @short_description: Base class for all CPUs | |
45 | */ | |
46 | ||
47 | #define TYPE_CPU "cpu" | |
48 | ||
0d6d1ab4 AF |
49 | /* Since this macro is used a lot in hot code paths and in conjunction with |
50 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
51 | * an unchecked cast. | |
52 | */ | |
53 | #define CPU(obj) ((CPUState *)(obj)) | |
54 | ||
6fbdff87 AB |
55 | /* |
56 | * The class checkers bring in CPU_GET_CLASS() which is potentially | |
57 | * expensive given the eventual call to | |
58 | * object_class_dynamic_cast_assert(). Because of this the CPUState | |
59 | * has a cached value for the class in cs->cc which is set up in | |
60 | * cpu_exec_realizefn() for use in hot code paths. | |
61 | */ | |
db1015e9 | 62 | typedef struct CPUClass CPUClass; |
8110fa1d EH |
63 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, |
64 | TYPE_CPU) | |
dd83b06a | 65 | |
9295b1aa PMD |
66 | /** |
67 | * OBJECT_DECLARE_CPU_TYPE: | |
68 | * @CpuInstanceType: instance struct name | |
69 | * @CpuClassType: class struct name | |
70 | * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators | |
71 | * | |
72 | * This macro is typically used in "cpu-qom.h" header file, and will: | |
73 | * | |
74 | * - create the typedefs for the CPU object and class structs | |
75 | * - register the type for use with g_autoptr | |
76 | * - provide three standard type cast functions | |
77 | * | |
78 | * The object struct and class struct need to be declared manually. | |
79 | */ | |
80 | #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \ | |
b36e239e PMD |
81 | typedef struct ArchCPU CpuInstanceType; \ |
82 | OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); | |
9295b1aa | 83 | |
b35399bb SS |
84 | typedef enum MMUAccessType { |
85 | MMU_DATA_LOAD = 0, | |
86 | MMU_DATA_STORE = 1, | |
87 | MMU_INST_FETCH = 2 | |
58e8f1f6 | 88 | #define MMU_ACCESS_COUNT 3 |
b35399bb SS |
89 | } MMUAccessType; |
90 | ||
568496c0 | 91 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 92 | |
78271684 CF |
93 | /* see tcg-cpu-ops.h */ |
94 | struct TCGCPUOps; | |
e9e51b71 | 95 | |
fb6916dd CF |
96 | /* see accel-cpu.h */ |
97 | struct AccelCPUClass; | |
98 | ||
8b80bd28 PMD |
99 | /* see sysemu-cpu-ops.h */ |
100 | struct SysemuCPUOps; | |
101 | ||
dd83b06a AF |
102 | /** |
103 | * CPUClass: | |
2b8c2754 AF |
104 | * @class_by_name: Callback to map -cpu command line model name to an |
105 | * instantiatable CPU type. | |
94a444b2 | 106 | * @parse_features: Callback to parse command line arguments. |
91b1df8c | 107 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 108 | * @has_work: Callback for checking if there is work to do. |
f3659eee | 109 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee | 110 | * @dump_state: Callback for dumping state. |
5503da4a TH |
111 | * @query_cpu_fast: |
112 | * Fill in target specific information for the "query-cpus-fast" | |
113 | * QAPI call. | |
997395d3 | 114 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
42f6ed91 JS |
115 | * @set_pc: Callback for setting the Program Counter register. This |
116 | * should have the semantics used by the target architecture when | |
117 | * setting the PC from a source such as an ELF file entry point; | |
118 | * for example on Arm it will also set the Thumb mode bit based | |
119 | * on the least significant bit of the new PC value. | |
120 | * If the target behaviour here is anything other than "set | |
121 | * the PC register to the value passed in" then the target must | |
122 | * also implement the synchronize_from_tb hook. | |
e4fdf9df RH |
123 | * @get_pc: Callback for getting the Program Counter register. |
124 | * As above, with the semantics of the target architecture. | |
5b50e790 AF |
125 | * @gdb_read_register: Callback for letting GDB read a register. |
126 | * @gdb_write_register: Callback for letting GDB write a register. | |
5bc31e94 RH |
127 | * @gdb_adjust_breakpoint: Callback for adjusting the address of a |
128 | * breakpoint. Used by AVR to handle a gdb mis-feature with | |
129 | * its Harvard architecture split code and data. | |
a0e372f0 | 130 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 131 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
132 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
133 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
134 | * @gdb_arch_name: Optional callback that returns the architecture name known |
135 | * to GDB. The caller must free the returned string with g_free. | |
200bf5b7 AB |
136 | * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the |
137 | * gdb stub. Returns a pointer to the XML contents for the specified XML file | |
138 | * or NULL if the CPU doesn't have a dynamically generated content for it. | |
37b9de46 | 139 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
140 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
141 | * address before attempting to match it against watchpoints. | |
61ad65d0 RH |
142 | * @deprecation_note: If this CPUClass is deprecated, this field provides |
143 | * related information. | |
dd83b06a AF |
144 | * |
145 | * Represents a CPU family or model. | |
146 | */ | |
db1015e9 | 147 | struct CPUClass { |
dd83b06a | 148 | /*< private >*/ |
961f8395 | 149 | DeviceClass parent_class; |
dd83b06a AF |
150 | /*< public >*/ |
151 | ||
2b8c2754 | 152 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 153 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 154 | |
8c2e1b00 | 155 | bool (*has_work)(CPUState *cpu); |
f3659eee AF |
156 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
157 | uint8_t *buf, int len, bool is_write); | |
90c84c56 | 158 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
5503da4a | 159 | void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); |
997395d3 | 160 | int64_t (*get_arch_id)(CPUState *cpu); |
f45748f1 | 161 | void (*set_pc)(CPUState *cpu, vaddr value); |
e4fdf9df | 162 | vaddr (*get_pc)(CPUState *cpu); |
a010bdbe | 163 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
5b50e790 | 164 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
5bc31e94 | 165 | vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); |
b170fce3 | 166 | |
5b24c641 | 167 | const char *gdb_core_xml_file; |
b3820e6c | 168 | gchar * (*gdb_arch_name)(CPUState *cpu); |
200bf5b7 | 169 | const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); |
37b9de46 PC |
170 | |
171 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
55c3ceef | 172 | |
61ad65d0 | 173 | const char *deprecation_note; |
fb6916dd | 174 | struct AccelCPUClass *accel_cpu; |
e9e51b71 | 175 | |
8b80bd28 PMD |
176 | /* when system emulation is not available, this pointer is NULL */ |
177 | const struct SysemuCPUOps *sysemu_ops; | |
178 | ||
78271684 | 179 | /* when TCG is not available, this pointer is NULL */ |
11906557 | 180 | const struct TCGCPUOps *tcg_ops; |
cc3f2be6 CF |
181 | |
182 | /* | |
183 | * if not NULL, this is called in order for the CPUClass to initialize | |
184 | * class data that depends on the accelerator, see accel/accel-common.c. | |
185 | */ | |
186 | void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc); | |
dc29f474 RH |
187 | |
188 | /* | |
189 | * Keep non-pointer data at the end to minimize holes. | |
190 | */ | |
191 | int reset_dump_flags; | |
192 | int gdb_num_core_regs; | |
193 | bool gdb_stop_before_watchpoint; | |
db1015e9 | 194 | }; |
dd83b06a | 195 | |
ef6d8210 RH |
196 | /* |
197 | * Fix the number of mmu modes to 16, which is also the maximum | |
198 | * supported by the softmmu tlb api. | |
199 | */ | |
200 | #define NB_MMU_MODES 16 | |
201 | ||
202 | /* Use a fully associative victim tlb of 8 entries. */ | |
203 | #define CPU_VTLB_SIZE 8 | |
204 | ||
205 | /* | |
206 | * The full TLB entry, which is not accessed by generated TCG code, | |
207 | * so the layout is not as critical as that of CPUTLBEntry. This is | |
208 | * also why we don't want to combine the two structs. | |
209 | */ | |
210 | typedef struct CPUTLBEntryFull { | |
211 | /* | |
212 | * @xlat_section contains: | |
213 | * - in the lower TARGET_PAGE_BITS, a physical section number | |
214 | * - with the lower TARGET_PAGE_BITS masked off, an offset which | |
215 | * must be added to the virtual address to obtain: | |
216 | * + the ram_addr_t of the target RAM (if the physical section | |
217 | * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) | |
218 | * + the offset within the target MemoryRegion (otherwise) | |
219 | */ | |
220 | hwaddr xlat_section; | |
221 | ||
222 | /* | |
223 | * @phys_addr contains the physical address in the address space | |
224 | * given by cpu_asidx_from_attrs(cpu, @attrs). | |
225 | */ | |
226 | hwaddr phys_addr; | |
227 | ||
228 | /* @attrs contains the memory transaction attributes for the page. */ | |
229 | MemTxAttrs attrs; | |
230 | ||
231 | /* @prot contains the complete protections for the page. */ | |
232 | uint8_t prot; | |
233 | ||
234 | /* @lg_page_size contains the log2 of the page size. */ | |
235 | uint8_t lg_page_size; | |
236 | ||
237 | /* | |
238 | * Additional tlb flags for use by the slow path. If non-zero, | |
239 | * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. | |
240 | */ | |
241 | uint8_t slow_flags[MMU_ACCESS_COUNT]; | |
242 | ||
243 | /* | |
244 | * Allow target-specific additions to this structure. | |
245 | * This may be used to cache items from the guest cpu | |
246 | * page tables for later use by the implementation. | |
247 | */ | |
248 | union { | |
249 | /* | |
250 | * Cache the attrs and shareability fields from the page table entry. | |
251 | * | |
252 | * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. | |
253 | * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. | |
254 | * For shareability and guarded, as in the SH and GP fields respectively | |
255 | * of the VMSAv8-64 PTEs. | |
256 | */ | |
257 | struct { | |
258 | uint8_t pte_attrs; | |
259 | uint8_t shareability; | |
260 | bool guarded; | |
261 | } arm; | |
262 | } extra; | |
263 | } CPUTLBEntryFull; | |
264 | ||
265 | /* | |
266 | * Data elements that are per MMU mode, minus the bits accessed by | |
267 | * the TCG fast path. | |
268 | */ | |
269 | typedef struct CPUTLBDesc { | |
270 | /* | |
271 | * Describe a region covering all of the large pages allocated | |
272 | * into the tlb. When any page within this region is flushed, | |
273 | * we must flush the entire tlb. The region is matched if | |
274 | * (addr & large_page_mask) == large_page_addr. | |
275 | */ | |
276 | vaddr large_page_addr; | |
277 | vaddr large_page_mask; | |
278 | /* host time (in ns) at the beginning of the time window */ | |
279 | int64_t window_begin_ns; | |
280 | /* maximum number of entries observed in the window */ | |
281 | size_t window_max_entries; | |
282 | size_t n_used_entries; | |
283 | /* The next index to use in the tlb victim table. */ | |
284 | size_t vindex; | |
285 | /* The tlb victim table, in two parts. */ | |
286 | CPUTLBEntry vtable[CPU_VTLB_SIZE]; | |
287 | CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; | |
288 | CPUTLBEntryFull *fulltlb; | |
289 | } CPUTLBDesc; | |
290 | ||
291 | /* | |
292 | * Data elements that are shared between all MMU modes. | |
293 | */ | |
294 | typedef struct CPUTLBCommon { | |
295 | /* Serialize updates to f.table and d.vtable, and others as noted. */ | |
296 | QemuSpin lock; | |
297 | /* | |
298 | * Within dirty, for each bit N, modifications have been made to | |
299 | * mmu_idx N since the last time that mmu_idx was flushed. | |
300 | * Protected by tlb_c.lock. | |
301 | */ | |
302 | uint16_t dirty; | |
303 | /* | |
304 | * Statistics. These are not lock protected, but are read and | |
305 | * written atomically. This allows the monitor to print a snapshot | |
306 | * of the stats without interfering with the cpu. | |
307 | */ | |
308 | size_t full_flush_count; | |
309 | size_t part_flush_count; | |
310 | size_t elide_flush_count; | |
311 | } CPUTLBCommon; | |
312 | ||
313 | /* | |
314 | * The entire softmmu tlb, for all MMU modes. | |
315 | * The meaning of each of the MMU modes is defined in the target code. | |
316 | * Since this is placed within CPUNegativeOffsetState, the smallest | |
317 | * negative offsets are at the end of the struct. | |
318 | */ | |
319 | typedef struct CPUTLB { | |
320 | #ifdef CONFIG_TCG | |
321 | CPUTLBCommon c; | |
322 | CPUTLBDesc d[NB_MMU_MODES]; | |
323 | CPUTLBDescFast f[NB_MMU_MODES]; | |
324 | #endif | |
325 | } CPUTLB; | |
326 | ||
5e140196 RH |
327 | /* |
328 | * Low 16 bits: number of cycles left, used only in icount mode. | |
329 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs | |
330 | * for this CPU and return to its top level loop (even in non-icount mode). | |
331 | * This allows a single read-compare-cbranch-write sequence to test | |
332 | * for both decrementer underflow and exceptions. | |
333 | */ | |
334 | typedef union IcountDecr { | |
335 | uint32_t u32; | |
336 | struct { | |
e03b5686 | 337 | #if HOST_BIG_ENDIAN |
5e140196 RH |
338 | uint16_t high; |
339 | uint16_t low; | |
28ecfd7a | 340 | #else |
5e140196 RH |
341 | uint16_t low; |
342 | uint16_t high; | |
28ecfd7a | 343 | #endif |
5e140196 RH |
344 | } u16; |
345 | } IcountDecr; | |
28ecfd7a | 346 | |
ef6d8210 | 347 | /* |
3b3d7df5 RH |
348 | * Elements of CPUState most efficiently accessed from CPUArchState, |
349 | * via small negative offsets. | |
ef6d8210 RH |
350 | */ |
351 | typedef struct CPUNegativeOffsetState { | |
352 | CPUTLB tlb; | |
353 | IcountDecr icount_decr; | |
464dacf6 | 354 | bool can_do_io; |
ef6d8210 RH |
355 | } CPUNegativeOffsetState; |
356 | ||
f0c3c505 AF |
357 | typedef struct CPUBreakpoint { |
358 | vaddr pc; | |
359 | int flags; /* BP_* */ | |
360 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
361 | } CPUBreakpoint; | |
362 | ||
568496c0 | 363 | struct CPUWatchpoint { |
ff4700b0 | 364 | vaddr vaddr; |
05068c0d | 365 | vaddr len; |
08225676 | 366 | vaddr hitaddr; |
66b9b43c | 367 | MemTxAttrs hitattrs; |
ff4700b0 AF |
368 | int flags; /* BP_* */ |
369 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 370 | }; |
ff4700b0 | 371 | |
a60f24b5 | 372 | struct KVMState; |
f7575c96 | 373 | struct kvm_run; |
a60f24b5 | 374 | |
4b4629d9 | 375 | /* work queue */ |
14e6fe12 PB |
376 | |
377 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
378 | * hosts in a single parameter | |
379 | */ | |
380 | typedef union { | |
381 | int host_int; | |
382 | unsigned long host_ulong; | |
383 | void *host_ptr; | |
384 | vaddr target_ptr; | |
385 | } run_on_cpu_data; | |
386 | ||
387 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
388 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
389 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
390 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
391 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
392 | ||
393 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
394 | ||
d148d90e | 395 | struct qemu_work_item; |
4b4629d9 | 396 | |
0b8497f0 IM |
397 | #define CPU_UNSET_NUMA_NODE_ID -1 |
398 | ||
dd83b06a AF |
399 | /** |
400 | * CPUState: | |
55e5c285 | 401 | * @cpu_index: CPU index (informative). |
7ea7b9ad PM |
402 | * @cluster_index: Identifies which cluster this CPU is in. |
403 | * For boards which don't define clusters or for "loose" CPUs not assigned | |
404 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will | |
405 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER | |
406 | * QOM parent. | |
a371975e PMD |
407 | * Under TCG this value is propagated to @tcg_cflags. |
408 | * See TranslationBlock::TCG CF_CLUSTER_MASK. | |
6cc9d67c | 409 | * @tcg_cflags: Pre-computed cflags for this cpu. |
ce3960eb AF |
410 | * @nr_cores: Number of cores within this CPU package. |
411 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
412 | * @running: #true if CPU is currently running (lockless). |
413 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 414 | * valid under cpu_list_lock. |
61a46217 | 415 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
416 | * @interrupt_request: Indicates a pending interrupt request. |
417 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 418 | * @stop: Indicates a pending stop request. |
f324e766 | 419 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 420 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 421 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 422 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 423 | * @icount_extra: Instructions until next timer event. |
464dacf6 | 424 | * @neg.can_do_io: True if memory-mapped IO is allowed. |
32857f4d PM |
425 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
426 | * AddressSpaces this CPU has) | |
12ebc9a7 | 427 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
428 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
429 | * only have a single AddressSpace | |
eac8b355 | 430 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 431 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 432 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 433 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 434 | * @opaque: User data. |
93afeade | 435 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
f861b3f3 | 436 | * @accel: Pointer to accelerator specific state. |
8737c51c | 437 | * @kvm_fd: vCPU file descriptor for KVM. |
0c0fcc20 EC |
438 | * @work_mutex: Lock to prevent multiple access to @work_list. |
439 | * @work_list: List of pending asynchronous work. | |
d4381116 LV |
440 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
441 | * to @trace_dstate). | |
48151859 | 442 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
54cb65d8 | 443 | * @plugin_mask: Plugin event bitmap. Modified only via async work. |
ed860129 PM |
444 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
445 | * flag of the same name: allows the board to suppress calling of the | |
446 | * CPU do_transaction_failed hook function. | |
b4420f19 PX |
447 | * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty |
448 | * ring is enabled. | |
449 | * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU | |
450 | * dirty ring structure. | |
dd83b06a AF |
451 | * |
452 | * State of one CPU core or thread. | |
3b3d7df5 RH |
453 | * |
454 | * Align, in order to match possible alignment required by CPUArchState, | |
455 | * and eliminate a hole between CPUState and CPUArchState within ArchCPU. | |
dd83b06a AF |
456 | */ |
457 | struct CPUState { | |
458 | /*< private >*/ | |
961f8395 | 459 | DeviceState parent_obj; |
6fbdff87 AB |
460 | /* cache to avoid expensive CPU_GET_CLASS */ |
461 | CPUClass *cc; | |
dd83b06a AF |
462 | /*< public >*/ |
463 | ||
ce3960eb AF |
464 | int nr_cores; |
465 | int nr_threads; | |
466 | ||
814e612e | 467 | struct QemuThread *thread; |
bcba2a72 | 468 | #ifdef _WIN32 |
c9923550 | 469 | QemuSemaphore sem; |
bcba2a72 | 470 | #endif |
9f09e18a | 471 | int thread_id; |
c265e976 | 472 | bool running, has_waiter; |
f5c121b8 | 473 | struct QemuCond *halt_cond; |
216fc9a4 | 474 | bool thread_kicked; |
61a46217 | 475 | bool created; |
4fdeee7c | 476 | bool stop; |
f324e766 | 477 | bool stopped; |
c1b70158 TJB |
478 | |
479 | /* Should CPU start in powered-off state? */ | |
480 | bool start_powered_off; | |
481 | ||
4c055ab5 | 482 | bool unplug; |
bac05aa9 | 483 | bool crash_occurred; |
e0c38211 | 484 | bool exit_request; |
df8a6880 | 485 | int exclusive_context_count; |
9b990ee5 | 486 | uint32_t cflags_next_tb; |
8d04fb55 | 487 | /* updates protected by BQL */ |
259186a7 | 488 | uint32_t interrupt_request; |
ed2803da | 489 | int singlestep_enabled; |
e4cd9657 | 490 | int64_t icount_budget; |
efee7340 | 491 | int64_t icount_extra; |
9c09a251 | 492 | uint64_t random_seed; |
6f03bef0 | 493 | sigjmp_buf jmp_env; |
bcba2a72 | 494 | |
376692b9 | 495 | QemuMutex work_mutex; |
0c0fcc20 | 496 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
376692b9 | 497 | |
32857f4d | 498 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 499 | int num_ases; |
09daed84 | 500 | AddressSpace *as; |
6731d864 | 501 | MemoryRegion *memory; |
09daed84 | 502 | |
a976a99a | 503 | CPUJumpCache *tb_jmp_cache; |
7d7500d9 | 504 | |
eac8b355 | 505 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 506 | int gdb_num_regs; |
35143f01 | 507 | int gdb_num_g_regs; |
bdc44640 | 508 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 509 | |
f0c3c505 | 510 | /* ice debug support */ |
b58deb34 | 511 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
f0c3c505 | 512 | |
b58deb34 | 513 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
ff4700b0 AF |
514 | CPUWatchpoint *watchpoint_hit; |
515 | ||
0429a971 AF |
516 | void *opaque; |
517 | ||
93afeade AF |
518 | /* In order to avoid passing too many arguments to the MMIO helpers, |
519 | * we store some rarely used information in the CPU context. | |
520 | */ | |
521 | uintptr_t mem_io_pc; | |
93afeade | 522 | |
b4420f19 | 523 | /* Only used in KVM */ |
8737c51c | 524 | int kvm_fd; |
a60f24b5 | 525 | struct KVMState *kvm_state; |
f7575c96 | 526 | struct kvm_run *kvm_run; |
b4420f19 PX |
527 | struct kvm_dirty_gfn *kvm_dirty_gfns; |
528 | uint32_t kvm_fetch_index; | |
7786ae40 | 529 | uint64_t dirty_pages; |
3b6f4852 | 530 | int kvm_vcpu_stats_fd; |
8737c51c | 531 | |
bd688fc9 EGE |
532 | /* Use by accel-block: CPU is executing an ioctl() */ |
533 | QemuLockCnt in_ioctl_lock; | |
534 | ||
54cb65d8 EC |
535 | DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); |
536 | ||
2f3a57ee | 537 | #ifdef CONFIG_PLUGIN |
54cb65d8 | 538 | GArray *plugin_mem_cbs; |
c5ffd16b | 539 | #endif |
54cb65d8 | 540 | |
f5df5baf | 541 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e | 542 | int cpu_index; |
7ea7b9ad | 543 | int cluster_index; |
6cc9d67c | 544 | uint32_t tcg_cflags; |
6fda014e | 545 | uint32_t halted; |
6fda014e | 546 | int32_t exception_index; |
7e4fb26d | 547 | |
f861b3f3 | 548 | AccelCPUState *accel; |
b91b0fc1 | 549 | /* shared by kvm and hvf */ |
99f31832 SAGDR |
550 | bool vcpu_dirty; |
551 | ||
2adcc85d JH |
552 | /* Used to keep track of an outstanding cpu throttle thread for migration |
553 | * autoconverge | |
554 | */ | |
555 | bool throttle_thread_scheduled; | |
556 | ||
baa60983 HH |
557 | /* |
558 | * Sleep throttle_us_per_full microseconds once dirty ring is full | |
559 | * if dirty page rate limit is enabled. | |
560 | */ | |
561 | int64_t throttle_us_per_full; | |
562 | ||
ed860129 PM |
563 | bool ignore_memory_transaction_failures; |
564 | ||
6e8dcacd RH |
565 | /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ |
566 | bool prctl_unalign_sigbus; | |
567 | ||
1f871c5e PM |
568 | /* track IOMMUs whose translations we've cached in the TCG TLB */ |
569 | GArray *iommu_notifiers; | |
3b3d7df5 RH |
570 | |
571 | /* | |
572 | * MUST BE LAST in order to minimize the displacement to CPUArchState. | |
573 | */ | |
574 | char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16); | |
575 | CPUNegativeOffsetState neg; | |
dd83b06a AF |
576 | }; |
577 | ||
3b3d7df5 RH |
578 | /* Validate placement of CPUNegativeOffsetState. */ |
579 | QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) != | |
580 | sizeof(CPUState) - sizeof(CPUNegativeOffsetState)); | |
581 | ||
b77af26e RH |
582 | static inline CPUArchState *cpu_env(CPUState *cpu) |
583 | { | |
584 | /* We validate that CPUArchState follows CPUState in cpu-all.h. */ | |
585 | return (CPUArchState *)(cpu + 1); | |
586 | } | |
587 | ||
f481ee2d PB |
588 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
589 | extern CPUTailQ cpus; | |
590 | ||
068a5ea0 EC |
591 | #define first_cpu QTAILQ_FIRST_RCU(&cpus) |
592 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) | |
593 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) | |
bdc44640 | 594 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
068a5ea0 | 595 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) |
182735ef | 596 | |
f240eb6f | 597 | extern __thread CPUState *current_cpu; |
4917cf44 | 598 | |
8d4e9146 FK |
599 | /** |
600 | * qemu_tcg_mttcg_enabled: | |
601 | * Check whether we are running MultiThread TCG or not. | |
602 | * | |
603 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
604 | */ | |
605 | extern bool mttcg_enabled; | |
606 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
607 | ||
444d5590 AF |
608 | /** |
609 | * cpu_paging_enabled: | |
610 | * @cpu: The CPU whose state is to be inspected. | |
611 | * | |
612 | * Returns: %true if paging is enabled, %false otherwise. | |
613 | */ | |
614 | bool cpu_paging_enabled(const CPUState *cpu); | |
615 | ||
a23bbfda AF |
616 | /** |
617 | * cpu_get_memory_mapping: | |
618 | * @cpu: The CPU whose memory mappings are to be obtained. | |
619 | * @list: Where to write the memory mappings to. | |
620 | * @errp: Pointer for reporting an #Error. | |
621 | */ | |
622 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
623 | Error **errp); | |
624 | ||
cfe35d48 PMD |
625 | #if !defined(CONFIG_USER_ONLY) |
626 | ||
c72bf468 JF |
627 | /** |
628 | * cpu_write_elf64_note: | |
629 | * @f: pointer to a function that writes memory to a file | |
630 | * @cpu: The CPU whose memory is to be dumped | |
631 | * @cpuid: ID number of the CPU | |
632 | * @opaque: pointer to the CPUState struct | |
633 | */ | |
634 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
635 | int cpuid, void *opaque); | |
636 | ||
637 | /** | |
638 | * cpu_write_elf64_qemunote: | |
639 | * @f: pointer to a function that writes memory to a file | |
640 | * @cpu: The CPU whose memory is to be dumped | |
641 | * @cpuid: ID number of the CPU | |
642 | * @opaque: pointer to the CPUState struct | |
643 | */ | |
644 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
645 | void *opaque); | |
646 | ||
647 | /** | |
648 | * cpu_write_elf32_note: | |
649 | * @f: pointer to a function that writes memory to a file | |
650 | * @cpu: The CPU whose memory is to be dumped | |
651 | * @cpuid: ID number of the CPU | |
652 | * @opaque: pointer to the CPUState struct | |
653 | */ | |
654 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
655 | int cpuid, void *opaque); | |
656 | ||
657 | /** | |
658 | * cpu_write_elf32_qemunote: | |
659 | * @f: pointer to a function that writes memory to a file | |
660 | * @cpu: The CPU whose memory is to be dumped | |
661 | * @cpuid: ID number of the CPU | |
662 | * @opaque: pointer to the CPUState struct | |
663 | */ | |
664 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
665 | void *opaque); | |
dd83b06a | 666 | |
c86f106b AN |
667 | /** |
668 | * cpu_get_crash_info: | |
669 | * @cpu: The CPU to get crash information for | |
670 | * | |
671 | * Gets the previously saved crash information. | |
672 | * Caller is responsible for freeing the data. | |
673 | */ | |
674 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
675 | ||
cfe35d48 PMD |
676 | #endif /* !CONFIG_USER_ONLY */ |
677 | ||
878096ee AF |
678 | /** |
679 | * CPUDumpFlags: | |
680 | * @CPU_DUMP_CODE: | |
681 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
682 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
b84694de | 683 | * @CPU_DUMP_VPU: dump VPU registers |
878096ee AF |
684 | */ |
685 | enum CPUDumpFlags { | |
686 | CPU_DUMP_CODE = 0x00010000, | |
687 | CPU_DUMP_FPU = 0x00020000, | |
688 | CPU_DUMP_CCOP = 0x00040000, | |
b84694de | 689 | CPU_DUMP_VPU = 0x00080000, |
878096ee AF |
690 | }; |
691 | ||
692 | /** | |
693 | * cpu_dump_state: | |
694 | * @cpu: The CPU whose state is to be dumped. | |
90c84c56 | 695 | * @f: If non-null, dump to this stream, else to current print sink. |
878096ee AF |
696 | * |
697 | * Dumps CPU state. | |
698 | */ | |
90c84c56 | 699 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
878096ee | 700 | |
00b941e5 | 701 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
702 | /** |
703 | * cpu_get_phys_page_attrs_debug: | |
704 | * @cpu: The CPU to obtain the physical page address for. | |
705 | * @addr: The virtual address. | |
706 | * @attrs: Updated on return with the memory transaction attributes to use | |
707 | * for this access. | |
708 | * | |
709 | * Obtains the physical page corresponding to a virtual one, together | |
710 | * with the corresponding memory transaction attributes to use for the access. | |
711 | * Use it only for debugging because no protection checks are done. | |
712 | * | |
713 | * Returns: Corresponding physical page address or -1 if no page found. | |
714 | */ | |
a41d3aae PMD |
715 | hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
716 | MemTxAttrs *attrs); | |
1dc6fb1f | 717 | |
00b941e5 AF |
718 | /** |
719 | * cpu_get_phys_page_debug: | |
720 | * @cpu: The CPU to obtain the physical page address for. | |
721 | * @addr: The virtual address. | |
722 | * | |
723 | * Obtains the physical page corresponding to a virtual one. | |
724 | * Use it only for debugging because no protection checks are done. | |
725 | * | |
726 | * Returns: Corresponding physical page address or -1 if no page found. | |
727 | */ | |
a41d3aae | 728 | hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
d7f25a9e PM |
729 | |
730 | /** cpu_asidx_from_attrs: | |
731 | * @cpu: CPU | |
732 | * @attrs: memory transaction attributes | |
733 | * | |
734 | * Returns the address space index specifying the CPU AddressSpace | |
735 | * to use for a memory access with the given transaction attributes. | |
736 | */ | |
a41d3aae | 737 | int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); |
d7f25a9e | 738 | |
cdba7e2f PMD |
739 | /** |
740 | * cpu_virtio_is_big_endian: | |
741 | * @cpu: CPU | |
742 | ||
743 | * Returns %true if a CPU which supports runtime configurable endianness | |
744 | * is currently big-endian. | |
745 | */ | |
746 | bool cpu_virtio_is_big_endian(CPUState *cpu); | |
cfe35d48 PMD |
747 | |
748 | #endif /* CONFIG_USER_ONLY */ | |
00b941e5 | 749 | |
267f685b PB |
750 | /** |
751 | * cpu_list_add: | |
752 | * @cpu: The CPU to be added to the list of CPUs. | |
753 | */ | |
754 | void cpu_list_add(CPUState *cpu); | |
755 | ||
756 | /** | |
757 | * cpu_list_remove: | |
758 | * @cpu: The CPU to be removed from the list of CPUs. | |
759 | */ | |
760 | void cpu_list_remove(CPUState *cpu); | |
761 | ||
dd83b06a AF |
762 | /** |
763 | * cpu_reset: | |
764 | * @cpu: The CPU whose state is to be reset. | |
765 | */ | |
766 | void cpu_reset(CPUState *cpu); | |
767 | ||
2b8c2754 AF |
768 | /** |
769 | * cpu_class_by_name: | |
770 | * @typename: The CPU base type. | |
771 | * @cpu_model: The model string without any parameters. | |
772 | * | |
773 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
774 | * | |
775 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
776 | */ | |
777 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
778 | ||
3c72234c IM |
779 | /** |
780 | * cpu_create: | |
781 | * @typename: The CPU type. | |
782 | * | |
783 | * Instantiates a CPU and realizes the CPU. | |
784 | * | |
785 | * Returns: A #CPUState or %NULL if an error occurred. | |
786 | */ | |
787 | CPUState *cpu_create(const char *typename); | |
788 | ||
789 | /** | |
c1c8cfe5 EH |
790 | * parse_cpu_option: |
791 | * @cpu_option: The -cpu option including optional parameters. | |
3c72234c IM |
792 | * |
793 | * processes optional parameters and registers them as global properties | |
794 | * | |
4482e05c IM |
795 | * Returns: type of CPU to create or prints error and terminates process |
796 | * if an error occurred. | |
3c72234c | 797 | */ |
c1c8cfe5 | 798 | const char *parse_cpu_option(const char *cpu_option); |
9262685b | 799 | |
3993c6bd | 800 | /** |
8c2e1b00 | 801 | * cpu_has_work: |
3993c6bd AF |
802 | * @cpu: The vCPU to check. |
803 | * | |
804 | * Checks whether the CPU has work to do. | |
805 | * | |
806 | * Returns: %true if the CPU has work, %false otherwise. | |
807 | */ | |
8c2e1b00 AF |
808 | static inline bool cpu_has_work(CPUState *cpu) |
809 | { | |
810 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
811 | ||
812 | g_assert(cc->has_work); | |
813 | return cc->has_work(cpu); | |
814 | } | |
3993c6bd | 815 | |
60e82579 AF |
816 | /** |
817 | * qemu_cpu_is_self: | |
818 | * @cpu: The vCPU to check against. | |
819 | * | |
820 | * Checks whether the caller is executing on the vCPU thread. | |
821 | * | |
822 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
823 | */ | |
824 | bool qemu_cpu_is_self(CPUState *cpu); | |
825 | ||
c08d7424 AF |
826 | /** |
827 | * qemu_cpu_kick: | |
828 | * @cpu: The vCPU to kick. | |
829 | * | |
830 | * Kicks @cpu's thread. | |
831 | */ | |
832 | void qemu_cpu_kick(CPUState *cpu); | |
833 | ||
2fa45344 AF |
834 | /** |
835 | * cpu_is_stopped: | |
836 | * @cpu: The CPU to check. | |
837 | * | |
838 | * Checks whether the CPU is stopped. | |
839 | * | |
840 | * Returns: %true if run state is not running or if artificially stopped; | |
841 | * %false otherwise. | |
842 | */ | |
843 | bool cpu_is_stopped(CPUState *cpu); | |
844 | ||
d148d90e SF |
845 | /** |
846 | * do_run_on_cpu: | |
847 | * @cpu: The vCPU to run on. | |
848 | * @func: The function to be executed. | |
849 | * @data: Data to pass to the function. | |
850 | * @mutex: Mutex to release while waiting for @func to run. | |
851 | * | |
852 | * Used internally in the implementation of run_on_cpu. | |
853 | */ | |
14e6fe12 | 854 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
855 | QemuMutex *mutex); |
856 | ||
f100f0b3 AF |
857 | /** |
858 | * run_on_cpu: | |
859 | * @cpu: The vCPU to run on. | |
860 | * @func: The function to be executed. | |
861 | * @data: Data to pass to the function. | |
862 | * | |
863 | * Schedules the function @func for execution on the vCPU @cpu. | |
864 | */ | |
14e6fe12 | 865 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 866 | |
3c02270d CV |
867 | /** |
868 | * async_run_on_cpu: | |
869 | * @cpu: The vCPU to run on. | |
870 | * @func: The function to be executed. | |
871 | * @data: Data to pass to the function. | |
872 | * | |
873 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
874 | */ | |
14e6fe12 | 875 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 876 | |
53f5ed95 PB |
877 | /** |
878 | * async_safe_run_on_cpu: | |
879 | * @cpu: The vCPU to run on. | |
880 | * @func: The function to be executed. | |
881 | * @data: Data to pass to the function. | |
882 | * | |
883 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
884 | * while all other vCPUs are sleeping. | |
885 | * | |
886 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
887 | * BQL. | |
888 | */ | |
14e6fe12 | 889 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 890 | |
cfbc3c60 EC |
891 | /** |
892 | * cpu_in_exclusive_context() | |
893 | * @cpu: The vCPU to check | |
894 | * | |
895 | * Returns true if @cpu is an exclusive context, for example running | |
896 | * something which has previously been queued via async_safe_run_on_cpu(). | |
897 | */ | |
898 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) | |
899 | { | |
df8a6880 | 900 | return cpu->exclusive_context_count; |
cfbc3c60 EC |
901 | } |
902 | ||
38d8f5c8 AF |
903 | /** |
904 | * qemu_get_cpu: | |
905 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
906 | * | |
907 | * Gets a CPU matching @index. | |
908 | * | |
909 | * Returns: The CPU or %NULL if there is no matching CPU. | |
910 | */ | |
911 | CPUState *qemu_get_cpu(int index); | |
912 | ||
69e5ff06 IM |
913 | /** |
914 | * cpu_exists: | |
915 | * @id: Guest-exposed CPU ID to lookup. | |
916 | * | |
917 | * Search for CPU with specified ID. | |
918 | * | |
919 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
920 | */ | |
921 | bool cpu_exists(int64_t id); | |
922 | ||
5ce46cb3 EH |
923 | /** |
924 | * cpu_by_arch_id: | |
925 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
926 | * | |
927 | * Get a CPU with matching @id. | |
928 | * | |
929 | * Returns: The CPU or %NULL if there is no matching CPU. | |
930 | */ | |
931 | CPUState *cpu_by_arch_id(int64_t id); | |
932 | ||
c3affe56 AF |
933 | /** |
934 | * cpu_interrupt: | |
935 | * @cpu: The CPU to set an interrupt on. | |
7e63bc38 | 936 | * @mask: The interrupts to set. |
c3affe56 AF |
937 | * |
938 | * Invokes the interrupt handler. | |
939 | */ | |
c3affe56 AF |
940 | |
941 | void cpu_interrupt(CPUState *cpu, int mask); | |
942 | ||
2991b890 PC |
943 | /** |
944 | * cpu_set_pc: | |
945 | * @cpu: The CPU to set the program counter for. | |
946 | * @addr: Program counter value. | |
947 | * | |
948 | * Sets the program counter for a CPU. | |
949 | */ | |
950 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
951 | { | |
952 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
953 | ||
954 | cc->set_pc(cpu, addr); | |
955 | } | |
956 | ||
d8ed887b AF |
957 | /** |
958 | * cpu_reset_interrupt: | |
959 | * @cpu: The CPU to clear the interrupt on. | |
960 | * @mask: The interrupt mask to clear. | |
961 | * | |
962 | * Resets interrupts on the vCPU @cpu. | |
963 | */ | |
964 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
965 | ||
60a3e17a AF |
966 | /** |
967 | * cpu_exit: | |
968 | * @cpu: The CPU to exit. | |
969 | * | |
970 | * Requests the CPU @cpu to exit execution. | |
971 | */ | |
972 | void cpu_exit(CPUState *cpu); | |
973 | ||
2993683b IM |
974 | /** |
975 | * cpu_resume: | |
976 | * @cpu: The CPU to resume. | |
977 | * | |
978 | * Resumes CPU, i.e. puts CPU into runnable state. | |
979 | */ | |
980 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 981 | |
4c055ab5 | 982 | /** |
2c579042 BR |
983 | * cpu_remove_sync: |
984 | * @cpu: The CPU to remove. | |
985 | * | |
986 | * Requests the CPU to be removed and waits till it is removed. | |
987 | */ | |
988 | void cpu_remove_sync(CPUState *cpu); | |
989 | ||
d148d90e SF |
990 | /** |
991 | * process_queued_cpu_work() - process all items on CPU work queue | |
992 | * @cpu: The CPU which work queue to process. | |
993 | */ | |
994 | void process_queued_cpu_work(CPUState *cpu); | |
995 | ||
ab129972 PB |
996 | /** |
997 | * cpu_exec_start: | |
998 | * @cpu: The CPU for the current thread. | |
999 | * | |
1000 | * Record that a CPU has started execution and can be interrupted with | |
1001 | * cpu_exit. | |
1002 | */ | |
1003 | void cpu_exec_start(CPUState *cpu); | |
1004 | ||
1005 | /** | |
1006 | * cpu_exec_end: | |
1007 | * @cpu: The CPU for the current thread. | |
1008 | * | |
1009 | * Record that a CPU has stopped execution and exclusive sections | |
1010 | * can be executed without interrupting it. | |
1011 | */ | |
1012 | void cpu_exec_end(CPUState *cpu); | |
1013 | ||
1014 | /** | |
1015 | * start_exclusive: | |
1016 | * | |
1017 | * Wait for a concurrent exclusive section to end, and then start | |
1018 | * a section of work that is run while other CPUs are not running | |
1019 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
1020 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
1021 | * during the exclusive section go to sleep until this CPU calls | |
1022 | * end_exclusive. | |
ab129972 PB |
1023 | */ |
1024 | void start_exclusive(void); | |
1025 | ||
1026 | /** | |
1027 | * end_exclusive: | |
1028 | * | |
1029 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
1030 | */ |
1031 | void end_exclusive(void); | |
1032 | ||
c643bed9 AF |
1033 | /** |
1034 | * qemu_init_vcpu: | |
1035 | * @cpu: The vCPU to initialize. | |
1036 | * | |
1037 | * Initializes a vCPU. | |
1038 | */ | |
1039 | void qemu_init_vcpu(CPUState *cpu); | |
1040 | ||
3825b28f AF |
1041 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
1042 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
1043 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
1044 | ||
1045 | /** | |
1046 | * cpu_single_step: | |
1047 | * @cpu: CPU to the flags for. | |
1048 | * @enabled: Flags to enable. | |
1049 | * | |
1050 | * Enables or disables single-stepping for @cpu. | |
1051 | */ | |
1052 | void cpu_single_step(CPUState *cpu, int enabled); | |
1053 | ||
b3310ab3 AF |
1054 | /* Breakpoint/watchpoint flags */ |
1055 | #define BP_MEM_READ 0x01 | |
1056 | #define BP_MEM_WRITE 0x02 | |
1057 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
1058 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 1059 | /* 0x08 currently unused */ |
b3310ab3 AF |
1060 | #define BP_GDB 0x10 |
1061 | #define BP_CPU 0x20 | |
b933066a | 1062 | #define BP_ANY (BP_GDB | BP_CPU) |
019a9808 RH |
1063 | #define BP_HIT_SHIFT 6 |
1064 | #define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) | |
1065 | #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) | |
1066 | #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) | |
b3310ab3 AF |
1067 | |
1068 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
1069 | CPUBreakpoint **breakpoint); | |
1070 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
1071 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
1072 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
1073 | ||
b933066a RH |
1074 | /* Return true if PC matches an installed breakpoint. */ |
1075 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
1076 | { | |
1077 | CPUBreakpoint *bp; | |
1078 | ||
1079 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
1080 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
1081 | if (bp->pc == pc && (bp->flags & mask)) { | |
1082 | return true; | |
1083 | } | |
1084 | } | |
1085 | } | |
1086 | return false; | |
1087 | } | |
1088 | ||
87e303de | 1089 | #if defined(CONFIG_USER_ONLY) |
74841f04 RH |
1090 | static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
1091 | int flags, CPUWatchpoint **watchpoint) | |
1092 | { | |
1093 | return -ENOSYS; | |
1094 | } | |
1095 | ||
1096 | static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
1097 | vaddr len, int flags) | |
1098 | { | |
1099 | return -ENOSYS; | |
1100 | } | |
1101 | ||
1102 | static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, | |
1103 | CPUWatchpoint *wp) | |
1104 | { | |
1105 | } | |
1106 | ||
1107 | static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
1108 | { | |
1109 | } | |
1110 | #else | |
75a34036 AF |
1111 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
1112 | int flags, CPUWatchpoint **watchpoint); | |
1113 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
1114 | vaddr len, int flags); | |
1115 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
1116 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
74841f04 | 1117 | #endif |
75a34036 | 1118 | |
6d03226b AB |
1119 | /** |
1120 | * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? | |
1121 | * @cs: CPUState pointer | |
1122 | * | |
1123 | * The memory callbacks are installed if a plugin has instrumented an | |
1124 | * instruction for memory. This can be useful to know if you want to | |
1125 | * force a slow path for a series of memory accesses. | |
1126 | */ | |
1127 | static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) | |
1128 | { | |
1129 | #ifdef CONFIG_PLUGIN | |
1130 | return !!cpu->plugin_mem_cbs; | |
1131 | #else | |
1132 | return false; | |
1133 | #endif | |
1134 | } | |
1135 | ||
63c91552 PB |
1136 | /** |
1137 | * cpu_get_address_space: | |
1138 | * @cpu: CPU to get address space from | |
1139 | * @asidx: index identifying which address space to get | |
1140 | * | |
1141 | * Return the requested address space of this CPU. @asidx | |
1142 | * specifies which address space to read. | |
1143 | */ | |
1144 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
1145 | ||
8905770b | 1146 | G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) |
9edc6313 | 1147 | G_GNUC_PRINTF(2, 3); |
7df5e3d6 CF |
1148 | |
1149 | /* $(top_srcdir)/cpu.c */ | |
995b87de | 1150 | void cpu_class_init_props(DeviceClass *dc); |
39e329e3 | 1151 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 1152 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 1153 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1154 | |
c95ac103 TH |
1155 | /** |
1156 | * target_words_bigendian: | |
1157 | * Returns true if the (default) endianness of the target is big endian, | |
1158 | * false otherwise. Note that in target-specific code, you can use | |
ee3eb3a7 | 1159 | * TARGET_BIG_ENDIAN directly instead. On the other hand, common |
c95ac103 TH |
1160 | * code should normally never need to know about the endianness of the |
1161 | * target, so please do *not* use this function unless you know very well | |
1162 | * what you are doing! | |
1163 | */ | |
1164 | bool target_words_bigendian(void); | |
1165 | ||
1077f50b TH |
1166 | const char *target_name(void); |
1167 | ||
4e40e893 MAL |
1168 | void page_size_init(void); |
1169 | ||
47507383 TH |
1170 | #ifdef NEED_CPU_H |
1171 | ||
75fe97b4 | 1172 | #ifndef CONFIG_USER_ONLY |
feece4d0 | 1173 | |
8a9358cc | 1174 | extern const VMStateDescription vmstate_cpu_common; |
1a1562f5 AF |
1175 | |
1176 | #define VMSTATE_CPU() { \ | |
1177 | .name = "parent_obj", \ | |
1178 | .size = sizeof(CPUState), \ | |
1179 | .vmsd = &vmstate_cpu_common, \ | |
1180 | .flags = VMS_STRUCT, \ | |
1181 | .offset = 0, \ | |
1182 | } | |
75fe97b4 | 1183 | #endif /* !CONFIG_USER_ONLY */ |
1a1562f5 | 1184 | |
47507383 TH |
1185 | #endif /* NEED_CPU_H */ |
1186 | ||
a07f953e | 1187 | #define UNASSIGNED_CPU_INDEX -1 |
7ea7b9ad | 1188 | #define UNASSIGNED_CLUSTER_INDEX -1 |
a07f953e | 1189 | |
dd83b06a | 1190 | #endif |