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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
3979fca4 | 24 | #include "disas/dis-asm.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
66b9b43c | 26 | #include "exec/memattrs.h" |
9af23989 | 27 | #include "qapi/qapi-types-run-state.h" |
48151859 | 28 | #include "qemu/bitmap.h" |
068a5ea0 | 29 | #include "qemu/rcu_queue.h" |
bdc44640 | 30 | #include "qemu/queue.h" |
1de7afc9 | 31 | #include "qemu/thread.h" |
54cb65d8 | 32 | #include "qemu/plugin.h" |
db1015e9 | 33 | #include "qom/object.h" |
dd83b06a | 34 | |
b5ba1cc6 QN |
35 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
36 | void *opaque); | |
c72bf468 | 37 | |
577f42c0 AF |
38 | /** |
39 | * vaddr: | |
40 | * Type wide enough to contain any #target_ulong virtual address. | |
41 | */ | |
42 | typedef uint64_t vaddr; | |
43 | #define VADDR_PRId PRId64 | |
44 | #define VADDR_PRIu PRIu64 | |
45 | #define VADDR_PRIo PRIo64 | |
46 | #define VADDR_PRIx PRIx64 | |
47 | #define VADDR_PRIX PRIX64 | |
48 | #define VADDR_MAX UINT64_MAX | |
49 | ||
dd83b06a AF |
50 | /** |
51 | * SECTION:cpu | |
52 | * @section_id: QEMU-cpu | |
53 | * @title: CPU Class | |
54 | * @short_description: Base class for all CPUs | |
55 | */ | |
56 | ||
57 | #define TYPE_CPU "cpu" | |
58 | ||
0d6d1ab4 AF |
59 | /* Since this macro is used a lot in hot code paths and in conjunction with |
60 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
61 | * an unchecked cast. | |
62 | */ | |
63 | #define CPU(obj) ((CPUState *)(obj)) | |
64 | ||
db1015e9 | 65 | typedef struct CPUClass CPUClass; |
8110fa1d EH |
66 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, |
67 | TYPE_CPU) | |
dd83b06a | 68 | |
b35399bb SS |
69 | typedef enum MMUAccessType { |
70 | MMU_DATA_LOAD = 0, | |
71 | MMU_DATA_STORE = 1, | |
72 | MMU_INST_FETCH = 2 | |
73 | } MMUAccessType; | |
74 | ||
568496c0 | 75 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 76 | |
bdf7ae5b AF |
77 | struct TranslationBlock; |
78 | ||
dd83b06a AF |
79 | /** |
80 | * CPUClass: | |
2b8c2754 AF |
81 | * @class_by_name: Callback to map -cpu command line model name to an |
82 | * instantiatable CPU type. | |
94a444b2 | 83 | * @parse_features: Callback to parse command line arguments. |
91b1df8c | 84 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 85 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 86 | * @do_interrupt: Callback for interrupt handling. |
93e22326 | 87 | * @do_unaligned_access: Callback for unaligned access handling, if |
52bf9771 | 88 | * the target defines #TARGET_ALIGNED_ONLY. |
0dff0939 PM |
89 | * @do_transaction_failed: Callback for handling failed memory transactions |
90 | * (ie bus faults or external aborts; not MMU faults) | |
c08295d4 PM |
91 | * @virtio_is_big_endian: Callback to return %true if a CPU which supports |
92 | * runtime configurable endianness is currently big-endian. Non-configurable | |
93 | * CPUs can use the default implementation of this method. This method should | |
94 | * not be used by any callers other than the pre-1.0 virtio devices. | |
f3659eee | 95 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
96 | * @dump_state: Callback for dumping state. |
97 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 98 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 99 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 100 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
42f6ed91 JS |
101 | * @set_pc: Callback for setting the Program Counter register. This |
102 | * should have the semantics used by the target architecture when | |
103 | * setting the PC from a source such as an ELF file entry point; | |
104 | * for example on Arm it will also set the Thumb mode bit based | |
105 | * on the least significant bit of the new PC value. | |
106 | * If the target behaviour here is anything other than "set | |
107 | * the PC register to the value passed in" then the target must | |
108 | * also implement the synchronize_from_tb hook. | |
bdf7ae5b | 109 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
42f6ed91 JS |
110 | * #TranslationBlock. This is called when we abandon execution |
111 | * of a TB before starting it, and must set all parts of the CPU | |
112 | * state which the previous TB in the chain may not have updated. | |
113 | * This always includes at least the program counter; some targets | |
114 | * will need to do more. If this hook is not implemented then the | |
115 | * default is to call @set_pc(tb->pc). | |
da6bbf85 RH |
116 | * @tlb_fill: Callback for handling a softmmu tlb miss or user-only |
117 | * address fault. For system mode, if the access is valid, call | |
118 | * tlb_set_page and return true; if the access is invalid, and | |
119 | * probe is true, return false; otherwise raise an exception and | |
120 | * do not return. For user-only mode, always raise an exception | |
121 | * and do not return. | |
00b941e5 | 122 | * @get_phys_page_debug: Callback for obtaining a physical address. |
1dc6fb1f PM |
123 | * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the |
124 | * associated memory transaction attributes to use for the access. | |
125 | * CPUs which use memory transaction attributes should implement this | |
126 | * instead of get_phys_page_debug. | |
d7f25a9e PM |
127 | * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for |
128 | * a memory access with the specified memory transaction attributes. | |
5b50e790 AF |
129 | * @gdb_read_register: Callback for letting GDB read a register. |
130 | * @gdb_write_register: Callback for letting GDB write a register. | |
568496c0 SF |
131 | * @debug_check_watchpoint: Callback: return true if the architectural |
132 | * watchpoint whose address has matched should really fire. | |
86025ee4 | 133 | * @debug_excp_handler: Callback for handling debug exceptions. |
c08295d4 PM |
134 | * @write_elf64_note: Callback for writing a CPU-specific ELF note to a |
135 | * 64-bit VM coredump. | |
136 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
137 | * note to a 32-bit VM coredump. | |
138 | * @write_elf32_note: Callback for writing a CPU-specific ELF note to a | |
139 | * 32-bit VM coredump. | |
140 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
141 | * note to a 32-bit VM coredump. | |
b170fce3 | 142 | * @vmsd: State description for migration. |
a0e372f0 | 143 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 144 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
145 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
146 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
147 | * @gdb_arch_name: Optional callback that returns the architecture name known |
148 | * to GDB. The caller must free the returned string with g_free. | |
200bf5b7 AB |
149 | * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the |
150 | * gdb stub. Returns a pointer to the XML contents for the specified XML file | |
151 | * or NULL if the CPU doesn't have a dynamically generated content for it. | |
cffe7b32 RH |
152 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
153 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
9585db68 | 154 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. |
37b9de46 | 155 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
156 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
157 | * address before attempting to match it against watchpoints. | |
61ad65d0 RH |
158 | * @deprecation_note: If this CPUClass is deprecated, this field provides |
159 | * related information. | |
dd83b06a AF |
160 | * |
161 | * Represents a CPU family or model. | |
162 | */ | |
db1015e9 | 163 | struct CPUClass { |
dd83b06a | 164 | /*< private >*/ |
961f8395 | 165 | DeviceClass parent_class; |
dd83b06a AF |
166 | /*< public >*/ |
167 | ||
2b8c2754 | 168 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 169 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 170 | |
91b1df8c | 171 | int reset_dump_flags; |
8c2e1b00 | 172 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 173 | void (*do_interrupt)(CPUState *cpu); |
93e22326 | 174 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
b35399bb SS |
175 | MMUAccessType access_type, |
176 | int mmu_idx, uintptr_t retaddr); | |
0dff0939 PM |
177 | void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, |
178 | unsigned size, MMUAccessType access_type, | |
179 | int mmu_idx, MemTxAttrs attrs, | |
180 | MemTxResult response, uintptr_t retaddr); | |
bf7663c4 | 181 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
182 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
183 | uint8_t *buf, int len, bool is_write); | |
90c84c56 | 184 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
c86f106b | 185 | GuestPanicInformation* (*get_crash_info)(CPUState *cpu); |
11cb6c15 | 186 | void (*dump_statistics)(CPUState *cpu, int flags); |
997395d3 | 187 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 188 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
189 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
190 | Error **errp); | |
f45748f1 | 191 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 192 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
da6bbf85 RH |
193 | bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, |
194 | MMUAccessType access_type, int mmu_idx, | |
195 | bool probe, uintptr_t retaddr); | |
00b941e5 | 196 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
1dc6fb1f PM |
197 | hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, |
198 | MemTxAttrs *attrs); | |
d7f25a9e | 199 | int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); |
a010bdbe | 200 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
5b50e790 | 201 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
568496c0 | 202 | bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); |
86025ee4 | 203 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 204 | |
c72bf468 JF |
205 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
206 | int cpuid, void *opaque); | |
207 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
208 | void *opaque); | |
209 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
210 | int cpuid, void *opaque); | |
211 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
212 | void *opaque); | |
a0e372f0 | 213 | |
8a9358cc | 214 | const VMStateDescription *vmsd; |
5b24c641 | 215 | const char *gdb_core_xml_file; |
b3820e6c | 216 | gchar * (*gdb_arch_name)(CPUState *cpu); |
200bf5b7 | 217 | const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); |
cffe7b32 RH |
218 | void (*cpu_exec_enter)(CPUState *cpu); |
219 | void (*cpu_exec_exit)(CPUState *cpu); | |
9585db68 | 220 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); |
37b9de46 PC |
221 | |
222 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
40612000 | 223 | vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); |
55c3ceef RH |
224 | void (*tcg_initialize)(void); |
225 | ||
61ad65d0 | 226 | const char *deprecation_note; |
55c3ceef RH |
227 | /* Keep non-pointer data at the end to minimize holes. */ |
228 | int gdb_num_core_regs; | |
229 | bool gdb_stop_before_watchpoint; | |
db1015e9 | 230 | }; |
dd83b06a | 231 | |
5e140196 RH |
232 | /* |
233 | * Low 16 bits: number of cycles left, used only in icount mode. | |
234 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs | |
235 | * for this CPU and return to its top level loop (even in non-icount mode). | |
236 | * This allows a single read-compare-cbranch-write sequence to test | |
237 | * for both decrementer underflow and exceptions. | |
238 | */ | |
239 | typedef union IcountDecr { | |
240 | uint32_t u32; | |
241 | struct { | |
28ecfd7a | 242 | #ifdef HOST_WORDS_BIGENDIAN |
5e140196 RH |
243 | uint16_t high; |
244 | uint16_t low; | |
28ecfd7a | 245 | #else |
5e140196 RH |
246 | uint16_t low; |
247 | uint16_t high; | |
28ecfd7a | 248 | #endif |
5e140196 RH |
249 | } u16; |
250 | } IcountDecr; | |
28ecfd7a | 251 | |
f0c3c505 AF |
252 | typedef struct CPUBreakpoint { |
253 | vaddr pc; | |
254 | int flags; /* BP_* */ | |
255 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
256 | } CPUBreakpoint; | |
257 | ||
568496c0 | 258 | struct CPUWatchpoint { |
ff4700b0 | 259 | vaddr vaddr; |
05068c0d | 260 | vaddr len; |
08225676 | 261 | vaddr hitaddr; |
66b9b43c | 262 | MemTxAttrs hitattrs; |
ff4700b0 AF |
263 | int flags; /* BP_* */ |
264 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 265 | }; |
ff4700b0 | 266 | |
2f3a57ee AB |
267 | #ifdef CONFIG_PLUGIN |
268 | /* | |
269 | * For plugins we sometime need to save the resolved iotlb data before | |
270 | * the memory regions get moved around by io_writex. | |
271 | */ | |
272 | typedef struct SavedIOTLB { | |
273 | hwaddr addr; | |
274 | MemoryRegionSection *section; | |
275 | hwaddr mr_offset; | |
276 | } SavedIOTLB; | |
277 | #endif | |
278 | ||
a60f24b5 | 279 | struct KVMState; |
f7575c96 | 280 | struct kvm_run; |
a60f24b5 | 281 | |
b0cb0a66 VP |
282 | struct hax_vcpu_state; |
283 | ||
8cd70437 AF |
284 | #define TB_JMP_CACHE_BITS 12 |
285 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
286 | ||
4b4629d9 | 287 | /* work queue */ |
14e6fe12 PB |
288 | |
289 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
290 | * hosts in a single parameter | |
291 | */ | |
292 | typedef union { | |
293 | int host_int; | |
294 | unsigned long host_ulong; | |
295 | void *host_ptr; | |
296 | vaddr target_ptr; | |
297 | } run_on_cpu_data; | |
298 | ||
299 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
300 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
301 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
302 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
303 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
304 | ||
305 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
306 | ||
d148d90e | 307 | struct qemu_work_item; |
4b4629d9 | 308 | |
0b8497f0 | 309 | #define CPU_UNSET_NUMA_NODE_ID -1 |
d01c05c9 | 310 | #define CPU_TRACE_DSTATE_MAX_EVENTS 32 |
0b8497f0 | 311 | |
dd83b06a AF |
312 | /** |
313 | * CPUState: | |
55e5c285 | 314 | * @cpu_index: CPU index (informative). |
7ea7b9ad PM |
315 | * @cluster_index: Identifies which cluster this CPU is in. |
316 | * For boards which don't define clusters or for "loose" CPUs not assigned | |
317 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will | |
318 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER | |
319 | * QOM parent. | |
ce3960eb AF |
320 | * @nr_cores: Number of cores within this CPU package. |
321 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
322 | * @running: #true if CPU is currently running (lockless). |
323 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 324 | * valid under cpu_list_lock. |
61a46217 | 325 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
326 | * @interrupt_request: Indicates a pending interrupt request. |
327 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 328 | * @stop: Indicates a pending stop request. |
f324e766 | 329 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 330 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 331 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 332 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 333 | * @icount_extra: Instructions until next timer event. |
414b15c9 PB |
334 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
335 | * requires that IO only be performed on the last instruction of a TB | |
336 | * so that interrupts take effect immediately. | |
32857f4d PM |
337 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
338 | * AddressSpaces this CPU has) | |
12ebc9a7 | 339 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
340 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
341 | * only have a single AddressSpace | |
c05efcb1 | 342 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
5e140196 | 343 | * @icount_decr_ptr: Pointer to IcountDecr field within subclass. |
eac8b355 | 344 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 345 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 346 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 347 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 348 | * @opaque: User data. |
93afeade | 349 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
8737c51c | 350 | * @kvm_fd: vCPU file descriptor for KVM. |
0c0fcc20 EC |
351 | * @work_mutex: Lock to prevent multiple access to @work_list. |
352 | * @work_list: List of pending asynchronous work. | |
d4381116 LV |
353 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
354 | * to @trace_dstate). | |
48151859 | 355 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
54cb65d8 | 356 | * @plugin_mask: Plugin event bitmap. Modified only via async work. |
ed860129 PM |
357 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
358 | * flag of the same name: allows the board to suppress calling of the | |
359 | * CPU do_transaction_failed hook function. | |
dd83b06a AF |
360 | * |
361 | * State of one CPU core or thread. | |
362 | */ | |
363 | struct CPUState { | |
364 | /*< private >*/ | |
961f8395 | 365 | DeviceState parent_obj; |
dd83b06a AF |
366 | /*< public >*/ |
367 | ||
ce3960eb AF |
368 | int nr_cores; |
369 | int nr_threads; | |
370 | ||
814e612e | 371 | struct QemuThread *thread; |
bcba2a72 AF |
372 | #ifdef _WIN32 |
373 | HANDLE hThread; | |
374 | #endif | |
9f09e18a | 375 | int thread_id; |
c265e976 | 376 | bool running, has_waiter; |
f5c121b8 | 377 | struct QemuCond *halt_cond; |
216fc9a4 | 378 | bool thread_kicked; |
61a46217 | 379 | bool created; |
4fdeee7c | 380 | bool stop; |
f324e766 | 381 | bool stopped; |
c1b70158 TJB |
382 | |
383 | /* Should CPU start in powered-off state? */ | |
384 | bool start_powered_off; | |
385 | ||
4c055ab5 | 386 | bool unplug; |
bac05aa9 | 387 | bool crash_occurred; |
e0c38211 | 388 | bool exit_request; |
cfbc3c60 | 389 | bool in_exclusive_context; |
9b990ee5 | 390 | uint32_t cflags_next_tb; |
8d04fb55 | 391 | /* updates protected by BQL */ |
259186a7 | 392 | uint32_t interrupt_request; |
ed2803da | 393 | int singlestep_enabled; |
e4cd9657 | 394 | int64_t icount_budget; |
efee7340 | 395 | int64_t icount_extra; |
9c09a251 | 396 | uint64_t random_seed; |
6f03bef0 | 397 | sigjmp_buf jmp_env; |
bcba2a72 | 398 | |
376692b9 | 399 | QemuMutex work_mutex; |
0c0fcc20 | 400 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
376692b9 | 401 | |
32857f4d | 402 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 403 | int num_ases; |
09daed84 | 404 | AddressSpace *as; |
6731d864 | 405 | MemoryRegion *memory; |
09daed84 | 406 | |
c05efcb1 | 407 | void *env_ptr; /* CPUArchState */ |
5e140196 | 408 | IcountDecr *icount_decr_ptr; |
7d7500d9 | 409 | |
f3ced3c5 | 410 | /* Accessed in parallel; all accesses must be atomic */ |
8cd70437 | 411 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
7d7500d9 | 412 | |
eac8b355 | 413 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 414 | int gdb_num_regs; |
35143f01 | 415 | int gdb_num_g_regs; |
bdc44640 | 416 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 417 | |
f0c3c505 | 418 | /* ice debug support */ |
b58deb34 | 419 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
f0c3c505 | 420 | |
b58deb34 | 421 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
ff4700b0 AF |
422 | CPUWatchpoint *watchpoint_hit; |
423 | ||
0429a971 AF |
424 | void *opaque; |
425 | ||
93afeade AF |
426 | /* In order to avoid passing too many arguments to the MMIO helpers, |
427 | * we store some rarely used information in the CPU context. | |
428 | */ | |
429 | uintptr_t mem_io_pc; | |
93afeade | 430 | |
8737c51c | 431 | int kvm_fd; |
a60f24b5 | 432 | struct KVMState *kvm_state; |
f7575c96 | 433 | struct kvm_run *kvm_run; |
8737c51c | 434 | |
d01c05c9 | 435 | /* Used for events with 'vcpu' and *without* the 'disabled' properties */ |
d4381116 | 436 | DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); |
d01c05c9 | 437 | DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); |
48151859 | 438 | |
54cb65d8 EC |
439 | DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); |
440 | ||
2f3a57ee | 441 | #ifdef CONFIG_PLUGIN |
54cb65d8 | 442 | GArray *plugin_mem_cbs; |
2f3a57ee AB |
443 | /* saved iotlb data from io_writex */ |
444 | SavedIOTLB saved_iotlb; | |
445 | #endif | |
54cb65d8 | 446 | |
f5df5baf | 447 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e | 448 | int cpu_index; |
7ea7b9ad | 449 | int cluster_index; |
6fda014e | 450 | uint32_t halted; |
99df7dce | 451 | uint32_t can_do_io; |
6fda014e | 452 | int32_t exception_index; |
7e4fb26d | 453 | |
99f31832 SAGDR |
454 | /* shared by kvm, hax and hvf */ |
455 | bool vcpu_dirty; | |
456 | ||
2adcc85d JH |
457 | /* Used to keep track of an outstanding cpu throttle thread for migration |
458 | * autoconverge | |
459 | */ | |
460 | bool throttle_thread_scheduled; | |
461 | ||
ed860129 PM |
462 | bool ignore_memory_transaction_failures; |
463 | ||
b0cb0a66 | 464 | struct hax_vcpu_state *hax_vcpu; |
e3b9ca81 | 465 | |
c97d6d2c | 466 | int hvf_fd; |
1f871c5e PM |
467 | |
468 | /* track IOMMUs whose translations we've cached in the TCG TLB */ | |
469 | GArray *iommu_notifiers; | |
dd83b06a AF |
470 | }; |
471 | ||
f481ee2d PB |
472 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
473 | extern CPUTailQ cpus; | |
474 | ||
068a5ea0 EC |
475 | #define first_cpu QTAILQ_FIRST_RCU(&cpus) |
476 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) | |
477 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) | |
bdc44640 | 478 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
068a5ea0 | 479 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) |
182735ef | 480 | |
f240eb6f | 481 | extern __thread CPUState *current_cpu; |
4917cf44 | 482 | |
f3ced3c5 EC |
483 | static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) |
484 | { | |
485 | unsigned int i; | |
486 | ||
487 | for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { | |
d73415a3 | 488 | qatomic_set(&cpu->tb_jmp_cache[i], NULL); |
f3ced3c5 EC |
489 | } |
490 | } | |
491 | ||
8d4e9146 FK |
492 | /** |
493 | * qemu_tcg_mttcg_enabled: | |
494 | * Check whether we are running MultiThread TCG or not. | |
495 | * | |
496 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
497 | */ | |
498 | extern bool mttcg_enabled; | |
499 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
500 | ||
444d5590 AF |
501 | /** |
502 | * cpu_paging_enabled: | |
503 | * @cpu: The CPU whose state is to be inspected. | |
504 | * | |
505 | * Returns: %true if paging is enabled, %false otherwise. | |
506 | */ | |
507 | bool cpu_paging_enabled(const CPUState *cpu); | |
508 | ||
a23bbfda AF |
509 | /** |
510 | * cpu_get_memory_mapping: | |
511 | * @cpu: The CPU whose memory mappings are to be obtained. | |
512 | * @list: Where to write the memory mappings to. | |
513 | * @errp: Pointer for reporting an #Error. | |
514 | */ | |
515 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
516 | Error **errp); | |
517 | ||
cfe35d48 PMD |
518 | #if !defined(CONFIG_USER_ONLY) |
519 | ||
c72bf468 JF |
520 | /** |
521 | * cpu_write_elf64_note: | |
522 | * @f: pointer to a function that writes memory to a file | |
523 | * @cpu: The CPU whose memory is to be dumped | |
524 | * @cpuid: ID number of the CPU | |
525 | * @opaque: pointer to the CPUState struct | |
526 | */ | |
527 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
528 | int cpuid, void *opaque); | |
529 | ||
530 | /** | |
531 | * cpu_write_elf64_qemunote: | |
532 | * @f: pointer to a function that writes memory to a file | |
533 | * @cpu: The CPU whose memory is to be dumped | |
534 | * @cpuid: ID number of the CPU | |
535 | * @opaque: pointer to the CPUState struct | |
536 | */ | |
537 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
538 | void *opaque); | |
539 | ||
540 | /** | |
541 | * cpu_write_elf32_note: | |
542 | * @f: pointer to a function that writes memory to a file | |
543 | * @cpu: The CPU whose memory is to be dumped | |
544 | * @cpuid: ID number of the CPU | |
545 | * @opaque: pointer to the CPUState struct | |
546 | */ | |
547 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
548 | int cpuid, void *opaque); | |
549 | ||
550 | /** | |
551 | * cpu_write_elf32_qemunote: | |
552 | * @f: pointer to a function that writes memory to a file | |
553 | * @cpu: The CPU whose memory is to be dumped | |
554 | * @cpuid: ID number of the CPU | |
555 | * @opaque: pointer to the CPUState struct | |
556 | */ | |
557 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
558 | void *opaque); | |
dd83b06a | 559 | |
c86f106b AN |
560 | /** |
561 | * cpu_get_crash_info: | |
562 | * @cpu: The CPU to get crash information for | |
563 | * | |
564 | * Gets the previously saved crash information. | |
565 | * Caller is responsible for freeing the data. | |
566 | */ | |
567 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
568 | ||
cfe35d48 PMD |
569 | #endif /* !CONFIG_USER_ONLY */ |
570 | ||
878096ee AF |
571 | /** |
572 | * CPUDumpFlags: | |
573 | * @CPU_DUMP_CODE: | |
574 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
575 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
576 | */ | |
577 | enum CPUDumpFlags { | |
578 | CPU_DUMP_CODE = 0x00010000, | |
579 | CPU_DUMP_FPU = 0x00020000, | |
580 | CPU_DUMP_CCOP = 0x00040000, | |
581 | }; | |
582 | ||
583 | /** | |
584 | * cpu_dump_state: | |
585 | * @cpu: The CPU whose state is to be dumped. | |
90c84c56 | 586 | * @f: If non-null, dump to this stream, else to current print sink. |
878096ee AF |
587 | * |
588 | * Dumps CPU state. | |
589 | */ | |
90c84c56 | 590 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
878096ee AF |
591 | |
592 | /** | |
593 | * cpu_dump_statistics: | |
594 | * @cpu: The CPU whose state is to be dumped. | |
878096ee AF |
595 | * @flags: Flags what to dump. |
596 | * | |
11cb6c15 MA |
597 | * Dump CPU statistics to the current monitor if we have one, else to |
598 | * stdout. | |
878096ee | 599 | */ |
11cb6c15 | 600 | void cpu_dump_statistics(CPUState *cpu, int flags); |
878096ee | 601 | |
00b941e5 | 602 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
603 | /** |
604 | * cpu_get_phys_page_attrs_debug: | |
605 | * @cpu: The CPU to obtain the physical page address for. | |
606 | * @addr: The virtual address. | |
607 | * @attrs: Updated on return with the memory transaction attributes to use | |
608 | * for this access. | |
609 | * | |
610 | * Obtains the physical page corresponding to a virtual one, together | |
611 | * with the corresponding memory transaction attributes to use for the access. | |
612 | * Use it only for debugging because no protection checks are done. | |
613 | * | |
614 | * Returns: Corresponding physical page address or -1 if no page found. | |
615 | */ | |
616 | static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
617 | MemTxAttrs *attrs) | |
618 | { | |
619 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
620 | ||
621 | if (cc->get_phys_page_attrs_debug) { | |
622 | return cc->get_phys_page_attrs_debug(cpu, addr, attrs); | |
623 | } | |
624 | /* Fallback for CPUs which don't implement the _attrs_ hook */ | |
625 | *attrs = MEMTXATTRS_UNSPECIFIED; | |
626 | return cc->get_phys_page_debug(cpu, addr); | |
627 | } | |
628 | ||
00b941e5 AF |
629 | /** |
630 | * cpu_get_phys_page_debug: | |
631 | * @cpu: The CPU to obtain the physical page address for. | |
632 | * @addr: The virtual address. | |
633 | * | |
634 | * Obtains the physical page corresponding to a virtual one. | |
635 | * Use it only for debugging because no protection checks are done. | |
636 | * | |
637 | * Returns: Corresponding physical page address or -1 if no page found. | |
638 | */ | |
639 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
640 | { | |
1dc6fb1f | 641 | MemTxAttrs attrs = {}; |
00b941e5 | 642 | |
1dc6fb1f | 643 | return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); |
00b941e5 | 644 | } |
d7f25a9e PM |
645 | |
646 | /** cpu_asidx_from_attrs: | |
647 | * @cpu: CPU | |
648 | * @attrs: memory transaction attributes | |
649 | * | |
650 | * Returns the address space index specifying the CPU AddressSpace | |
651 | * to use for a memory access with the given transaction attributes. | |
652 | */ | |
653 | static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) | |
654 | { | |
655 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
9c8c334b | 656 | int ret = 0; |
d7f25a9e PM |
657 | |
658 | if (cc->asidx_from_attrs) { | |
9c8c334b RH |
659 | ret = cc->asidx_from_attrs(cpu, attrs); |
660 | assert(ret < cpu->num_ases && ret >= 0); | |
d7f25a9e | 661 | } |
9c8c334b | 662 | return ret; |
d7f25a9e | 663 | } |
cfe35d48 PMD |
664 | |
665 | #endif /* CONFIG_USER_ONLY */ | |
00b941e5 | 666 | |
267f685b PB |
667 | /** |
668 | * cpu_list_add: | |
669 | * @cpu: The CPU to be added to the list of CPUs. | |
670 | */ | |
671 | void cpu_list_add(CPUState *cpu); | |
672 | ||
673 | /** | |
674 | * cpu_list_remove: | |
675 | * @cpu: The CPU to be removed from the list of CPUs. | |
676 | */ | |
677 | void cpu_list_remove(CPUState *cpu); | |
678 | ||
dd83b06a AF |
679 | /** |
680 | * cpu_reset: | |
681 | * @cpu: The CPU whose state is to be reset. | |
682 | */ | |
683 | void cpu_reset(CPUState *cpu); | |
684 | ||
2b8c2754 AF |
685 | /** |
686 | * cpu_class_by_name: | |
687 | * @typename: The CPU base type. | |
688 | * @cpu_model: The model string without any parameters. | |
689 | * | |
690 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
691 | * | |
692 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
693 | */ | |
694 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
695 | ||
3c72234c IM |
696 | /** |
697 | * cpu_create: | |
698 | * @typename: The CPU type. | |
699 | * | |
700 | * Instantiates a CPU and realizes the CPU. | |
701 | * | |
702 | * Returns: A #CPUState or %NULL if an error occurred. | |
703 | */ | |
704 | CPUState *cpu_create(const char *typename); | |
705 | ||
706 | /** | |
c1c8cfe5 EH |
707 | * parse_cpu_option: |
708 | * @cpu_option: The -cpu option including optional parameters. | |
3c72234c IM |
709 | * |
710 | * processes optional parameters and registers them as global properties | |
711 | * | |
4482e05c IM |
712 | * Returns: type of CPU to create or prints error and terminates process |
713 | * if an error occurred. | |
3c72234c | 714 | */ |
c1c8cfe5 | 715 | const char *parse_cpu_option(const char *cpu_option); |
9262685b | 716 | |
3993c6bd | 717 | /** |
8c2e1b00 | 718 | * cpu_has_work: |
3993c6bd AF |
719 | * @cpu: The vCPU to check. |
720 | * | |
721 | * Checks whether the CPU has work to do. | |
722 | * | |
723 | * Returns: %true if the CPU has work, %false otherwise. | |
724 | */ | |
8c2e1b00 AF |
725 | static inline bool cpu_has_work(CPUState *cpu) |
726 | { | |
727 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
728 | ||
729 | g_assert(cc->has_work); | |
730 | return cc->has_work(cpu); | |
731 | } | |
3993c6bd | 732 | |
60e82579 AF |
733 | /** |
734 | * qemu_cpu_is_self: | |
735 | * @cpu: The vCPU to check against. | |
736 | * | |
737 | * Checks whether the caller is executing on the vCPU thread. | |
738 | * | |
739 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
740 | */ | |
741 | bool qemu_cpu_is_self(CPUState *cpu); | |
742 | ||
c08d7424 AF |
743 | /** |
744 | * qemu_cpu_kick: | |
745 | * @cpu: The vCPU to kick. | |
746 | * | |
747 | * Kicks @cpu's thread. | |
748 | */ | |
749 | void qemu_cpu_kick(CPUState *cpu); | |
750 | ||
2fa45344 AF |
751 | /** |
752 | * cpu_is_stopped: | |
753 | * @cpu: The CPU to check. | |
754 | * | |
755 | * Checks whether the CPU is stopped. | |
756 | * | |
757 | * Returns: %true if run state is not running or if artificially stopped; | |
758 | * %false otherwise. | |
759 | */ | |
760 | bool cpu_is_stopped(CPUState *cpu); | |
761 | ||
d148d90e SF |
762 | /** |
763 | * do_run_on_cpu: | |
764 | * @cpu: The vCPU to run on. | |
765 | * @func: The function to be executed. | |
766 | * @data: Data to pass to the function. | |
767 | * @mutex: Mutex to release while waiting for @func to run. | |
768 | * | |
769 | * Used internally in the implementation of run_on_cpu. | |
770 | */ | |
14e6fe12 | 771 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
772 | QemuMutex *mutex); |
773 | ||
f100f0b3 AF |
774 | /** |
775 | * run_on_cpu: | |
776 | * @cpu: The vCPU to run on. | |
777 | * @func: The function to be executed. | |
778 | * @data: Data to pass to the function. | |
779 | * | |
780 | * Schedules the function @func for execution on the vCPU @cpu. | |
781 | */ | |
14e6fe12 | 782 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 783 | |
3c02270d CV |
784 | /** |
785 | * async_run_on_cpu: | |
786 | * @cpu: The vCPU to run on. | |
787 | * @func: The function to be executed. | |
788 | * @data: Data to pass to the function. | |
789 | * | |
790 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
791 | */ | |
14e6fe12 | 792 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 793 | |
53f5ed95 PB |
794 | /** |
795 | * async_safe_run_on_cpu: | |
796 | * @cpu: The vCPU to run on. | |
797 | * @func: The function to be executed. | |
798 | * @data: Data to pass to the function. | |
799 | * | |
800 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
801 | * while all other vCPUs are sleeping. | |
802 | * | |
803 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
804 | * BQL. | |
805 | */ | |
14e6fe12 | 806 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 807 | |
cfbc3c60 EC |
808 | /** |
809 | * cpu_in_exclusive_context() | |
810 | * @cpu: The vCPU to check | |
811 | * | |
812 | * Returns true if @cpu is an exclusive context, for example running | |
813 | * something which has previously been queued via async_safe_run_on_cpu(). | |
814 | */ | |
815 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) | |
816 | { | |
817 | return cpu->in_exclusive_context; | |
818 | } | |
819 | ||
38d8f5c8 AF |
820 | /** |
821 | * qemu_get_cpu: | |
822 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
823 | * | |
824 | * Gets a CPU matching @index. | |
825 | * | |
826 | * Returns: The CPU or %NULL if there is no matching CPU. | |
827 | */ | |
828 | CPUState *qemu_get_cpu(int index); | |
829 | ||
69e5ff06 IM |
830 | /** |
831 | * cpu_exists: | |
832 | * @id: Guest-exposed CPU ID to lookup. | |
833 | * | |
834 | * Search for CPU with specified ID. | |
835 | * | |
836 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
837 | */ | |
838 | bool cpu_exists(int64_t id); | |
839 | ||
5ce46cb3 EH |
840 | /** |
841 | * cpu_by_arch_id: | |
842 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
843 | * | |
844 | * Get a CPU with matching @id. | |
845 | * | |
846 | * Returns: The CPU or %NULL if there is no matching CPU. | |
847 | */ | |
848 | CPUState *cpu_by_arch_id(int64_t id); | |
849 | ||
c3affe56 AF |
850 | /** |
851 | * cpu_interrupt: | |
852 | * @cpu: The CPU to set an interrupt on. | |
7e63bc38 | 853 | * @mask: The interrupts to set. |
c3affe56 AF |
854 | * |
855 | * Invokes the interrupt handler. | |
856 | */ | |
c3affe56 AF |
857 | |
858 | void cpu_interrupt(CPUState *cpu, int mask); | |
859 | ||
47507383 TH |
860 | #ifdef NEED_CPU_H |
861 | ||
93e22326 | 862 | #ifdef CONFIG_SOFTMMU |
93e22326 | 863 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
b35399bb SS |
864 | MMUAccessType access_type, |
865 | int mmu_idx, uintptr_t retaddr) | |
93e22326 PB |
866 | { |
867 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
868 | ||
b35399bb | 869 | cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); |
93e22326 | 870 | } |
0dff0939 PM |
871 | |
872 | static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | |
873 | vaddr addr, unsigned size, | |
874 | MMUAccessType access_type, | |
875 | int mmu_idx, MemTxAttrs attrs, | |
876 | MemTxResult response, | |
877 | uintptr_t retaddr) | |
878 | { | |
879 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
880 | ||
ed860129 | 881 | if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { |
0dff0939 PM |
882 | cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, |
883 | mmu_idx, attrs, response, retaddr); | |
884 | } | |
885 | } | |
c658b94f AF |
886 | #endif |
887 | ||
47507383 TH |
888 | #endif /* NEED_CPU_H */ |
889 | ||
2991b890 PC |
890 | /** |
891 | * cpu_set_pc: | |
892 | * @cpu: The CPU to set the program counter for. | |
893 | * @addr: Program counter value. | |
894 | * | |
895 | * Sets the program counter for a CPU. | |
896 | */ | |
897 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
898 | { | |
899 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
900 | ||
901 | cc->set_pc(cpu, addr); | |
902 | } | |
903 | ||
d8ed887b AF |
904 | /** |
905 | * cpu_reset_interrupt: | |
906 | * @cpu: The CPU to clear the interrupt on. | |
907 | * @mask: The interrupt mask to clear. | |
908 | * | |
909 | * Resets interrupts on the vCPU @cpu. | |
910 | */ | |
911 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
912 | ||
60a3e17a AF |
913 | /** |
914 | * cpu_exit: | |
915 | * @cpu: The CPU to exit. | |
916 | * | |
917 | * Requests the CPU @cpu to exit execution. | |
918 | */ | |
919 | void cpu_exit(CPUState *cpu); | |
920 | ||
2993683b IM |
921 | /** |
922 | * cpu_resume: | |
923 | * @cpu: The CPU to resume. | |
924 | * | |
925 | * Resumes CPU, i.e. puts CPU into runnable state. | |
926 | */ | |
927 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 928 | |
4c055ab5 | 929 | /** |
2c579042 BR |
930 | * cpu_remove_sync: |
931 | * @cpu: The CPU to remove. | |
932 | * | |
933 | * Requests the CPU to be removed and waits till it is removed. | |
934 | */ | |
935 | void cpu_remove_sync(CPUState *cpu); | |
936 | ||
d148d90e SF |
937 | /** |
938 | * process_queued_cpu_work() - process all items on CPU work queue | |
939 | * @cpu: The CPU which work queue to process. | |
940 | */ | |
941 | void process_queued_cpu_work(CPUState *cpu); | |
942 | ||
ab129972 PB |
943 | /** |
944 | * cpu_exec_start: | |
945 | * @cpu: The CPU for the current thread. | |
946 | * | |
947 | * Record that a CPU has started execution and can be interrupted with | |
948 | * cpu_exit. | |
949 | */ | |
950 | void cpu_exec_start(CPUState *cpu); | |
951 | ||
952 | /** | |
953 | * cpu_exec_end: | |
954 | * @cpu: The CPU for the current thread. | |
955 | * | |
956 | * Record that a CPU has stopped execution and exclusive sections | |
957 | * can be executed without interrupting it. | |
958 | */ | |
959 | void cpu_exec_end(CPUState *cpu); | |
960 | ||
961 | /** | |
962 | * start_exclusive: | |
963 | * | |
964 | * Wait for a concurrent exclusive section to end, and then start | |
965 | * a section of work that is run while other CPUs are not running | |
966 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
967 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
968 | * during the exclusive section go to sleep until this CPU calls | |
969 | * end_exclusive. | |
ab129972 PB |
970 | */ |
971 | void start_exclusive(void); | |
972 | ||
973 | /** | |
974 | * end_exclusive: | |
975 | * | |
976 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
977 | */ |
978 | void end_exclusive(void); | |
979 | ||
c643bed9 AF |
980 | /** |
981 | * qemu_init_vcpu: | |
982 | * @cpu: The vCPU to initialize. | |
983 | * | |
984 | * Initializes a vCPU. | |
985 | */ | |
986 | void qemu_init_vcpu(CPUState *cpu); | |
987 | ||
3825b28f AF |
988 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
989 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
990 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
991 | ||
992 | /** | |
993 | * cpu_single_step: | |
994 | * @cpu: CPU to the flags for. | |
995 | * @enabled: Flags to enable. | |
996 | * | |
997 | * Enables or disables single-stepping for @cpu. | |
998 | */ | |
999 | void cpu_single_step(CPUState *cpu, int enabled); | |
1000 | ||
b3310ab3 AF |
1001 | /* Breakpoint/watchpoint flags */ |
1002 | #define BP_MEM_READ 0x01 | |
1003 | #define BP_MEM_WRITE 0x02 | |
1004 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
1005 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 1006 | /* 0x08 currently unused */ |
b3310ab3 AF |
1007 | #define BP_GDB 0x10 |
1008 | #define BP_CPU 0x20 | |
b933066a | 1009 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
1010 | #define BP_WATCHPOINT_HIT_READ 0x40 |
1011 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
1012 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
1013 | |
1014 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
1015 | CPUBreakpoint **breakpoint); | |
1016 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
1017 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
1018 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
1019 | ||
b933066a RH |
1020 | /* Return true if PC matches an installed breakpoint. */ |
1021 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
1022 | { | |
1023 | CPUBreakpoint *bp; | |
1024 | ||
1025 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
1026 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
1027 | if (bp->pc == pc && (bp->flags & mask)) { | |
1028 | return true; | |
1029 | } | |
1030 | } | |
1031 | } | |
1032 | return false; | |
1033 | } | |
1034 | ||
74841f04 RH |
1035 | #ifdef CONFIG_USER_ONLY |
1036 | static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
1037 | int flags, CPUWatchpoint **watchpoint) | |
1038 | { | |
1039 | return -ENOSYS; | |
1040 | } | |
1041 | ||
1042 | static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
1043 | vaddr len, int flags) | |
1044 | { | |
1045 | return -ENOSYS; | |
1046 | } | |
1047 | ||
1048 | static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, | |
1049 | CPUWatchpoint *wp) | |
1050 | { | |
1051 | } | |
1052 | ||
1053 | static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
1054 | { | |
1055 | } | |
0026348b DH |
1056 | |
1057 | static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, | |
1058 | MemTxAttrs atr, int fl, uintptr_t ra) | |
1059 | { | |
1060 | } | |
56ad8b00 RH |
1061 | |
1062 | static inline int cpu_watchpoint_address_matches(CPUState *cpu, | |
1063 | vaddr addr, vaddr len) | |
1064 | { | |
1065 | return 0; | |
1066 | } | |
74841f04 | 1067 | #else |
75a34036 AF |
1068 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
1069 | int flags, CPUWatchpoint **watchpoint); | |
1070 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
1071 | vaddr len, int flags); | |
1072 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
1073 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
390734a4 RH |
1074 | |
1075 | /** | |
1076 | * cpu_check_watchpoint: | |
1077 | * @cpu: cpu context | |
1078 | * @addr: guest virtual address | |
1079 | * @len: access length | |
1080 | * @attrs: memory access attributes | |
1081 | * @flags: watchpoint access type | |
1082 | * @ra: unwind return address | |
1083 | * | |
1084 | * Check for a watchpoint hit in [addr, addr+len) of the type | |
1085 | * specified by @flags. Exit via exception with a hit. | |
1086 | */ | |
0026348b DH |
1087 | void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, |
1088 | MemTxAttrs attrs, int flags, uintptr_t ra); | |
390734a4 RH |
1089 | |
1090 | /** | |
1091 | * cpu_watchpoint_address_matches: | |
1092 | * @cpu: cpu context | |
1093 | * @addr: guest virtual address | |
1094 | * @len: access length | |
1095 | * | |
1096 | * Return the watchpoint flags that apply to [addr, addr+len). | |
1097 | * If no watchpoint is registered for the range, the result is 0. | |
1098 | */ | |
56ad8b00 | 1099 | int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); |
74841f04 | 1100 | #endif |
75a34036 | 1101 | |
63c91552 PB |
1102 | /** |
1103 | * cpu_get_address_space: | |
1104 | * @cpu: CPU to get address space from | |
1105 | * @asidx: index identifying which address space to get | |
1106 | * | |
1107 | * Return the requested address space of this CPU. @asidx | |
1108 | * specifies which address space to read. | |
1109 | */ | |
1110 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
1111 | ||
a47dddd7 AF |
1112 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
1113 | GCC_FMT_ATTR(2, 3); | |
c7e002c5 | 1114 | extern Property cpu_common_props[]; |
39e329e3 | 1115 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 1116 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 1117 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1118 | |
c95ac103 TH |
1119 | /** |
1120 | * target_words_bigendian: | |
1121 | * Returns true if the (default) endianness of the target is big endian, | |
1122 | * false otherwise. Note that in target-specific code, you can use | |
1123 | * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common | |
1124 | * code should normally never need to know about the endianness of the | |
1125 | * target, so please do *not* use this function unless you know very well | |
1126 | * what you are doing! | |
1127 | */ | |
1128 | bool target_words_bigendian(void); | |
1129 | ||
47507383 TH |
1130 | #ifdef NEED_CPU_H |
1131 | ||
1a1562f5 | 1132 | #ifdef CONFIG_SOFTMMU |
8a9358cc | 1133 | extern const VMStateDescription vmstate_cpu_common; |
1a1562f5 AF |
1134 | #else |
1135 | #define vmstate_cpu_common vmstate_dummy | |
1136 | #endif | |
1137 | ||
1138 | #define VMSTATE_CPU() { \ | |
1139 | .name = "parent_obj", \ | |
1140 | .size = sizeof(CPUState), \ | |
1141 | .vmsd = &vmstate_cpu_common, \ | |
1142 | .flags = VMS_STRUCT, \ | |
1143 | .offset = 0, \ | |
1144 | } | |
1145 | ||
47507383 TH |
1146 | #endif /* NEED_CPU_H */ |
1147 | ||
a07f953e | 1148 | #define UNASSIGNED_CPU_INDEX -1 |
7ea7b9ad | 1149 | #define UNASSIGNED_CLUSTER_INDEX -1 |
a07f953e | 1150 | |
dd83b06a | 1151 | #endif |