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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
3979fca4 | 24 | #include "disas/dis-asm.h" |
06445fbd | 25 | #include "exec/cpu-common.h" |
c658b94f | 26 | #include "exec/hwaddr.h" |
66b9b43c | 27 | #include "exec/memattrs.h" |
9af23989 | 28 | #include "qapi/qapi-types-run-state.h" |
48151859 | 29 | #include "qemu/bitmap.h" |
068a5ea0 | 30 | #include "qemu/rcu_queue.h" |
bdc44640 | 31 | #include "qemu/queue.h" |
1de7afc9 | 32 | #include "qemu/thread.h" |
aa4cf6eb | 33 | #include "qemu/plugin-event.h" |
db1015e9 | 34 | #include "qom/object.h" |
dd83b06a | 35 | |
b5ba1cc6 QN |
36 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
37 | void *opaque); | |
c72bf468 | 38 | |
dd83b06a AF |
39 | /** |
40 | * SECTION:cpu | |
41 | * @section_id: QEMU-cpu | |
42 | * @title: CPU Class | |
43 | * @short_description: Base class for all CPUs | |
44 | */ | |
45 | ||
46 | #define TYPE_CPU "cpu" | |
47 | ||
0d6d1ab4 AF |
48 | /* Since this macro is used a lot in hot code paths and in conjunction with |
49 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
50 | * an unchecked cast. | |
51 | */ | |
52 | #define CPU(obj) ((CPUState *)(obj)) | |
53 | ||
6fbdff87 AB |
54 | /* |
55 | * The class checkers bring in CPU_GET_CLASS() which is potentially | |
56 | * expensive given the eventual call to | |
57 | * object_class_dynamic_cast_assert(). Because of this the CPUState | |
58 | * has a cached value for the class in cs->cc which is set up in | |
59 | * cpu_exec_realizefn() for use in hot code paths. | |
60 | */ | |
db1015e9 | 61 | typedef struct CPUClass CPUClass; |
8110fa1d EH |
62 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, |
63 | TYPE_CPU) | |
dd83b06a | 64 | |
9295b1aa PMD |
65 | /** |
66 | * OBJECT_DECLARE_CPU_TYPE: | |
67 | * @CpuInstanceType: instance struct name | |
68 | * @CpuClassType: class struct name | |
69 | * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators | |
70 | * | |
71 | * This macro is typically used in "cpu-qom.h" header file, and will: | |
72 | * | |
73 | * - create the typedefs for the CPU object and class structs | |
74 | * - register the type for use with g_autoptr | |
75 | * - provide three standard type cast functions | |
76 | * | |
77 | * The object struct and class struct need to be declared manually. | |
78 | */ | |
79 | #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \ | |
b36e239e PMD |
80 | typedef struct ArchCPU CpuInstanceType; \ |
81 | OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); | |
9295b1aa | 82 | |
b35399bb SS |
83 | typedef enum MMUAccessType { |
84 | MMU_DATA_LOAD = 0, | |
85 | MMU_DATA_STORE = 1, | |
86 | MMU_INST_FETCH = 2 | |
58e8f1f6 | 87 | #define MMU_ACCESS_COUNT 3 |
b35399bb SS |
88 | } MMUAccessType; |
89 | ||
568496c0 | 90 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 91 | |
78271684 CF |
92 | /* see tcg-cpu-ops.h */ |
93 | struct TCGCPUOps; | |
e9e51b71 | 94 | |
fb6916dd CF |
95 | /* see accel-cpu.h */ |
96 | struct AccelCPUClass; | |
97 | ||
8b80bd28 PMD |
98 | /* see sysemu-cpu-ops.h */ |
99 | struct SysemuCPUOps; | |
100 | ||
dd83b06a AF |
101 | /** |
102 | * CPUClass: | |
2b8c2754 AF |
103 | * @class_by_name: Callback to map -cpu command line model name to an |
104 | * instantiatable CPU type. | |
94a444b2 | 105 | * @parse_features: Callback to parse command line arguments. |
91b1df8c | 106 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 107 | * @has_work: Callback for checking if there is work to do. |
f3659eee | 108 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee | 109 | * @dump_state: Callback for dumping state. |
5503da4a TH |
110 | * @query_cpu_fast: |
111 | * Fill in target specific information for the "query-cpus-fast" | |
112 | * QAPI call. | |
997395d3 | 113 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
42f6ed91 JS |
114 | * @set_pc: Callback for setting the Program Counter register. This |
115 | * should have the semantics used by the target architecture when | |
116 | * setting the PC from a source such as an ELF file entry point; | |
117 | * for example on Arm it will also set the Thumb mode bit based | |
118 | * on the least significant bit of the new PC value. | |
119 | * If the target behaviour here is anything other than "set | |
120 | * the PC register to the value passed in" then the target must | |
121 | * also implement the synchronize_from_tb hook. | |
e4fdf9df RH |
122 | * @get_pc: Callback for getting the Program Counter register. |
123 | * As above, with the semantics of the target architecture. | |
5b50e790 AF |
124 | * @gdb_read_register: Callback for letting GDB read a register. |
125 | * @gdb_write_register: Callback for letting GDB write a register. | |
5bc31e94 RH |
126 | * @gdb_adjust_breakpoint: Callback for adjusting the address of a |
127 | * breakpoint. Used by AVR to handle a gdb mis-feature with | |
128 | * its Harvard architecture split code and data. | |
a0e372f0 | 129 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 130 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
131 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
132 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
133 | * @gdb_arch_name: Optional callback that returns the architecture name known |
134 | * to GDB. The caller must free the returned string with g_free. | |
200bf5b7 AB |
135 | * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the |
136 | * gdb stub. Returns a pointer to the XML contents for the specified XML file | |
137 | * or NULL if the CPU doesn't have a dynamically generated content for it. | |
37b9de46 | 138 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
139 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
140 | * address before attempting to match it against watchpoints. | |
61ad65d0 RH |
141 | * @deprecation_note: If this CPUClass is deprecated, this field provides |
142 | * related information. | |
dd83b06a AF |
143 | * |
144 | * Represents a CPU family or model. | |
145 | */ | |
db1015e9 | 146 | struct CPUClass { |
dd83b06a | 147 | /*< private >*/ |
961f8395 | 148 | DeviceClass parent_class; |
dd83b06a AF |
149 | /*< public >*/ |
150 | ||
2b8c2754 | 151 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 152 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 153 | |
8c2e1b00 | 154 | bool (*has_work)(CPUState *cpu); |
f3659eee AF |
155 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
156 | uint8_t *buf, int len, bool is_write); | |
90c84c56 | 157 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
5503da4a | 158 | void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); |
997395d3 | 159 | int64_t (*get_arch_id)(CPUState *cpu); |
f45748f1 | 160 | void (*set_pc)(CPUState *cpu, vaddr value); |
e4fdf9df | 161 | vaddr (*get_pc)(CPUState *cpu); |
a010bdbe | 162 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
5b50e790 | 163 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
5bc31e94 | 164 | vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); |
b170fce3 | 165 | |
5b24c641 | 166 | const char *gdb_core_xml_file; |
b3820e6c | 167 | gchar * (*gdb_arch_name)(CPUState *cpu); |
200bf5b7 | 168 | const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); |
37b9de46 PC |
169 | |
170 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
55c3ceef | 171 | |
61ad65d0 | 172 | const char *deprecation_note; |
fb6916dd | 173 | struct AccelCPUClass *accel_cpu; |
e9e51b71 | 174 | |
8b80bd28 PMD |
175 | /* when system emulation is not available, this pointer is NULL */ |
176 | const struct SysemuCPUOps *sysemu_ops; | |
177 | ||
78271684 | 178 | /* when TCG is not available, this pointer is NULL */ |
11906557 | 179 | const struct TCGCPUOps *tcg_ops; |
cc3f2be6 CF |
180 | |
181 | /* | |
182 | * if not NULL, this is called in order for the CPUClass to initialize | |
183 | * class data that depends on the accelerator, see accel/accel-common.c. | |
184 | */ | |
185 | void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc); | |
dc29f474 RH |
186 | |
187 | /* | |
188 | * Keep non-pointer data at the end to minimize holes. | |
189 | */ | |
190 | int reset_dump_flags; | |
191 | int gdb_num_core_regs; | |
192 | bool gdb_stop_before_watchpoint; | |
db1015e9 | 193 | }; |
dd83b06a | 194 | |
5e140196 RH |
195 | /* |
196 | * Low 16 bits: number of cycles left, used only in icount mode. | |
197 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs | |
198 | * for this CPU and return to its top level loop (even in non-icount mode). | |
199 | * This allows a single read-compare-cbranch-write sequence to test | |
200 | * for both decrementer underflow and exceptions. | |
201 | */ | |
202 | typedef union IcountDecr { | |
203 | uint32_t u32; | |
204 | struct { | |
e03b5686 | 205 | #if HOST_BIG_ENDIAN |
5e140196 RH |
206 | uint16_t high; |
207 | uint16_t low; | |
28ecfd7a | 208 | #else |
5e140196 RH |
209 | uint16_t low; |
210 | uint16_t high; | |
28ecfd7a | 211 | #endif |
5e140196 RH |
212 | } u16; |
213 | } IcountDecr; | |
28ecfd7a | 214 | |
f0c3c505 AF |
215 | typedef struct CPUBreakpoint { |
216 | vaddr pc; | |
217 | int flags; /* BP_* */ | |
218 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
219 | } CPUBreakpoint; | |
220 | ||
568496c0 | 221 | struct CPUWatchpoint { |
ff4700b0 | 222 | vaddr vaddr; |
05068c0d | 223 | vaddr len; |
08225676 | 224 | vaddr hitaddr; |
66b9b43c | 225 | MemTxAttrs hitattrs; |
ff4700b0 AF |
226 | int flags; /* BP_* */ |
227 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 228 | }; |
ff4700b0 | 229 | |
a60f24b5 | 230 | struct KVMState; |
f7575c96 | 231 | struct kvm_run; |
a60f24b5 | 232 | |
4b4629d9 | 233 | /* work queue */ |
14e6fe12 PB |
234 | |
235 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
236 | * hosts in a single parameter | |
237 | */ | |
238 | typedef union { | |
239 | int host_int; | |
240 | unsigned long host_ulong; | |
241 | void *host_ptr; | |
242 | vaddr target_ptr; | |
243 | } run_on_cpu_data; | |
244 | ||
245 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
246 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
247 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
248 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
249 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
250 | ||
251 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
252 | ||
d148d90e | 253 | struct qemu_work_item; |
4b4629d9 | 254 | |
0b8497f0 IM |
255 | #define CPU_UNSET_NUMA_NODE_ID -1 |
256 | ||
dd83b06a AF |
257 | /** |
258 | * CPUState: | |
55e5c285 | 259 | * @cpu_index: CPU index (informative). |
7ea7b9ad PM |
260 | * @cluster_index: Identifies which cluster this CPU is in. |
261 | * For boards which don't define clusters or for "loose" CPUs not assigned | |
262 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will | |
263 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER | |
264 | * QOM parent. | |
a371975e PMD |
265 | * Under TCG this value is propagated to @tcg_cflags. |
266 | * See TranslationBlock::TCG CF_CLUSTER_MASK. | |
6cc9d67c | 267 | * @tcg_cflags: Pre-computed cflags for this cpu. |
ce3960eb AF |
268 | * @nr_cores: Number of cores within this CPU package. |
269 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
270 | * @running: #true if CPU is currently running (lockless). |
271 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 272 | * valid under cpu_list_lock. |
61a46217 | 273 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
274 | * @interrupt_request: Indicates a pending interrupt request. |
275 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 276 | * @stop: Indicates a pending stop request. |
f324e766 | 277 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 278 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 279 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 280 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 281 | * @icount_extra: Instructions until next timer event. |
414b15c9 PB |
282 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
283 | * requires that IO only be performed on the last instruction of a TB | |
284 | * so that interrupts take effect immediately. | |
32857f4d PM |
285 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
286 | * AddressSpaces this CPU has) | |
12ebc9a7 | 287 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
288 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
289 | * only have a single AddressSpace | |
c05efcb1 | 290 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
5e140196 | 291 | * @icount_decr_ptr: Pointer to IcountDecr field within subclass. |
eac8b355 | 292 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 293 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 294 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 295 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 296 | * @opaque: User data. |
93afeade | 297 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
f861b3f3 | 298 | * @accel: Pointer to accelerator specific state. |
8737c51c | 299 | * @kvm_fd: vCPU file descriptor for KVM. |
0c0fcc20 EC |
300 | * @work_mutex: Lock to prevent multiple access to @work_list. |
301 | * @work_list: List of pending asynchronous work. | |
d4381116 LV |
302 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
303 | * to @trace_dstate). | |
48151859 | 304 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
54cb65d8 | 305 | * @plugin_mask: Plugin event bitmap. Modified only via async work. |
ed860129 PM |
306 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
307 | * flag of the same name: allows the board to suppress calling of the | |
308 | * CPU do_transaction_failed hook function. | |
b4420f19 PX |
309 | * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty |
310 | * ring is enabled. | |
311 | * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU | |
312 | * dirty ring structure. | |
dd83b06a AF |
313 | * |
314 | * State of one CPU core or thread. | |
315 | */ | |
316 | struct CPUState { | |
317 | /*< private >*/ | |
961f8395 | 318 | DeviceState parent_obj; |
6fbdff87 AB |
319 | /* cache to avoid expensive CPU_GET_CLASS */ |
320 | CPUClass *cc; | |
dd83b06a AF |
321 | /*< public >*/ |
322 | ||
ce3960eb AF |
323 | int nr_cores; |
324 | int nr_threads; | |
325 | ||
814e612e | 326 | struct QemuThread *thread; |
bcba2a72 | 327 | #ifdef _WIN32 |
c9923550 | 328 | QemuSemaphore sem; |
bcba2a72 | 329 | #endif |
9f09e18a | 330 | int thread_id; |
c265e976 | 331 | bool running, has_waiter; |
f5c121b8 | 332 | struct QemuCond *halt_cond; |
216fc9a4 | 333 | bool thread_kicked; |
61a46217 | 334 | bool created; |
4fdeee7c | 335 | bool stop; |
f324e766 | 336 | bool stopped; |
c1b70158 TJB |
337 | |
338 | /* Should CPU start in powered-off state? */ | |
339 | bool start_powered_off; | |
340 | ||
4c055ab5 | 341 | bool unplug; |
bac05aa9 | 342 | bool crash_occurred; |
e0c38211 | 343 | bool exit_request; |
df8a6880 | 344 | int exclusive_context_count; |
9b990ee5 | 345 | uint32_t cflags_next_tb; |
8d04fb55 | 346 | /* updates protected by BQL */ |
259186a7 | 347 | uint32_t interrupt_request; |
ed2803da | 348 | int singlestep_enabled; |
e4cd9657 | 349 | int64_t icount_budget; |
efee7340 | 350 | int64_t icount_extra; |
9c09a251 | 351 | uint64_t random_seed; |
6f03bef0 | 352 | sigjmp_buf jmp_env; |
bcba2a72 | 353 | |
376692b9 | 354 | QemuMutex work_mutex; |
0c0fcc20 | 355 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
376692b9 | 356 | |
32857f4d | 357 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 358 | int num_ases; |
09daed84 | 359 | AddressSpace *as; |
6731d864 | 360 | MemoryRegion *memory; |
09daed84 | 361 | |
1ea4a06a | 362 | CPUArchState *env_ptr; |
5e140196 | 363 | IcountDecr *icount_decr_ptr; |
7d7500d9 | 364 | |
a976a99a | 365 | CPUJumpCache *tb_jmp_cache; |
7d7500d9 | 366 | |
eac8b355 | 367 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 368 | int gdb_num_regs; |
35143f01 | 369 | int gdb_num_g_regs; |
bdc44640 | 370 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 371 | |
f0c3c505 | 372 | /* ice debug support */ |
b58deb34 | 373 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
f0c3c505 | 374 | |
b58deb34 | 375 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
ff4700b0 AF |
376 | CPUWatchpoint *watchpoint_hit; |
377 | ||
0429a971 AF |
378 | void *opaque; |
379 | ||
93afeade AF |
380 | /* In order to avoid passing too many arguments to the MMIO helpers, |
381 | * we store some rarely used information in the CPU context. | |
382 | */ | |
383 | uintptr_t mem_io_pc; | |
93afeade | 384 | |
b4420f19 | 385 | /* Only used in KVM */ |
8737c51c | 386 | int kvm_fd; |
a60f24b5 | 387 | struct KVMState *kvm_state; |
f7575c96 | 388 | struct kvm_run *kvm_run; |
b4420f19 PX |
389 | struct kvm_dirty_gfn *kvm_dirty_gfns; |
390 | uint32_t kvm_fetch_index; | |
7786ae40 | 391 | uint64_t dirty_pages; |
3b6f4852 | 392 | int kvm_vcpu_stats_fd; |
8737c51c | 393 | |
bd688fc9 EGE |
394 | /* Use by accel-block: CPU is executing an ioctl() */ |
395 | QemuLockCnt in_ioctl_lock; | |
396 | ||
54cb65d8 EC |
397 | DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); |
398 | ||
2f3a57ee | 399 | #ifdef CONFIG_PLUGIN |
54cb65d8 | 400 | GArray *plugin_mem_cbs; |
c5ffd16b | 401 | #endif |
54cb65d8 | 402 | |
f5df5baf | 403 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e | 404 | int cpu_index; |
7ea7b9ad | 405 | int cluster_index; |
6cc9d67c | 406 | uint32_t tcg_cflags; |
6fda014e | 407 | uint32_t halted; |
99df7dce | 408 | uint32_t can_do_io; |
6fda014e | 409 | int32_t exception_index; |
7e4fb26d | 410 | |
f861b3f3 | 411 | AccelCPUState *accel; |
b91b0fc1 | 412 | /* shared by kvm and hvf */ |
99f31832 SAGDR |
413 | bool vcpu_dirty; |
414 | ||
2adcc85d JH |
415 | /* Used to keep track of an outstanding cpu throttle thread for migration |
416 | * autoconverge | |
417 | */ | |
418 | bool throttle_thread_scheduled; | |
419 | ||
baa60983 HH |
420 | /* |
421 | * Sleep throttle_us_per_full microseconds once dirty ring is full | |
422 | * if dirty page rate limit is enabled. | |
423 | */ | |
424 | int64_t throttle_us_per_full; | |
425 | ||
ed860129 PM |
426 | bool ignore_memory_transaction_failures; |
427 | ||
6e8dcacd RH |
428 | /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ |
429 | bool prctl_unalign_sigbus; | |
430 | ||
1f871c5e PM |
431 | /* track IOMMUs whose translations we've cached in the TCG TLB */ |
432 | GArray *iommu_notifiers; | |
dd83b06a AF |
433 | }; |
434 | ||
f481ee2d PB |
435 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
436 | extern CPUTailQ cpus; | |
437 | ||
068a5ea0 EC |
438 | #define first_cpu QTAILQ_FIRST_RCU(&cpus) |
439 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) | |
440 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) | |
bdc44640 | 441 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
068a5ea0 | 442 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) |
182735ef | 443 | |
f240eb6f | 444 | extern __thread CPUState *current_cpu; |
4917cf44 | 445 | |
8d4e9146 FK |
446 | /** |
447 | * qemu_tcg_mttcg_enabled: | |
448 | * Check whether we are running MultiThread TCG or not. | |
449 | * | |
450 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
451 | */ | |
452 | extern bool mttcg_enabled; | |
453 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
454 | ||
444d5590 AF |
455 | /** |
456 | * cpu_paging_enabled: | |
457 | * @cpu: The CPU whose state is to be inspected. | |
458 | * | |
459 | * Returns: %true if paging is enabled, %false otherwise. | |
460 | */ | |
461 | bool cpu_paging_enabled(const CPUState *cpu); | |
462 | ||
a23bbfda AF |
463 | /** |
464 | * cpu_get_memory_mapping: | |
465 | * @cpu: The CPU whose memory mappings are to be obtained. | |
466 | * @list: Where to write the memory mappings to. | |
467 | * @errp: Pointer for reporting an #Error. | |
468 | */ | |
469 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
470 | Error **errp); | |
471 | ||
cfe35d48 PMD |
472 | #if !defined(CONFIG_USER_ONLY) |
473 | ||
c72bf468 JF |
474 | /** |
475 | * cpu_write_elf64_note: | |
476 | * @f: pointer to a function that writes memory to a file | |
477 | * @cpu: The CPU whose memory is to be dumped | |
478 | * @cpuid: ID number of the CPU | |
479 | * @opaque: pointer to the CPUState struct | |
480 | */ | |
481 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
482 | int cpuid, void *opaque); | |
483 | ||
484 | /** | |
485 | * cpu_write_elf64_qemunote: | |
486 | * @f: pointer to a function that writes memory to a file | |
487 | * @cpu: The CPU whose memory is to be dumped | |
488 | * @cpuid: ID number of the CPU | |
489 | * @opaque: pointer to the CPUState struct | |
490 | */ | |
491 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
492 | void *opaque); | |
493 | ||
494 | /** | |
495 | * cpu_write_elf32_note: | |
496 | * @f: pointer to a function that writes memory to a file | |
497 | * @cpu: The CPU whose memory is to be dumped | |
498 | * @cpuid: ID number of the CPU | |
499 | * @opaque: pointer to the CPUState struct | |
500 | */ | |
501 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
502 | int cpuid, void *opaque); | |
503 | ||
504 | /** | |
505 | * cpu_write_elf32_qemunote: | |
506 | * @f: pointer to a function that writes memory to a file | |
507 | * @cpu: The CPU whose memory is to be dumped | |
508 | * @cpuid: ID number of the CPU | |
509 | * @opaque: pointer to the CPUState struct | |
510 | */ | |
511 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
512 | void *opaque); | |
dd83b06a | 513 | |
c86f106b AN |
514 | /** |
515 | * cpu_get_crash_info: | |
516 | * @cpu: The CPU to get crash information for | |
517 | * | |
518 | * Gets the previously saved crash information. | |
519 | * Caller is responsible for freeing the data. | |
520 | */ | |
521 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
522 | ||
cfe35d48 PMD |
523 | #endif /* !CONFIG_USER_ONLY */ |
524 | ||
878096ee AF |
525 | /** |
526 | * CPUDumpFlags: | |
527 | * @CPU_DUMP_CODE: | |
528 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
529 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
b84694de | 530 | * @CPU_DUMP_VPU: dump VPU registers |
878096ee AF |
531 | */ |
532 | enum CPUDumpFlags { | |
533 | CPU_DUMP_CODE = 0x00010000, | |
534 | CPU_DUMP_FPU = 0x00020000, | |
535 | CPU_DUMP_CCOP = 0x00040000, | |
b84694de | 536 | CPU_DUMP_VPU = 0x00080000, |
878096ee AF |
537 | }; |
538 | ||
539 | /** | |
540 | * cpu_dump_state: | |
541 | * @cpu: The CPU whose state is to be dumped. | |
90c84c56 | 542 | * @f: If non-null, dump to this stream, else to current print sink. |
878096ee AF |
543 | * |
544 | * Dumps CPU state. | |
545 | */ | |
90c84c56 | 546 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
878096ee | 547 | |
00b941e5 | 548 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
549 | /** |
550 | * cpu_get_phys_page_attrs_debug: | |
551 | * @cpu: The CPU to obtain the physical page address for. | |
552 | * @addr: The virtual address. | |
553 | * @attrs: Updated on return with the memory transaction attributes to use | |
554 | * for this access. | |
555 | * | |
556 | * Obtains the physical page corresponding to a virtual one, together | |
557 | * with the corresponding memory transaction attributes to use for the access. | |
558 | * Use it only for debugging because no protection checks are done. | |
559 | * | |
560 | * Returns: Corresponding physical page address or -1 if no page found. | |
561 | */ | |
a41d3aae PMD |
562 | hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
563 | MemTxAttrs *attrs); | |
1dc6fb1f | 564 | |
00b941e5 AF |
565 | /** |
566 | * cpu_get_phys_page_debug: | |
567 | * @cpu: The CPU to obtain the physical page address for. | |
568 | * @addr: The virtual address. | |
569 | * | |
570 | * Obtains the physical page corresponding to a virtual one. | |
571 | * Use it only for debugging because no protection checks are done. | |
572 | * | |
573 | * Returns: Corresponding physical page address or -1 if no page found. | |
574 | */ | |
a41d3aae | 575 | hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
d7f25a9e PM |
576 | |
577 | /** cpu_asidx_from_attrs: | |
578 | * @cpu: CPU | |
579 | * @attrs: memory transaction attributes | |
580 | * | |
581 | * Returns the address space index specifying the CPU AddressSpace | |
582 | * to use for a memory access with the given transaction attributes. | |
583 | */ | |
a41d3aae | 584 | int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); |
d7f25a9e | 585 | |
cdba7e2f PMD |
586 | /** |
587 | * cpu_virtio_is_big_endian: | |
588 | * @cpu: CPU | |
589 | ||
590 | * Returns %true if a CPU which supports runtime configurable endianness | |
591 | * is currently big-endian. | |
592 | */ | |
593 | bool cpu_virtio_is_big_endian(CPUState *cpu); | |
cfe35d48 PMD |
594 | |
595 | #endif /* CONFIG_USER_ONLY */ | |
00b941e5 | 596 | |
267f685b PB |
597 | /** |
598 | * cpu_list_add: | |
599 | * @cpu: The CPU to be added to the list of CPUs. | |
600 | */ | |
601 | void cpu_list_add(CPUState *cpu); | |
602 | ||
603 | /** | |
604 | * cpu_list_remove: | |
605 | * @cpu: The CPU to be removed from the list of CPUs. | |
606 | */ | |
607 | void cpu_list_remove(CPUState *cpu); | |
608 | ||
dd83b06a AF |
609 | /** |
610 | * cpu_reset: | |
611 | * @cpu: The CPU whose state is to be reset. | |
612 | */ | |
613 | void cpu_reset(CPUState *cpu); | |
614 | ||
2b8c2754 AF |
615 | /** |
616 | * cpu_class_by_name: | |
617 | * @typename: The CPU base type. | |
618 | * @cpu_model: The model string without any parameters. | |
619 | * | |
620 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
621 | * | |
622 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
623 | */ | |
624 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
625 | ||
3c72234c IM |
626 | /** |
627 | * cpu_create: | |
628 | * @typename: The CPU type. | |
629 | * | |
630 | * Instantiates a CPU and realizes the CPU. | |
631 | * | |
632 | * Returns: A #CPUState or %NULL if an error occurred. | |
633 | */ | |
634 | CPUState *cpu_create(const char *typename); | |
635 | ||
636 | /** | |
c1c8cfe5 EH |
637 | * parse_cpu_option: |
638 | * @cpu_option: The -cpu option including optional parameters. | |
3c72234c IM |
639 | * |
640 | * processes optional parameters and registers them as global properties | |
641 | * | |
4482e05c IM |
642 | * Returns: type of CPU to create or prints error and terminates process |
643 | * if an error occurred. | |
3c72234c | 644 | */ |
c1c8cfe5 | 645 | const char *parse_cpu_option(const char *cpu_option); |
9262685b | 646 | |
3993c6bd | 647 | /** |
8c2e1b00 | 648 | * cpu_has_work: |
3993c6bd AF |
649 | * @cpu: The vCPU to check. |
650 | * | |
651 | * Checks whether the CPU has work to do. | |
652 | * | |
653 | * Returns: %true if the CPU has work, %false otherwise. | |
654 | */ | |
8c2e1b00 AF |
655 | static inline bool cpu_has_work(CPUState *cpu) |
656 | { | |
657 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
658 | ||
659 | g_assert(cc->has_work); | |
660 | return cc->has_work(cpu); | |
661 | } | |
3993c6bd | 662 | |
60e82579 AF |
663 | /** |
664 | * qemu_cpu_is_self: | |
665 | * @cpu: The vCPU to check against. | |
666 | * | |
667 | * Checks whether the caller is executing on the vCPU thread. | |
668 | * | |
669 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
670 | */ | |
671 | bool qemu_cpu_is_self(CPUState *cpu); | |
672 | ||
c08d7424 AF |
673 | /** |
674 | * qemu_cpu_kick: | |
675 | * @cpu: The vCPU to kick. | |
676 | * | |
677 | * Kicks @cpu's thread. | |
678 | */ | |
679 | void qemu_cpu_kick(CPUState *cpu); | |
680 | ||
2fa45344 AF |
681 | /** |
682 | * cpu_is_stopped: | |
683 | * @cpu: The CPU to check. | |
684 | * | |
685 | * Checks whether the CPU is stopped. | |
686 | * | |
687 | * Returns: %true if run state is not running or if artificially stopped; | |
688 | * %false otherwise. | |
689 | */ | |
690 | bool cpu_is_stopped(CPUState *cpu); | |
691 | ||
d148d90e SF |
692 | /** |
693 | * do_run_on_cpu: | |
694 | * @cpu: The vCPU to run on. | |
695 | * @func: The function to be executed. | |
696 | * @data: Data to pass to the function. | |
697 | * @mutex: Mutex to release while waiting for @func to run. | |
698 | * | |
699 | * Used internally in the implementation of run_on_cpu. | |
700 | */ | |
14e6fe12 | 701 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
702 | QemuMutex *mutex); |
703 | ||
f100f0b3 AF |
704 | /** |
705 | * run_on_cpu: | |
706 | * @cpu: The vCPU to run on. | |
707 | * @func: The function to be executed. | |
708 | * @data: Data to pass to the function. | |
709 | * | |
710 | * Schedules the function @func for execution on the vCPU @cpu. | |
711 | */ | |
14e6fe12 | 712 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 713 | |
3c02270d CV |
714 | /** |
715 | * async_run_on_cpu: | |
716 | * @cpu: The vCPU to run on. | |
717 | * @func: The function to be executed. | |
718 | * @data: Data to pass to the function. | |
719 | * | |
720 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
721 | */ | |
14e6fe12 | 722 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 723 | |
53f5ed95 PB |
724 | /** |
725 | * async_safe_run_on_cpu: | |
726 | * @cpu: The vCPU to run on. | |
727 | * @func: The function to be executed. | |
728 | * @data: Data to pass to the function. | |
729 | * | |
730 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
731 | * while all other vCPUs are sleeping. | |
732 | * | |
733 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
734 | * BQL. | |
735 | */ | |
14e6fe12 | 736 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 737 | |
cfbc3c60 EC |
738 | /** |
739 | * cpu_in_exclusive_context() | |
740 | * @cpu: The vCPU to check | |
741 | * | |
742 | * Returns true if @cpu is an exclusive context, for example running | |
743 | * something which has previously been queued via async_safe_run_on_cpu(). | |
744 | */ | |
745 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) | |
746 | { | |
df8a6880 | 747 | return cpu->exclusive_context_count; |
cfbc3c60 EC |
748 | } |
749 | ||
38d8f5c8 AF |
750 | /** |
751 | * qemu_get_cpu: | |
752 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
753 | * | |
754 | * Gets a CPU matching @index. | |
755 | * | |
756 | * Returns: The CPU or %NULL if there is no matching CPU. | |
757 | */ | |
758 | CPUState *qemu_get_cpu(int index); | |
759 | ||
69e5ff06 IM |
760 | /** |
761 | * cpu_exists: | |
762 | * @id: Guest-exposed CPU ID to lookup. | |
763 | * | |
764 | * Search for CPU with specified ID. | |
765 | * | |
766 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
767 | */ | |
768 | bool cpu_exists(int64_t id); | |
769 | ||
5ce46cb3 EH |
770 | /** |
771 | * cpu_by_arch_id: | |
772 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
773 | * | |
774 | * Get a CPU with matching @id. | |
775 | * | |
776 | * Returns: The CPU or %NULL if there is no matching CPU. | |
777 | */ | |
778 | CPUState *cpu_by_arch_id(int64_t id); | |
779 | ||
c3affe56 AF |
780 | /** |
781 | * cpu_interrupt: | |
782 | * @cpu: The CPU to set an interrupt on. | |
7e63bc38 | 783 | * @mask: The interrupts to set. |
c3affe56 AF |
784 | * |
785 | * Invokes the interrupt handler. | |
786 | */ | |
c3affe56 AF |
787 | |
788 | void cpu_interrupt(CPUState *cpu, int mask); | |
789 | ||
2991b890 PC |
790 | /** |
791 | * cpu_set_pc: | |
792 | * @cpu: The CPU to set the program counter for. | |
793 | * @addr: Program counter value. | |
794 | * | |
795 | * Sets the program counter for a CPU. | |
796 | */ | |
797 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
798 | { | |
799 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
800 | ||
801 | cc->set_pc(cpu, addr); | |
802 | } | |
803 | ||
d8ed887b AF |
804 | /** |
805 | * cpu_reset_interrupt: | |
806 | * @cpu: The CPU to clear the interrupt on. | |
807 | * @mask: The interrupt mask to clear. | |
808 | * | |
809 | * Resets interrupts on the vCPU @cpu. | |
810 | */ | |
811 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
812 | ||
60a3e17a AF |
813 | /** |
814 | * cpu_exit: | |
815 | * @cpu: The CPU to exit. | |
816 | * | |
817 | * Requests the CPU @cpu to exit execution. | |
818 | */ | |
819 | void cpu_exit(CPUState *cpu); | |
820 | ||
2993683b IM |
821 | /** |
822 | * cpu_resume: | |
823 | * @cpu: The CPU to resume. | |
824 | * | |
825 | * Resumes CPU, i.e. puts CPU into runnable state. | |
826 | */ | |
827 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 828 | |
4c055ab5 | 829 | /** |
2c579042 BR |
830 | * cpu_remove_sync: |
831 | * @cpu: The CPU to remove. | |
832 | * | |
833 | * Requests the CPU to be removed and waits till it is removed. | |
834 | */ | |
835 | void cpu_remove_sync(CPUState *cpu); | |
836 | ||
d148d90e SF |
837 | /** |
838 | * process_queued_cpu_work() - process all items on CPU work queue | |
839 | * @cpu: The CPU which work queue to process. | |
840 | */ | |
841 | void process_queued_cpu_work(CPUState *cpu); | |
842 | ||
ab129972 PB |
843 | /** |
844 | * cpu_exec_start: | |
845 | * @cpu: The CPU for the current thread. | |
846 | * | |
847 | * Record that a CPU has started execution and can be interrupted with | |
848 | * cpu_exit. | |
849 | */ | |
850 | void cpu_exec_start(CPUState *cpu); | |
851 | ||
852 | /** | |
853 | * cpu_exec_end: | |
854 | * @cpu: The CPU for the current thread. | |
855 | * | |
856 | * Record that a CPU has stopped execution and exclusive sections | |
857 | * can be executed without interrupting it. | |
858 | */ | |
859 | void cpu_exec_end(CPUState *cpu); | |
860 | ||
861 | /** | |
862 | * start_exclusive: | |
863 | * | |
864 | * Wait for a concurrent exclusive section to end, and then start | |
865 | * a section of work that is run while other CPUs are not running | |
866 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
867 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
868 | * during the exclusive section go to sleep until this CPU calls | |
869 | * end_exclusive. | |
ab129972 PB |
870 | */ |
871 | void start_exclusive(void); | |
872 | ||
873 | /** | |
874 | * end_exclusive: | |
875 | * | |
876 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
877 | */ |
878 | void end_exclusive(void); | |
879 | ||
c643bed9 AF |
880 | /** |
881 | * qemu_init_vcpu: | |
882 | * @cpu: The vCPU to initialize. | |
883 | * | |
884 | * Initializes a vCPU. | |
885 | */ | |
886 | void qemu_init_vcpu(CPUState *cpu); | |
887 | ||
3825b28f AF |
888 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
889 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
890 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
891 | ||
892 | /** | |
893 | * cpu_single_step: | |
894 | * @cpu: CPU to the flags for. | |
895 | * @enabled: Flags to enable. | |
896 | * | |
897 | * Enables or disables single-stepping for @cpu. | |
898 | */ | |
899 | void cpu_single_step(CPUState *cpu, int enabled); | |
900 | ||
b3310ab3 AF |
901 | /* Breakpoint/watchpoint flags */ |
902 | #define BP_MEM_READ 0x01 | |
903 | #define BP_MEM_WRITE 0x02 | |
904 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
905 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 906 | /* 0x08 currently unused */ |
b3310ab3 AF |
907 | #define BP_GDB 0x10 |
908 | #define BP_CPU 0x20 | |
b933066a | 909 | #define BP_ANY (BP_GDB | BP_CPU) |
019a9808 RH |
910 | #define BP_HIT_SHIFT 6 |
911 | #define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) | |
912 | #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) | |
913 | #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) | |
b3310ab3 AF |
914 | |
915 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
916 | CPUBreakpoint **breakpoint); | |
917 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
918 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
919 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
920 | ||
b933066a RH |
921 | /* Return true if PC matches an installed breakpoint. */ |
922 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
923 | { | |
924 | CPUBreakpoint *bp; | |
925 | ||
926 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
927 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
928 | if (bp->pc == pc && (bp->flags & mask)) { | |
929 | return true; | |
930 | } | |
931 | } | |
932 | } | |
933 | return false; | |
934 | } | |
935 | ||
87e303de | 936 | #if defined(CONFIG_USER_ONLY) |
74841f04 RH |
937 | static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
938 | int flags, CPUWatchpoint **watchpoint) | |
939 | { | |
940 | return -ENOSYS; | |
941 | } | |
942 | ||
943 | static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
944 | vaddr len, int flags) | |
945 | { | |
946 | return -ENOSYS; | |
947 | } | |
948 | ||
949 | static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, | |
950 | CPUWatchpoint *wp) | |
951 | { | |
952 | } | |
953 | ||
954 | static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
955 | { | |
956 | } | |
957 | #else | |
75a34036 AF |
958 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
959 | int flags, CPUWatchpoint **watchpoint); | |
960 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
961 | vaddr len, int flags); | |
962 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
963 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
74841f04 | 964 | #endif |
75a34036 | 965 | |
6d03226b AB |
966 | /** |
967 | * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? | |
968 | * @cs: CPUState pointer | |
969 | * | |
970 | * The memory callbacks are installed if a plugin has instrumented an | |
971 | * instruction for memory. This can be useful to know if you want to | |
972 | * force a slow path for a series of memory accesses. | |
973 | */ | |
974 | static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) | |
975 | { | |
976 | #ifdef CONFIG_PLUGIN | |
977 | return !!cpu->plugin_mem_cbs; | |
978 | #else | |
979 | return false; | |
980 | #endif | |
981 | } | |
982 | ||
63c91552 PB |
983 | /** |
984 | * cpu_get_address_space: | |
985 | * @cpu: CPU to get address space from | |
986 | * @asidx: index identifying which address space to get | |
987 | * | |
988 | * Return the requested address space of this CPU. @asidx | |
989 | * specifies which address space to read. | |
990 | */ | |
991 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
992 | ||
8905770b | 993 | G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) |
9edc6313 | 994 | G_GNUC_PRINTF(2, 3); |
7df5e3d6 CF |
995 | |
996 | /* $(top_srcdir)/cpu.c */ | |
995b87de | 997 | void cpu_class_init_props(DeviceClass *dc); |
39e329e3 | 998 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 999 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 1000 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1001 | |
c95ac103 TH |
1002 | /** |
1003 | * target_words_bigendian: | |
1004 | * Returns true if the (default) endianness of the target is big endian, | |
1005 | * false otherwise. Note that in target-specific code, you can use | |
ee3eb3a7 | 1006 | * TARGET_BIG_ENDIAN directly instead. On the other hand, common |
c95ac103 TH |
1007 | * code should normally never need to know about the endianness of the |
1008 | * target, so please do *not* use this function unless you know very well | |
1009 | * what you are doing! | |
1010 | */ | |
1011 | bool target_words_bigendian(void); | |
1012 | ||
1077f50b TH |
1013 | const char *target_name(void); |
1014 | ||
4e40e893 MAL |
1015 | void page_size_init(void); |
1016 | ||
47507383 TH |
1017 | #ifdef NEED_CPU_H |
1018 | ||
75fe97b4 | 1019 | #ifndef CONFIG_USER_ONLY |
feece4d0 | 1020 | |
8a9358cc | 1021 | extern const VMStateDescription vmstate_cpu_common; |
1a1562f5 AF |
1022 | |
1023 | #define VMSTATE_CPU() { \ | |
1024 | .name = "parent_obj", \ | |
1025 | .size = sizeof(CPUState), \ | |
1026 | .vmsd = &vmstate_cpu_common, \ | |
1027 | .flags = VMS_STRUCT, \ | |
1028 | .offset = 0, \ | |
1029 | } | |
75fe97b4 | 1030 | #endif /* !CONFIG_USER_ONLY */ |
1a1562f5 | 1031 | |
47507383 TH |
1032 | #endif /* NEED_CPU_H */ |
1033 | ||
a07f953e | 1034 | #define UNASSIGNED_CPU_INDEX -1 |
7ea7b9ad | 1035 | #define UNASSIGNED_CLUSTER_INDEX -1 |
a07f953e | 1036 | |
dd83b06a | 1037 | #endif |