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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
3979fca4 | 24 | #include "disas/dis-asm.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
66b9b43c | 26 | #include "exec/memattrs.h" |
9af23989 | 27 | #include "qapi/qapi-types-run-state.h" |
48151859 | 28 | #include "qemu/bitmap.h" |
068a5ea0 | 29 | #include "qemu/rcu_queue.h" |
bdc44640 | 30 | #include "qemu/queue.h" |
1de7afc9 | 31 | #include "qemu/thread.h" |
54cb65d8 | 32 | #include "qemu/plugin.h" |
db1015e9 | 33 | #include "qom/object.h" |
dd83b06a | 34 | |
b5ba1cc6 QN |
35 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
36 | void *opaque); | |
c72bf468 | 37 | |
577f42c0 AF |
38 | /** |
39 | * vaddr: | |
40 | * Type wide enough to contain any #target_ulong virtual address. | |
41 | */ | |
42 | typedef uint64_t vaddr; | |
43 | #define VADDR_PRId PRId64 | |
44 | #define VADDR_PRIu PRIu64 | |
45 | #define VADDR_PRIo PRIo64 | |
46 | #define VADDR_PRIx PRIx64 | |
47 | #define VADDR_PRIX PRIX64 | |
48 | #define VADDR_MAX UINT64_MAX | |
49 | ||
dd83b06a AF |
50 | /** |
51 | * SECTION:cpu | |
52 | * @section_id: QEMU-cpu | |
53 | * @title: CPU Class | |
54 | * @short_description: Base class for all CPUs | |
55 | */ | |
56 | ||
57 | #define TYPE_CPU "cpu" | |
58 | ||
0d6d1ab4 AF |
59 | /* Since this macro is used a lot in hot code paths and in conjunction with |
60 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
61 | * an unchecked cast. | |
62 | */ | |
63 | #define CPU(obj) ((CPUState *)(obj)) | |
64 | ||
db1015e9 | 65 | typedef struct CPUClass CPUClass; |
8110fa1d EH |
66 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, |
67 | TYPE_CPU) | |
dd83b06a | 68 | |
b35399bb SS |
69 | typedef enum MMUAccessType { |
70 | MMU_DATA_LOAD = 0, | |
71 | MMU_DATA_STORE = 1, | |
72 | MMU_INST_FETCH = 2 | |
73 | } MMUAccessType; | |
74 | ||
568496c0 | 75 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 76 | |
78271684 CF |
77 | /* see tcg-cpu-ops.h */ |
78 | struct TCGCPUOps; | |
e9e51b71 | 79 | |
fb6916dd CF |
80 | /* see accel-cpu.h */ |
81 | struct AccelCPUClass; | |
82 | ||
8b80bd28 PMD |
83 | /* see sysemu-cpu-ops.h */ |
84 | struct SysemuCPUOps; | |
85 | ||
dd83b06a AF |
86 | /** |
87 | * CPUClass: | |
2b8c2754 AF |
88 | * @class_by_name: Callback to map -cpu command line model name to an |
89 | * instantiatable CPU type. | |
94a444b2 | 90 | * @parse_features: Callback to parse command line arguments. |
91b1df8c | 91 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 92 | * @has_work: Callback for checking if there is work to do. |
f3659eee | 93 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee | 94 | * @dump_state: Callback for dumping state. |
997395d3 | 95 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
42f6ed91 JS |
96 | * @set_pc: Callback for setting the Program Counter register. This |
97 | * should have the semantics used by the target architecture when | |
98 | * setting the PC from a source such as an ELF file entry point; | |
99 | * for example on Arm it will also set the Thumb mode bit based | |
100 | * on the least significant bit of the new PC value. | |
101 | * If the target behaviour here is anything other than "set | |
102 | * the PC register to the value passed in" then the target must | |
103 | * also implement the synchronize_from_tb hook. | |
5b50e790 AF |
104 | * @gdb_read_register: Callback for letting GDB read a register. |
105 | * @gdb_write_register: Callback for letting GDB write a register. | |
a0e372f0 | 106 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 107 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
108 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
109 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
110 | * @gdb_arch_name: Optional callback that returns the architecture name known |
111 | * to GDB. The caller must free the returned string with g_free. | |
200bf5b7 AB |
112 | * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the |
113 | * gdb stub. Returns a pointer to the XML contents for the specified XML file | |
114 | * or NULL if the CPU doesn't have a dynamically generated content for it. | |
37b9de46 | 115 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
116 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
117 | * address before attempting to match it against watchpoints. | |
61ad65d0 RH |
118 | * @deprecation_note: If this CPUClass is deprecated, this field provides |
119 | * related information. | |
dd83b06a AF |
120 | * |
121 | * Represents a CPU family or model. | |
122 | */ | |
db1015e9 | 123 | struct CPUClass { |
dd83b06a | 124 | /*< private >*/ |
961f8395 | 125 | DeviceClass parent_class; |
dd83b06a AF |
126 | /*< public >*/ |
127 | ||
2b8c2754 | 128 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 129 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 130 | |
91b1df8c | 131 | int reset_dump_flags; |
8c2e1b00 | 132 | bool (*has_work)(CPUState *cpu); |
f3659eee AF |
133 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
134 | uint8_t *buf, int len, bool is_write); | |
90c84c56 | 135 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
997395d3 | 136 | int64_t (*get_arch_id)(CPUState *cpu); |
f45748f1 | 137 | void (*set_pc)(CPUState *cpu, vaddr value); |
a010bdbe | 138 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
5b50e790 | 139 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
b170fce3 | 140 | |
5b24c641 | 141 | const char *gdb_core_xml_file; |
b3820e6c | 142 | gchar * (*gdb_arch_name)(CPUState *cpu); |
200bf5b7 | 143 | const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); |
37b9de46 PC |
144 | |
145 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
55c3ceef | 146 | |
61ad65d0 | 147 | const char *deprecation_note; |
55c3ceef RH |
148 | /* Keep non-pointer data at the end to minimize holes. */ |
149 | int gdb_num_core_regs; | |
150 | bool gdb_stop_before_watchpoint; | |
fb6916dd | 151 | struct AccelCPUClass *accel_cpu; |
e9e51b71 | 152 | |
8b80bd28 PMD |
153 | /* when system emulation is not available, this pointer is NULL */ |
154 | const struct SysemuCPUOps *sysemu_ops; | |
155 | ||
78271684 | 156 | /* when TCG is not available, this pointer is NULL */ |
11906557 | 157 | const struct TCGCPUOps *tcg_ops; |
cc3f2be6 CF |
158 | |
159 | /* | |
160 | * if not NULL, this is called in order for the CPUClass to initialize | |
161 | * class data that depends on the accelerator, see accel/accel-common.c. | |
162 | */ | |
163 | void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc); | |
db1015e9 | 164 | }; |
dd83b06a | 165 | |
5e140196 RH |
166 | /* |
167 | * Low 16 bits: number of cycles left, used only in icount mode. | |
168 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs | |
169 | * for this CPU and return to its top level loop (even in non-icount mode). | |
170 | * This allows a single read-compare-cbranch-write sequence to test | |
171 | * for both decrementer underflow and exceptions. | |
172 | */ | |
173 | typedef union IcountDecr { | |
174 | uint32_t u32; | |
175 | struct { | |
28ecfd7a | 176 | #ifdef HOST_WORDS_BIGENDIAN |
5e140196 RH |
177 | uint16_t high; |
178 | uint16_t low; | |
28ecfd7a | 179 | #else |
5e140196 RH |
180 | uint16_t low; |
181 | uint16_t high; | |
28ecfd7a | 182 | #endif |
5e140196 RH |
183 | } u16; |
184 | } IcountDecr; | |
28ecfd7a | 185 | |
f0c3c505 AF |
186 | typedef struct CPUBreakpoint { |
187 | vaddr pc; | |
188 | int flags; /* BP_* */ | |
189 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
190 | } CPUBreakpoint; | |
191 | ||
568496c0 | 192 | struct CPUWatchpoint { |
ff4700b0 | 193 | vaddr vaddr; |
05068c0d | 194 | vaddr len; |
08225676 | 195 | vaddr hitaddr; |
66b9b43c | 196 | MemTxAttrs hitattrs; |
ff4700b0 AF |
197 | int flags; /* BP_* */ |
198 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 199 | }; |
ff4700b0 | 200 | |
2f3a57ee AB |
201 | #ifdef CONFIG_PLUGIN |
202 | /* | |
203 | * For plugins we sometime need to save the resolved iotlb data before | |
204 | * the memory regions get moved around by io_writex. | |
205 | */ | |
206 | typedef struct SavedIOTLB { | |
207 | hwaddr addr; | |
208 | MemoryRegionSection *section; | |
209 | hwaddr mr_offset; | |
210 | } SavedIOTLB; | |
211 | #endif | |
212 | ||
a60f24b5 | 213 | struct KVMState; |
f7575c96 | 214 | struct kvm_run; |
a60f24b5 | 215 | |
b0cb0a66 | 216 | struct hax_vcpu_state; |
b533450e | 217 | struct hvf_vcpu_state; |
b0cb0a66 | 218 | |
8cd70437 AF |
219 | #define TB_JMP_CACHE_BITS 12 |
220 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
221 | ||
4b4629d9 | 222 | /* work queue */ |
14e6fe12 PB |
223 | |
224 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
225 | * hosts in a single parameter | |
226 | */ | |
227 | typedef union { | |
228 | int host_int; | |
229 | unsigned long host_ulong; | |
230 | void *host_ptr; | |
231 | vaddr target_ptr; | |
232 | } run_on_cpu_data; | |
233 | ||
234 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
235 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
236 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
237 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
238 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
239 | ||
240 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
241 | ||
d148d90e | 242 | struct qemu_work_item; |
4b4629d9 | 243 | |
0b8497f0 | 244 | #define CPU_UNSET_NUMA_NODE_ID -1 |
d01c05c9 | 245 | #define CPU_TRACE_DSTATE_MAX_EVENTS 32 |
0b8497f0 | 246 | |
dd83b06a AF |
247 | /** |
248 | * CPUState: | |
55e5c285 | 249 | * @cpu_index: CPU index (informative). |
7ea7b9ad PM |
250 | * @cluster_index: Identifies which cluster this CPU is in. |
251 | * For boards which don't define clusters or for "loose" CPUs not assigned | |
252 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will | |
253 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER | |
254 | * QOM parent. | |
6cc9d67c | 255 | * @tcg_cflags: Pre-computed cflags for this cpu. |
ce3960eb AF |
256 | * @nr_cores: Number of cores within this CPU package. |
257 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
258 | * @running: #true if CPU is currently running (lockless). |
259 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 260 | * valid under cpu_list_lock. |
61a46217 | 261 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
262 | * @interrupt_request: Indicates a pending interrupt request. |
263 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 264 | * @stop: Indicates a pending stop request. |
f324e766 | 265 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 266 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 267 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 268 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 269 | * @icount_extra: Instructions until next timer event. |
414b15c9 PB |
270 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
271 | * requires that IO only be performed on the last instruction of a TB | |
272 | * so that interrupts take effect immediately. | |
32857f4d PM |
273 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
274 | * AddressSpaces this CPU has) | |
12ebc9a7 | 275 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
276 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
277 | * only have a single AddressSpace | |
c05efcb1 | 278 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
5e140196 | 279 | * @icount_decr_ptr: Pointer to IcountDecr field within subclass. |
eac8b355 | 280 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 281 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 282 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 283 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 284 | * @opaque: User data. |
93afeade | 285 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
8737c51c | 286 | * @kvm_fd: vCPU file descriptor for KVM. |
0c0fcc20 EC |
287 | * @work_mutex: Lock to prevent multiple access to @work_list. |
288 | * @work_list: List of pending asynchronous work. | |
d4381116 LV |
289 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
290 | * to @trace_dstate). | |
48151859 | 291 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
54cb65d8 | 292 | * @plugin_mask: Plugin event bitmap. Modified only via async work. |
ed860129 PM |
293 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
294 | * flag of the same name: allows the board to suppress calling of the | |
295 | * CPU do_transaction_failed hook function. | |
b4420f19 PX |
296 | * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty |
297 | * ring is enabled. | |
298 | * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU | |
299 | * dirty ring structure. | |
dd83b06a AF |
300 | * |
301 | * State of one CPU core or thread. | |
302 | */ | |
303 | struct CPUState { | |
304 | /*< private >*/ | |
961f8395 | 305 | DeviceState parent_obj; |
dd83b06a AF |
306 | /*< public >*/ |
307 | ||
ce3960eb AF |
308 | int nr_cores; |
309 | int nr_threads; | |
310 | ||
814e612e | 311 | struct QemuThread *thread; |
bcba2a72 AF |
312 | #ifdef _WIN32 |
313 | HANDLE hThread; | |
314 | #endif | |
9f09e18a | 315 | int thread_id; |
c265e976 | 316 | bool running, has_waiter; |
f5c121b8 | 317 | struct QemuCond *halt_cond; |
216fc9a4 | 318 | bool thread_kicked; |
61a46217 | 319 | bool created; |
4fdeee7c | 320 | bool stop; |
f324e766 | 321 | bool stopped; |
c1b70158 TJB |
322 | |
323 | /* Should CPU start in powered-off state? */ | |
324 | bool start_powered_off; | |
325 | ||
4c055ab5 | 326 | bool unplug; |
bac05aa9 | 327 | bool crash_occurred; |
e0c38211 | 328 | bool exit_request; |
cfbc3c60 | 329 | bool in_exclusive_context; |
9b990ee5 | 330 | uint32_t cflags_next_tb; |
8d04fb55 | 331 | /* updates protected by BQL */ |
259186a7 | 332 | uint32_t interrupt_request; |
ed2803da | 333 | int singlestep_enabled; |
e4cd9657 | 334 | int64_t icount_budget; |
efee7340 | 335 | int64_t icount_extra; |
9c09a251 | 336 | uint64_t random_seed; |
6f03bef0 | 337 | sigjmp_buf jmp_env; |
bcba2a72 | 338 | |
376692b9 | 339 | QemuMutex work_mutex; |
0c0fcc20 | 340 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
376692b9 | 341 | |
32857f4d | 342 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 343 | int num_ases; |
09daed84 | 344 | AddressSpace *as; |
6731d864 | 345 | MemoryRegion *memory; |
09daed84 | 346 | |
c05efcb1 | 347 | void *env_ptr; /* CPUArchState */ |
5e140196 | 348 | IcountDecr *icount_decr_ptr; |
7d7500d9 | 349 | |
f3ced3c5 | 350 | /* Accessed in parallel; all accesses must be atomic */ |
8349d2ae | 351 | TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
7d7500d9 | 352 | |
eac8b355 | 353 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 354 | int gdb_num_regs; |
35143f01 | 355 | int gdb_num_g_regs; |
bdc44640 | 356 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 357 | |
f0c3c505 | 358 | /* ice debug support */ |
b58deb34 | 359 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
f0c3c505 | 360 | |
b58deb34 | 361 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
ff4700b0 AF |
362 | CPUWatchpoint *watchpoint_hit; |
363 | ||
0429a971 AF |
364 | void *opaque; |
365 | ||
93afeade AF |
366 | /* In order to avoid passing too many arguments to the MMIO helpers, |
367 | * we store some rarely used information in the CPU context. | |
368 | */ | |
369 | uintptr_t mem_io_pc; | |
93afeade | 370 | |
b4420f19 | 371 | /* Only used in KVM */ |
8737c51c | 372 | int kvm_fd; |
a60f24b5 | 373 | struct KVMState *kvm_state; |
f7575c96 | 374 | struct kvm_run *kvm_run; |
b4420f19 PX |
375 | struct kvm_dirty_gfn *kvm_dirty_gfns; |
376 | uint32_t kvm_fetch_index; | |
8737c51c | 377 | |
d01c05c9 | 378 | /* Used for events with 'vcpu' and *without* the 'disabled' properties */ |
d4381116 | 379 | DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); |
d01c05c9 | 380 | DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); |
48151859 | 381 | |
54cb65d8 EC |
382 | DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); |
383 | ||
2f3a57ee | 384 | #ifdef CONFIG_PLUGIN |
54cb65d8 | 385 | GArray *plugin_mem_cbs; |
2f3a57ee AB |
386 | /* saved iotlb data from io_writex */ |
387 | SavedIOTLB saved_iotlb; | |
388 | #endif | |
54cb65d8 | 389 | |
f5df5baf | 390 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e | 391 | int cpu_index; |
7ea7b9ad | 392 | int cluster_index; |
6cc9d67c | 393 | uint32_t tcg_cflags; |
6fda014e | 394 | uint32_t halted; |
99df7dce | 395 | uint32_t can_do_io; |
6fda014e | 396 | int32_t exception_index; |
7e4fb26d | 397 | |
99f31832 SAGDR |
398 | /* shared by kvm, hax and hvf */ |
399 | bool vcpu_dirty; | |
400 | ||
2adcc85d JH |
401 | /* Used to keep track of an outstanding cpu throttle thread for migration |
402 | * autoconverge | |
403 | */ | |
404 | bool throttle_thread_scheduled; | |
405 | ||
ed860129 PM |
406 | bool ignore_memory_transaction_failures; |
407 | ||
b0cb0a66 | 408 | struct hax_vcpu_state *hax_vcpu; |
e3b9ca81 | 409 | |
b533450e | 410 | struct hvf_vcpu_state *hvf; |
1f871c5e PM |
411 | |
412 | /* track IOMMUs whose translations we've cached in the TCG TLB */ | |
413 | GArray *iommu_notifiers; | |
dd83b06a AF |
414 | }; |
415 | ||
f481ee2d PB |
416 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
417 | extern CPUTailQ cpus; | |
418 | ||
068a5ea0 EC |
419 | #define first_cpu QTAILQ_FIRST_RCU(&cpus) |
420 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) | |
421 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) | |
bdc44640 | 422 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
068a5ea0 | 423 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) |
182735ef | 424 | |
f240eb6f | 425 | extern __thread CPUState *current_cpu; |
4917cf44 | 426 | |
f3ced3c5 EC |
427 | static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) |
428 | { | |
429 | unsigned int i; | |
430 | ||
431 | for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { | |
d73415a3 | 432 | qatomic_set(&cpu->tb_jmp_cache[i], NULL); |
f3ced3c5 EC |
433 | } |
434 | } | |
435 | ||
8d4e9146 FK |
436 | /** |
437 | * qemu_tcg_mttcg_enabled: | |
438 | * Check whether we are running MultiThread TCG or not. | |
439 | * | |
440 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
441 | */ | |
442 | extern bool mttcg_enabled; | |
443 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
444 | ||
444d5590 AF |
445 | /** |
446 | * cpu_paging_enabled: | |
447 | * @cpu: The CPU whose state is to be inspected. | |
448 | * | |
449 | * Returns: %true if paging is enabled, %false otherwise. | |
450 | */ | |
451 | bool cpu_paging_enabled(const CPUState *cpu); | |
452 | ||
a23bbfda AF |
453 | /** |
454 | * cpu_get_memory_mapping: | |
455 | * @cpu: The CPU whose memory mappings are to be obtained. | |
456 | * @list: Where to write the memory mappings to. | |
457 | * @errp: Pointer for reporting an #Error. | |
458 | */ | |
459 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
460 | Error **errp); | |
461 | ||
cfe35d48 PMD |
462 | #if !defined(CONFIG_USER_ONLY) |
463 | ||
c72bf468 JF |
464 | /** |
465 | * cpu_write_elf64_note: | |
466 | * @f: pointer to a function that writes memory to a file | |
467 | * @cpu: The CPU whose memory is to be dumped | |
468 | * @cpuid: ID number of the CPU | |
469 | * @opaque: pointer to the CPUState struct | |
470 | */ | |
471 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
472 | int cpuid, void *opaque); | |
473 | ||
474 | /** | |
475 | * cpu_write_elf64_qemunote: | |
476 | * @f: pointer to a function that writes memory to a file | |
477 | * @cpu: The CPU whose memory is to be dumped | |
478 | * @cpuid: ID number of the CPU | |
479 | * @opaque: pointer to the CPUState struct | |
480 | */ | |
481 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
482 | void *opaque); | |
483 | ||
484 | /** | |
485 | * cpu_write_elf32_note: | |
486 | * @f: pointer to a function that writes memory to a file | |
487 | * @cpu: The CPU whose memory is to be dumped | |
488 | * @cpuid: ID number of the CPU | |
489 | * @opaque: pointer to the CPUState struct | |
490 | */ | |
491 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
492 | int cpuid, void *opaque); | |
493 | ||
494 | /** | |
495 | * cpu_write_elf32_qemunote: | |
496 | * @f: pointer to a function that writes memory to a file | |
497 | * @cpu: The CPU whose memory is to be dumped | |
498 | * @cpuid: ID number of the CPU | |
499 | * @opaque: pointer to the CPUState struct | |
500 | */ | |
501 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
502 | void *opaque); | |
dd83b06a | 503 | |
c86f106b AN |
504 | /** |
505 | * cpu_get_crash_info: | |
506 | * @cpu: The CPU to get crash information for | |
507 | * | |
508 | * Gets the previously saved crash information. | |
509 | * Caller is responsible for freeing the data. | |
510 | */ | |
511 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
512 | ||
cfe35d48 PMD |
513 | #endif /* !CONFIG_USER_ONLY */ |
514 | ||
878096ee AF |
515 | /** |
516 | * CPUDumpFlags: | |
517 | * @CPU_DUMP_CODE: | |
518 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
519 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
520 | */ | |
521 | enum CPUDumpFlags { | |
522 | CPU_DUMP_CODE = 0x00010000, | |
523 | CPU_DUMP_FPU = 0x00020000, | |
524 | CPU_DUMP_CCOP = 0x00040000, | |
525 | }; | |
526 | ||
527 | /** | |
528 | * cpu_dump_state: | |
529 | * @cpu: The CPU whose state is to be dumped. | |
90c84c56 | 530 | * @f: If non-null, dump to this stream, else to current print sink. |
878096ee AF |
531 | * |
532 | * Dumps CPU state. | |
533 | */ | |
90c84c56 | 534 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
878096ee | 535 | |
00b941e5 | 536 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
537 | /** |
538 | * cpu_get_phys_page_attrs_debug: | |
539 | * @cpu: The CPU to obtain the physical page address for. | |
540 | * @addr: The virtual address. | |
541 | * @attrs: Updated on return with the memory transaction attributes to use | |
542 | * for this access. | |
543 | * | |
544 | * Obtains the physical page corresponding to a virtual one, together | |
545 | * with the corresponding memory transaction attributes to use for the access. | |
546 | * Use it only for debugging because no protection checks are done. | |
547 | * | |
548 | * Returns: Corresponding physical page address or -1 if no page found. | |
549 | */ | |
a41d3aae PMD |
550 | hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
551 | MemTxAttrs *attrs); | |
1dc6fb1f | 552 | |
00b941e5 AF |
553 | /** |
554 | * cpu_get_phys_page_debug: | |
555 | * @cpu: The CPU to obtain the physical page address for. | |
556 | * @addr: The virtual address. | |
557 | * | |
558 | * Obtains the physical page corresponding to a virtual one. | |
559 | * Use it only for debugging because no protection checks are done. | |
560 | * | |
561 | * Returns: Corresponding physical page address or -1 if no page found. | |
562 | */ | |
a41d3aae | 563 | hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
d7f25a9e PM |
564 | |
565 | /** cpu_asidx_from_attrs: | |
566 | * @cpu: CPU | |
567 | * @attrs: memory transaction attributes | |
568 | * | |
569 | * Returns the address space index specifying the CPU AddressSpace | |
570 | * to use for a memory access with the given transaction attributes. | |
571 | */ | |
a41d3aae | 572 | int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); |
d7f25a9e | 573 | |
cdba7e2f PMD |
574 | /** |
575 | * cpu_virtio_is_big_endian: | |
576 | * @cpu: CPU | |
577 | ||
578 | * Returns %true if a CPU which supports runtime configurable endianness | |
579 | * is currently big-endian. | |
580 | */ | |
581 | bool cpu_virtio_is_big_endian(CPUState *cpu); | |
cfe35d48 PMD |
582 | |
583 | #endif /* CONFIG_USER_ONLY */ | |
00b941e5 | 584 | |
267f685b PB |
585 | /** |
586 | * cpu_list_add: | |
587 | * @cpu: The CPU to be added to the list of CPUs. | |
588 | */ | |
589 | void cpu_list_add(CPUState *cpu); | |
590 | ||
591 | /** | |
592 | * cpu_list_remove: | |
593 | * @cpu: The CPU to be removed from the list of CPUs. | |
594 | */ | |
595 | void cpu_list_remove(CPUState *cpu); | |
596 | ||
dd83b06a AF |
597 | /** |
598 | * cpu_reset: | |
599 | * @cpu: The CPU whose state is to be reset. | |
600 | */ | |
601 | void cpu_reset(CPUState *cpu); | |
602 | ||
2b8c2754 AF |
603 | /** |
604 | * cpu_class_by_name: | |
605 | * @typename: The CPU base type. | |
606 | * @cpu_model: The model string without any parameters. | |
607 | * | |
608 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
609 | * | |
610 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
611 | */ | |
612 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
613 | ||
3c72234c IM |
614 | /** |
615 | * cpu_create: | |
616 | * @typename: The CPU type. | |
617 | * | |
618 | * Instantiates a CPU and realizes the CPU. | |
619 | * | |
620 | * Returns: A #CPUState or %NULL if an error occurred. | |
621 | */ | |
622 | CPUState *cpu_create(const char *typename); | |
623 | ||
624 | /** | |
c1c8cfe5 EH |
625 | * parse_cpu_option: |
626 | * @cpu_option: The -cpu option including optional parameters. | |
3c72234c IM |
627 | * |
628 | * processes optional parameters and registers them as global properties | |
629 | * | |
4482e05c IM |
630 | * Returns: type of CPU to create or prints error and terminates process |
631 | * if an error occurred. | |
3c72234c | 632 | */ |
c1c8cfe5 | 633 | const char *parse_cpu_option(const char *cpu_option); |
9262685b | 634 | |
3993c6bd | 635 | /** |
8c2e1b00 | 636 | * cpu_has_work: |
3993c6bd AF |
637 | * @cpu: The vCPU to check. |
638 | * | |
639 | * Checks whether the CPU has work to do. | |
640 | * | |
641 | * Returns: %true if the CPU has work, %false otherwise. | |
642 | */ | |
8c2e1b00 AF |
643 | static inline bool cpu_has_work(CPUState *cpu) |
644 | { | |
645 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
646 | ||
647 | g_assert(cc->has_work); | |
648 | return cc->has_work(cpu); | |
649 | } | |
3993c6bd | 650 | |
60e82579 AF |
651 | /** |
652 | * qemu_cpu_is_self: | |
653 | * @cpu: The vCPU to check against. | |
654 | * | |
655 | * Checks whether the caller is executing on the vCPU thread. | |
656 | * | |
657 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
658 | */ | |
659 | bool qemu_cpu_is_self(CPUState *cpu); | |
660 | ||
c08d7424 AF |
661 | /** |
662 | * qemu_cpu_kick: | |
663 | * @cpu: The vCPU to kick. | |
664 | * | |
665 | * Kicks @cpu's thread. | |
666 | */ | |
667 | void qemu_cpu_kick(CPUState *cpu); | |
668 | ||
2fa45344 AF |
669 | /** |
670 | * cpu_is_stopped: | |
671 | * @cpu: The CPU to check. | |
672 | * | |
673 | * Checks whether the CPU is stopped. | |
674 | * | |
675 | * Returns: %true if run state is not running or if artificially stopped; | |
676 | * %false otherwise. | |
677 | */ | |
678 | bool cpu_is_stopped(CPUState *cpu); | |
679 | ||
d148d90e SF |
680 | /** |
681 | * do_run_on_cpu: | |
682 | * @cpu: The vCPU to run on. | |
683 | * @func: The function to be executed. | |
684 | * @data: Data to pass to the function. | |
685 | * @mutex: Mutex to release while waiting for @func to run. | |
686 | * | |
687 | * Used internally in the implementation of run_on_cpu. | |
688 | */ | |
14e6fe12 | 689 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
690 | QemuMutex *mutex); |
691 | ||
f100f0b3 AF |
692 | /** |
693 | * run_on_cpu: | |
694 | * @cpu: The vCPU to run on. | |
695 | * @func: The function to be executed. | |
696 | * @data: Data to pass to the function. | |
697 | * | |
698 | * Schedules the function @func for execution on the vCPU @cpu. | |
699 | */ | |
14e6fe12 | 700 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 701 | |
3c02270d CV |
702 | /** |
703 | * async_run_on_cpu: | |
704 | * @cpu: The vCPU to run on. | |
705 | * @func: The function to be executed. | |
706 | * @data: Data to pass to the function. | |
707 | * | |
708 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
709 | */ | |
14e6fe12 | 710 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 711 | |
53f5ed95 PB |
712 | /** |
713 | * async_safe_run_on_cpu: | |
714 | * @cpu: The vCPU to run on. | |
715 | * @func: The function to be executed. | |
716 | * @data: Data to pass to the function. | |
717 | * | |
718 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
719 | * while all other vCPUs are sleeping. | |
720 | * | |
721 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
722 | * BQL. | |
723 | */ | |
14e6fe12 | 724 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 725 | |
cfbc3c60 EC |
726 | /** |
727 | * cpu_in_exclusive_context() | |
728 | * @cpu: The vCPU to check | |
729 | * | |
730 | * Returns true if @cpu is an exclusive context, for example running | |
731 | * something which has previously been queued via async_safe_run_on_cpu(). | |
732 | */ | |
733 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) | |
734 | { | |
735 | return cpu->in_exclusive_context; | |
736 | } | |
737 | ||
38d8f5c8 AF |
738 | /** |
739 | * qemu_get_cpu: | |
740 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
741 | * | |
742 | * Gets a CPU matching @index. | |
743 | * | |
744 | * Returns: The CPU or %NULL if there is no matching CPU. | |
745 | */ | |
746 | CPUState *qemu_get_cpu(int index); | |
747 | ||
69e5ff06 IM |
748 | /** |
749 | * cpu_exists: | |
750 | * @id: Guest-exposed CPU ID to lookup. | |
751 | * | |
752 | * Search for CPU with specified ID. | |
753 | * | |
754 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
755 | */ | |
756 | bool cpu_exists(int64_t id); | |
757 | ||
5ce46cb3 EH |
758 | /** |
759 | * cpu_by_arch_id: | |
760 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
761 | * | |
762 | * Get a CPU with matching @id. | |
763 | * | |
764 | * Returns: The CPU or %NULL if there is no matching CPU. | |
765 | */ | |
766 | CPUState *cpu_by_arch_id(int64_t id); | |
767 | ||
c3affe56 AF |
768 | /** |
769 | * cpu_interrupt: | |
770 | * @cpu: The CPU to set an interrupt on. | |
7e63bc38 | 771 | * @mask: The interrupts to set. |
c3affe56 AF |
772 | * |
773 | * Invokes the interrupt handler. | |
774 | */ | |
c3affe56 AF |
775 | |
776 | void cpu_interrupt(CPUState *cpu, int mask); | |
777 | ||
2991b890 PC |
778 | /** |
779 | * cpu_set_pc: | |
780 | * @cpu: The CPU to set the program counter for. | |
781 | * @addr: Program counter value. | |
782 | * | |
783 | * Sets the program counter for a CPU. | |
784 | */ | |
785 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
786 | { | |
787 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
788 | ||
789 | cc->set_pc(cpu, addr); | |
790 | } | |
791 | ||
d8ed887b AF |
792 | /** |
793 | * cpu_reset_interrupt: | |
794 | * @cpu: The CPU to clear the interrupt on. | |
795 | * @mask: The interrupt mask to clear. | |
796 | * | |
797 | * Resets interrupts on the vCPU @cpu. | |
798 | */ | |
799 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
800 | ||
60a3e17a AF |
801 | /** |
802 | * cpu_exit: | |
803 | * @cpu: The CPU to exit. | |
804 | * | |
805 | * Requests the CPU @cpu to exit execution. | |
806 | */ | |
807 | void cpu_exit(CPUState *cpu); | |
808 | ||
2993683b IM |
809 | /** |
810 | * cpu_resume: | |
811 | * @cpu: The CPU to resume. | |
812 | * | |
813 | * Resumes CPU, i.e. puts CPU into runnable state. | |
814 | */ | |
815 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 816 | |
4c055ab5 | 817 | /** |
2c579042 BR |
818 | * cpu_remove_sync: |
819 | * @cpu: The CPU to remove. | |
820 | * | |
821 | * Requests the CPU to be removed and waits till it is removed. | |
822 | */ | |
823 | void cpu_remove_sync(CPUState *cpu); | |
824 | ||
d148d90e SF |
825 | /** |
826 | * process_queued_cpu_work() - process all items on CPU work queue | |
827 | * @cpu: The CPU which work queue to process. | |
828 | */ | |
829 | void process_queued_cpu_work(CPUState *cpu); | |
830 | ||
ab129972 PB |
831 | /** |
832 | * cpu_exec_start: | |
833 | * @cpu: The CPU for the current thread. | |
834 | * | |
835 | * Record that a CPU has started execution and can be interrupted with | |
836 | * cpu_exit. | |
837 | */ | |
838 | void cpu_exec_start(CPUState *cpu); | |
839 | ||
840 | /** | |
841 | * cpu_exec_end: | |
842 | * @cpu: The CPU for the current thread. | |
843 | * | |
844 | * Record that a CPU has stopped execution and exclusive sections | |
845 | * can be executed without interrupting it. | |
846 | */ | |
847 | void cpu_exec_end(CPUState *cpu); | |
848 | ||
849 | /** | |
850 | * start_exclusive: | |
851 | * | |
852 | * Wait for a concurrent exclusive section to end, and then start | |
853 | * a section of work that is run while other CPUs are not running | |
854 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
855 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
856 | * during the exclusive section go to sleep until this CPU calls | |
857 | * end_exclusive. | |
ab129972 PB |
858 | */ |
859 | void start_exclusive(void); | |
860 | ||
861 | /** | |
862 | * end_exclusive: | |
863 | * | |
864 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
865 | */ |
866 | void end_exclusive(void); | |
867 | ||
c643bed9 AF |
868 | /** |
869 | * qemu_init_vcpu: | |
870 | * @cpu: The vCPU to initialize. | |
871 | * | |
872 | * Initializes a vCPU. | |
873 | */ | |
874 | void qemu_init_vcpu(CPUState *cpu); | |
875 | ||
3825b28f AF |
876 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
877 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
878 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
879 | ||
880 | /** | |
881 | * cpu_single_step: | |
882 | * @cpu: CPU to the flags for. | |
883 | * @enabled: Flags to enable. | |
884 | * | |
885 | * Enables or disables single-stepping for @cpu. | |
886 | */ | |
887 | void cpu_single_step(CPUState *cpu, int enabled); | |
888 | ||
b3310ab3 AF |
889 | /* Breakpoint/watchpoint flags */ |
890 | #define BP_MEM_READ 0x01 | |
891 | #define BP_MEM_WRITE 0x02 | |
892 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
893 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 894 | /* 0x08 currently unused */ |
b3310ab3 AF |
895 | #define BP_GDB 0x10 |
896 | #define BP_CPU 0x20 | |
b933066a | 897 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
898 | #define BP_WATCHPOINT_HIT_READ 0x40 |
899 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
900 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
901 | |
902 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
903 | CPUBreakpoint **breakpoint); | |
904 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
905 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
906 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
907 | ||
b933066a RH |
908 | /* Return true if PC matches an installed breakpoint. */ |
909 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
910 | { | |
911 | CPUBreakpoint *bp; | |
912 | ||
913 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
914 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
915 | if (bp->pc == pc && (bp->flags & mask)) { | |
916 | return true; | |
917 | } | |
918 | } | |
919 | } | |
920 | return false; | |
921 | } | |
922 | ||
74841f04 RH |
923 | #ifdef CONFIG_USER_ONLY |
924 | static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
925 | int flags, CPUWatchpoint **watchpoint) | |
926 | { | |
927 | return -ENOSYS; | |
928 | } | |
929 | ||
930 | static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
931 | vaddr len, int flags) | |
932 | { | |
933 | return -ENOSYS; | |
934 | } | |
935 | ||
936 | static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, | |
937 | CPUWatchpoint *wp) | |
938 | { | |
939 | } | |
940 | ||
941 | static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
942 | { | |
943 | } | |
0026348b DH |
944 | |
945 | static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, | |
946 | MemTxAttrs atr, int fl, uintptr_t ra) | |
947 | { | |
948 | } | |
56ad8b00 RH |
949 | |
950 | static inline int cpu_watchpoint_address_matches(CPUState *cpu, | |
951 | vaddr addr, vaddr len) | |
952 | { | |
953 | return 0; | |
954 | } | |
74841f04 | 955 | #else |
75a34036 AF |
956 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
957 | int flags, CPUWatchpoint **watchpoint); | |
958 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
959 | vaddr len, int flags); | |
960 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
961 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
390734a4 RH |
962 | |
963 | /** | |
964 | * cpu_check_watchpoint: | |
965 | * @cpu: cpu context | |
966 | * @addr: guest virtual address | |
967 | * @len: access length | |
968 | * @attrs: memory access attributes | |
969 | * @flags: watchpoint access type | |
970 | * @ra: unwind return address | |
971 | * | |
972 | * Check for a watchpoint hit in [addr, addr+len) of the type | |
973 | * specified by @flags. Exit via exception with a hit. | |
974 | */ | |
0026348b DH |
975 | void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, |
976 | MemTxAttrs attrs, int flags, uintptr_t ra); | |
390734a4 RH |
977 | |
978 | /** | |
979 | * cpu_watchpoint_address_matches: | |
980 | * @cpu: cpu context | |
981 | * @addr: guest virtual address | |
982 | * @len: access length | |
983 | * | |
984 | * Return the watchpoint flags that apply to [addr, addr+len). | |
985 | * If no watchpoint is registered for the range, the result is 0. | |
986 | */ | |
56ad8b00 | 987 | int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); |
74841f04 | 988 | #endif |
75a34036 | 989 | |
63c91552 PB |
990 | /** |
991 | * cpu_get_address_space: | |
992 | * @cpu: CPU to get address space from | |
993 | * @asidx: index identifying which address space to get | |
994 | * | |
995 | * Return the requested address space of this CPU. @asidx | |
996 | * specifies which address space to read. | |
997 | */ | |
998 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
999 | ||
a47dddd7 AF |
1000 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
1001 | GCC_FMT_ATTR(2, 3); | |
7df5e3d6 CF |
1002 | |
1003 | /* $(top_srcdir)/cpu.c */ | |
39e329e3 | 1004 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 1005 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 1006 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1007 | |
c95ac103 TH |
1008 | /** |
1009 | * target_words_bigendian: | |
1010 | * Returns true if the (default) endianness of the target is big endian, | |
1011 | * false otherwise. Note that in target-specific code, you can use | |
1012 | * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common | |
1013 | * code should normally never need to know about the endianness of the | |
1014 | * target, so please do *not* use this function unless you know very well | |
1015 | * what you are doing! | |
1016 | */ | |
1017 | bool target_words_bigendian(void); | |
1018 | ||
47507383 TH |
1019 | #ifdef NEED_CPU_H |
1020 | ||
1a1562f5 | 1021 | #ifdef CONFIG_SOFTMMU |
feece4d0 | 1022 | |
8a9358cc | 1023 | extern const VMStateDescription vmstate_cpu_common; |
1a1562f5 AF |
1024 | |
1025 | #define VMSTATE_CPU() { \ | |
1026 | .name = "parent_obj", \ | |
1027 | .size = sizeof(CPUState), \ | |
1028 | .vmsd = &vmstate_cpu_common, \ | |
1029 | .flags = VMS_STRUCT, \ | |
1030 | .offset = 0, \ | |
1031 | } | |
feece4d0 | 1032 | #endif /* CONFIG_SOFTMMU */ |
1a1562f5 | 1033 | |
47507383 TH |
1034 | #endif /* NEED_CPU_H */ |
1035 | ||
a07f953e | 1036 | #define UNASSIGNED_CPU_INDEX -1 |
7ea7b9ad | 1037 | #define UNASSIGNED_CLUSTER_INDEX -1 |
a07f953e | 1038 | |
dd83b06a | 1039 | #endif |