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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
3979fca4 | 24 | #include "disas/dis-asm.h" |
06445fbd | 25 | #include "exec/cpu-common.h" |
c658b94f | 26 | #include "exec/hwaddr.h" |
66b9b43c | 27 | #include "exec/memattrs.h" |
9af23989 | 28 | #include "qapi/qapi-types-run-state.h" |
48151859 | 29 | #include "qemu/bitmap.h" |
068a5ea0 | 30 | #include "qemu/rcu_queue.h" |
bdc44640 | 31 | #include "qemu/queue.h" |
1de7afc9 | 32 | #include "qemu/thread.h" |
aa4cf6eb | 33 | #include "qemu/plugin-event.h" |
db1015e9 | 34 | #include "qom/object.h" |
dd83b06a | 35 | |
b5ba1cc6 QN |
36 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
37 | void *opaque); | |
c72bf468 | 38 | |
dd83b06a AF |
39 | /** |
40 | * SECTION:cpu | |
41 | * @section_id: QEMU-cpu | |
42 | * @title: CPU Class | |
43 | * @short_description: Base class for all CPUs | |
44 | */ | |
45 | ||
46 | #define TYPE_CPU "cpu" | |
47 | ||
0d6d1ab4 AF |
48 | /* Since this macro is used a lot in hot code paths and in conjunction with |
49 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
50 | * an unchecked cast. | |
51 | */ | |
52 | #define CPU(obj) ((CPUState *)(obj)) | |
53 | ||
6fbdff87 AB |
54 | /* |
55 | * The class checkers bring in CPU_GET_CLASS() which is potentially | |
56 | * expensive given the eventual call to | |
57 | * object_class_dynamic_cast_assert(). Because of this the CPUState | |
58 | * has a cached value for the class in cs->cc which is set up in | |
59 | * cpu_exec_realizefn() for use in hot code paths. | |
60 | */ | |
db1015e9 | 61 | typedef struct CPUClass CPUClass; |
8110fa1d EH |
62 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, |
63 | TYPE_CPU) | |
dd83b06a | 64 | |
9295b1aa PMD |
65 | /** |
66 | * OBJECT_DECLARE_CPU_TYPE: | |
67 | * @CpuInstanceType: instance struct name | |
68 | * @CpuClassType: class struct name | |
69 | * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators | |
70 | * | |
71 | * This macro is typically used in "cpu-qom.h" header file, and will: | |
72 | * | |
73 | * - create the typedefs for the CPU object and class structs | |
74 | * - register the type for use with g_autoptr | |
75 | * - provide three standard type cast functions | |
76 | * | |
77 | * The object struct and class struct need to be declared manually. | |
78 | */ | |
79 | #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \ | |
b36e239e PMD |
80 | typedef struct ArchCPU CpuInstanceType; \ |
81 | OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); | |
9295b1aa | 82 | |
b35399bb SS |
83 | typedef enum MMUAccessType { |
84 | MMU_DATA_LOAD = 0, | |
85 | MMU_DATA_STORE = 1, | |
86 | MMU_INST_FETCH = 2 | |
87 | } MMUAccessType; | |
88 | ||
568496c0 | 89 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 90 | |
78271684 CF |
91 | /* see tcg-cpu-ops.h */ |
92 | struct TCGCPUOps; | |
e9e51b71 | 93 | |
fb6916dd CF |
94 | /* see accel-cpu.h */ |
95 | struct AccelCPUClass; | |
96 | ||
8b80bd28 PMD |
97 | /* see sysemu-cpu-ops.h */ |
98 | struct SysemuCPUOps; | |
99 | ||
dd83b06a AF |
100 | /** |
101 | * CPUClass: | |
2b8c2754 AF |
102 | * @class_by_name: Callback to map -cpu command line model name to an |
103 | * instantiatable CPU type. | |
94a444b2 | 104 | * @parse_features: Callback to parse command line arguments. |
91b1df8c | 105 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 106 | * @has_work: Callback for checking if there is work to do. |
f3659eee | 107 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee | 108 | * @dump_state: Callback for dumping state. |
997395d3 | 109 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
42f6ed91 JS |
110 | * @set_pc: Callback for setting the Program Counter register. This |
111 | * should have the semantics used by the target architecture when | |
112 | * setting the PC from a source such as an ELF file entry point; | |
113 | * for example on Arm it will also set the Thumb mode bit based | |
114 | * on the least significant bit of the new PC value. | |
115 | * If the target behaviour here is anything other than "set | |
116 | * the PC register to the value passed in" then the target must | |
117 | * also implement the synchronize_from_tb hook. | |
e4fdf9df RH |
118 | * @get_pc: Callback for getting the Program Counter register. |
119 | * As above, with the semantics of the target architecture. | |
5b50e790 AF |
120 | * @gdb_read_register: Callback for letting GDB read a register. |
121 | * @gdb_write_register: Callback for letting GDB write a register. | |
5bc31e94 RH |
122 | * @gdb_adjust_breakpoint: Callback for adjusting the address of a |
123 | * breakpoint. Used by AVR to handle a gdb mis-feature with | |
124 | * its Harvard architecture split code and data. | |
a0e372f0 | 125 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 126 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
127 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
128 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
129 | * @gdb_arch_name: Optional callback that returns the architecture name known |
130 | * to GDB. The caller must free the returned string with g_free. | |
200bf5b7 AB |
131 | * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the |
132 | * gdb stub. Returns a pointer to the XML contents for the specified XML file | |
133 | * or NULL if the CPU doesn't have a dynamically generated content for it. | |
37b9de46 | 134 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
135 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
136 | * address before attempting to match it against watchpoints. | |
61ad65d0 RH |
137 | * @deprecation_note: If this CPUClass is deprecated, this field provides |
138 | * related information. | |
dd83b06a AF |
139 | * |
140 | * Represents a CPU family or model. | |
141 | */ | |
db1015e9 | 142 | struct CPUClass { |
dd83b06a | 143 | /*< private >*/ |
961f8395 | 144 | DeviceClass parent_class; |
dd83b06a AF |
145 | /*< public >*/ |
146 | ||
2b8c2754 | 147 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 148 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 149 | |
8c2e1b00 | 150 | bool (*has_work)(CPUState *cpu); |
f3659eee AF |
151 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
152 | uint8_t *buf, int len, bool is_write); | |
90c84c56 | 153 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
997395d3 | 154 | int64_t (*get_arch_id)(CPUState *cpu); |
f45748f1 | 155 | void (*set_pc)(CPUState *cpu, vaddr value); |
e4fdf9df | 156 | vaddr (*get_pc)(CPUState *cpu); |
a010bdbe | 157 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
5b50e790 | 158 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
5bc31e94 | 159 | vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); |
b170fce3 | 160 | |
5b24c641 | 161 | const char *gdb_core_xml_file; |
b3820e6c | 162 | gchar * (*gdb_arch_name)(CPUState *cpu); |
200bf5b7 | 163 | const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname); |
37b9de46 PC |
164 | |
165 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
55c3ceef | 166 | |
61ad65d0 | 167 | const char *deprecation_note; |
fb6916dd | 168 | struct AccelCPUClass *accel_cpu; |
e9e51b71 | 169 | |
8b80bd28 PMD |
170 | /* when system emulation is not available, this pointer is NULL */ |
171 | const struct SysemuCPUOps *sysemu_ops; | |
172 | ||
78271684 | 173 | /* when TCG is not available, this pointer is NULL */ |
11906557 | 174 | const struct TCGCPUOps *tcg_ops; |
cc3f2be6 CF |
175 | |
176 | /* | |
177 | * if not NULL, this is called in order for the CPUClass to initialize | |
178 | * class data that depends on the accelerator, see accel/accel-common.c. | |
179 | */ | |
180 | void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc); | |
dc29f474 RH |
181 | |
182 | /* | |
183 | * Keep non-pointer data at the end to minimize holes. | |
184 | */ | |
185 | int reset_dump_flags; | |
186 | int gdb_num_core_regs; | |
187 | bool gdb_stop_before_watchpoint; | |
db1015e9 | 188 | }; |
dd83b06a | 189 | |
5e140196 RH |
190 | /* |
191 | * Low 16 bits: number of cycles left, used only in icount mode. | |
192 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs | |
193 | * for this CPU and return to its top level loop (even in non-icount mode). | |
194 | * This allows a single read-compare-cbranch-write sequence to test | |
195 | * for both decrementer underflow and exceptions. | |
196 | */ | |
197 | typedef union IcountDecr { | |
198 | uint32_t u32; | |
199 | struct { | |
e03b5686 | 200 | #if HOST_BIG_ENDIAN |
5e140196 RH |
201 | uint16_t high; |
202 | uint16_t low; | |
28ecfd7a | 203 | #else |
5e140196 RH |
204 | uint16_t low; |
205 | uint16_t high; | |
28ecfd7a | 206 | #endif |
5e140196 RH |
207 | } u16; |
208 | } IcountDecr; | |
28ecfd7a | 209 | |
f0c3c505 AF |
210 | typedef struct CPUBreakpoint { |
211 | vaddr pc; | |
212 | int flags; /* BP_* */ | |
213 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
214 | } CPUBreakpoint; | |
215 | ||
568496c0 | 216 | struct CPUWatchpoint { |
ff4700b0 | 217 | vaddr vaddr; |
05068c0d | 218 | vaddr len; |
08225676 | 219 | vaddr hitaddr; |
66b9b43c | 220 | MemTxAttrs hitattrs; |
ff4700b0 AF |
221 | int flags; /* BP_* */ |
222 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 223 | }; |
ff4700b0 | 224 | |
2f3a57ee AB |
225 | #ifdef CONFIG_PLUGIN |
226 | /* | |
227 | * For plugins we sometime need to save the resolved iotlb data before | |
228 | * the memory regions get moved around by io_writex. | |
229 | */ | |
230 | typedef struct SavedIOTLB { | |
2f3a57ee AB |
231 | MemoryRegionSection *section; |
232 | hwaddr mr_offset; | |
233 | } SavedIOTLB; | |
234 | #endif | |
235 | ||
a60f24b5 | 236 | struct KVMState; |
f7575c96 | 237 | struct kvm_run; |
a60f24b5 | 238 | |
b0cb0a66 | 239 | struct hax_vcpu_state; |
b533450e | 240 | struct hvf_vcpu_state; |
b0cb0a66 | 241 | |
4b4629d9 | 242 | /* work queue */ |
14e6fe12 PB |
243 | |
244 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
245 | * hosts in a single parameter | |
246 | */ | |
247 | typedef union { | |
248 | int host_int; | |
249 | unsigned long host_ulong; | |
250 | void *host_ptr; | |
251 | vaddr target_ptr; | |
252 | } run_on_cpu_data; | |
253 | ||
254 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
255 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
256 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
257 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
258 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
259 | ||
260 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
261 | ||
d148d90e | 262 | struct qemu_work_item; |
4b4629d9 | 263 | |
0b8497f0 | 264 | #define CPU_UNSET_NUMA_NODE_ID -1 |
d01c05c9 | 265 | #define CPU_TRACE_DSTATE_MAX_EVENTS 32 |
0b8497f0 | 266 | |
dd83b06a AF |
267 | /** |
268 | * CPUState: | |
55e5c285 | 269 | * @cpu_index: CPU index (informative). |
7ea7b9ad PM |
270 | * @cluster_index: Identifies which cluster this CPU is in. |
271 | * For boards which don't define clusters or for "loose" CPUs not assigned | |
272 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will | |
273 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER | |
274 | * QOM parent. | |
a371975e PMD |
275 | * Under TCG this value is propagated to @tcg_cflags. |
276 | * See TranslationBlock::TCG CF_CLUSTER_MASK. | |
6cc9d67c | 277 | * @tcg_cflags: Pre-computed cflags for this cpu. |
ce3960eb AF |
278 | * @nr_cores: Number of cores within this CPU package. |
279 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
280 | * @running: #true if CPU is currently running (lockless). |
281 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 282 | * valid under cpu_list_lock. |
61a46217 | 283 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
284 | * @interrupt_request: Indicates a pending interrupt request. |
285 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 286 | * @stop: Indicates a pending stop request. |
f324e766 | 287 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 288 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 289 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 290 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 291 | * @icount_extra: Instructions until next timer event. |
414b15c9 PB |
292 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
293 | * requires that IO only be performed on the last instruction of a TB | |
294 | * so that interrupts take effect immediately. | |
32857f4d PM |
295 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
296 | * AddressSpaces this CPU has) | |
12ebc9a7 | 297 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
298 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
299 | * only have a single AddressSpace | |
c05efcb1 | 300 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
5e140196 | 301 | * @icount_decr_ptr: Pointer to IcountDecr field within subclass. |
eac8b355 | 302 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 303 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 304 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 305 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 306 | * @opaque: User data. |
93afeade | 307 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
8737c51c | 308 | * @kvm_fd: vCPU file descriptor for KVM. |
0c0fcc20 EC |
309 | * @work_mutex: Lock to prevent multiple access to @work_list. |
310 | * @work_list: List of pending asynchronous work. | |
d4381116 LV |
311 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
312 | * to @trace_dstate). | |
48151859 | 313 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
54cb65d8 | 314 | * @plugin_mask: Plugin event bitmap. Modified only via async work. |
ed860129 PM |
315 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
316 | * flag of the same name: allows the board to suppress calling of the | |
317 | * CPU do_transaction_failed hook function. | |
b4420f19 PX |
318 | * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty |
319 | * ring is enabled. | |
320 | * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU | |
321 | * dirty ring structure. | |
dd83b06a AF |
322 | * |
323 | * State of one CPU core or thread. | |
324 | */ | |
325 | struct CPUState { | |
326 | /*< private >*/ | |
961f8395 | 327 | DeviceState parent_obj; |
6fbdff87 AB |
328 | /* cache to avoid expensive CPU_GET_CLASS */ |
329 | CPUClass *cc; | |
dd83b06a AF |
330 | /*< public >*/ |
331 | ||
ce3960eb AF |
332 | int nr_cores; |
333 | int nr_threads; | |
334 | ||
814e612e | 335 | struct QemuThread *thread; |
bcba2a72 AF |
336 | #ifdef _WIN32 |
337 | HANDLE hThread; | |
c9923550 | 338 | QemuSemaphore sem; |
bcba2a72 | 339 | #endif |
9f09e18a | 340 | int thread_id; |
c265e976 | 341 | bool running, has_waiter; |
f5c121b8 | 342 | struct QemuCond *halt_cond; |
216fc9a4 | 343 | bool thread_kicked; |
61a46217 | 344 | bool created; |
4fdeee7c | 345 | bool stop; |
f324e766 | 346 | bool stopped; |
c1b70158 TJB |
347 | |
348 | /* Should CPU start in powered-off state? */ | |
349 | bool start_powered_off; | |
350 | ||
4c055ab5 | 351 | bool unplug; |
bac05aa9 | 352 | bool crash_occurred; |
e0c38211 | 353 | bool exit_request; |
df8a6880 | 354 | int exclusive_context_count; |
9b990ee5 | 355 | uint32_t cflags_next_tb; |
8d04fb55 | 356 | /* updates protected by BQL */ |
259186a7 | 357 | uint32_t interrupt_request; |
ed2803da | 358 | int singlestep_enabled; |
e4cd9657 | 359 | int64_t icount_budget; |
efee7340 | 360 | int64_t icount_extra; |
9c09a251 | 361 | uint64_t random_seed; |
6f03bef0 | 362 | sigjmp_buf jmp_env; |
bcba2a72 | 363 | |
376692b9 | 364 | QemuMutex work_mutex; |
0c0fcc20 | 365 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
376692b9 | 366 | |
32857f4d | 367 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 368 | int num_ases; |
09daed84 | 369 | AddressSpace *as; |
6731d864 | 370 | MemoryRegion *memory; |
09daed84 | 371 | |
1ea4a06a | 372 | CPUArchState *env_ptr; |
5e140196 | 373 | IcountDecr *icount_decr_ptr; |
7d7500d9 | 374 | |
a976a99a | 375 | CPUJumpCache *tb_jmp_cache; |
7d7500d9 | 376 | |
eac8b355 | 377 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 378 | int gdb_num_regs; |
35143f01 | 379 | int gdb_num_g_regs; |
bdc44640 | 380 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 381 | |
f0c3c505 | 382 | /* ice debug support */ |
b58deb34 | 383 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
f0c3c505 | 384 | |
b58deb34 | 385 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
ff4700b0 AF |
386 | CPUWatchpoint *watchpoint_hit; |
387 | ||
0429a971 AF |
388 | void *opaque; |
389 | ||
93afeade AF |
390 | /* In order to avoid passing too many arguments to the MMIO helpers, |
391 | * we store some rarely used information in the CPU context. | |
392 | */ | |
393 | uintptr_t mem_io_pc; | |
93afeade | 394 | |
b4420f19 | 395 | /* Only used in KVM */ |
8737c51c | 396 | int kvm_fd; |
a60f24b5 | 397 | struct KVMState *kvm_state; |
f7575c96 | 398 | struct kvm_run *kvm_run; |
b4420f19 PX |
399 | struct kvm_dirty_gfn *kvm_dirty_gfns; |
400 | uint32_t kvm_fetch_index; | |
7786ae40 | 401 | uint64_t dirty_pages; |
8737c51c | 402 | |
bd688fc9 EGE |
403 | /* Use by accel-block: CPU is executing an ioctl() */ |
404 | QemuLockCnt in_ioctl_lock; | |
405 | ||
d01c05c9 | 406 | /* Used for events with 'vcpu' and *without* the 'disabled' properties */ |
d4381116 | 407 | DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); |
d01c05c9 | 408 | DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); |
48151859 | 409 | |
54cb65d8 EC |
410 | DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX); |
411 | ||
2f3a57ee | 412 | #ifdef CONFIG_PLUGIN |
54cb65d8 | 413 | GArray *plugin_mem_cbs; |
2f3a57ee AB |
414 | /* saved iotlb data from io_writex */ |
415 | SavedIOTLB saved_iotlb; | |
416 | #endif | |
54cb65d8 | 417 | |
f5df5baf | 418 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e | 419 | int cpu_index; |
7ea7b9ad | 420 | int cluster_index; |
6cc9d67c | 421 | uint32_t tcg_cflags; |
6fda014e | 422 | uint32_t halted; |
99df7dce | 423 | uint32_t can_do_io; |
6fda014e | 424 | int32_t exception_index; |
7e4fb26d | 425 | |
99f31832 SAGDR |
426 | /* shared by kvm, hax and hvf */ |
427 | bool vcpu_dirty; | |
428 | ||
2adcc85d JH |
429 | /* Used to keep track of an outstanding cpu throttle thread for migration |
430 | * autoconverge | |
431 | */ | |
432 | bool throttle_thread_scheduled; | |
433 | ||
baa60983 HH |
434 | /* |
435 | * Sleep throttle_us_per_full microseconds once dirty ring is full | |
436 | * if dirty page rate limit is enabled. | |
437 | */ | |
438 | int64_t throttle_us_per_full; | |
439 | ||
ed860129 PM |
440 | bool ignore_memory_transaction_failures; |
441 | ||
6e8dcacd RH |
442 | /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ |
443 | bool prctl_unalign_sigbus; | |
444 | ||
b0cb0a66 | 445 | struct hax_vcpu_state *hax_vcpu; |
e3b9ca81 | 446 | |
b533450e | 447 | struct hvf_vcpu_state *hvf; |
1f871c5e PM |
448 | |
449 | /* track IOMMUs whose translations we've cached in the TCG TLB */ | |
450 | GArray *iommu_notifiers; | |
dd83b06a AF |
451 | }; |
452 | ||
f481ee2d PB |
453 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
454 | extern CPUTailQ cpus; | |
455 | ||
068a5ea0 EC |
456 | #define first_cpu QTAILQ_FIRST_RCU(&cpus) |
457 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) | |
458 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) | |
bdc44640 | 459 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
068a5ea0 | 460 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) |
182735ef | 461 | |
f240eb6f | 462 | extern __thread CPUState *current_cpu; |
4917cf44 | 463 | |
8d4e9146 FK |
464 | /** |
465 | * qemu_tcg_mttcg_enabled: | |
466 | * Check whether we are running MultiThread TCG or not. | |
467 | * | |
468 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
469 | */ | |
470 | extern bool mttcg_enabled; | |
471 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
472 | ||
444d5590 AF |
473 | /** |
474 | * cpu_paging_enabled: | |
475 | * @cpu: The CPU whose state is to be inspected. | |
476 | * | |
477 | * Returns: %true if paging is enabled, %false otherwise. | |
478 | */ | |
479 | bool cpu_paging_enabled(const CPUState *cpu); | |
480 | ||
a23bbfda AF |
481 | /** |
482 | * cpu_get_memory_mapping: | |
483 | * @cpu: The CPU whose memory mappings are to be obtained. | |
484 | * @list: Where to write the memory mappings to. | |
485 | * @errp: Pointer for reporting an #Error. | |
486 | */ | |
487 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
488 | Error **errp); | |
489 | ||
cfe35d48 PMD |
490 | #if !defined(CONFIG_USER_ONLY) |
491 | ||
c72bf468 JF |
492 | /** |
493 | * cpu_write_elf64_note: | |
494 | * @f: pointer to a function that writes memory to a file | |
495 | * @cpu: The CPU whose memory is to be dumped | |
496 | * @cpuid: ID number of the CPU | |
497 | * @opaque: pointer to the CPUState struct | |
498 | */ | |
499 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
500 | int cpuid, void *opaque); | |
501 | ||
502 | /** | |
503 | * cpu_write_elf64_qemunote: | |
504 | * @f: pointer to a function that writes memory to a file | |
505 | * @cpu: The CPU whose memory is to be dumped | |
506 | * @cpuid: ID number of the CPU | |
507 | * @opaque: pointer to the CPUState struct | |
508 | */ | |
509 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
510 | void *opaque); | |
511 | ||
512 | /** | |
513 | * cpu_write_elf32_note: | |
514 | * @f: pointer to a function that writes memory to a file | |
515 | * @cpu: The CPU whose memory is to be dumped | |
516 | * @cpuid: ID number of the CPU | |
517 | * @opaque: pointer to the CPUState struct | |
518 | */ | |
519 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
520 | int cpuid, void *opaque); | |
521 | ||
522 | /** | |
523 | * cpu_write_elf32_qemunote: | |
524 | * @f: pointer to a function that writes memory to a file | |
525 | * @cpu: The CPU whose memory is to be dumped | |
526 | * @cpuid: ID number of the CPU | |
527 | * @opaque: pointer to the CPUState struct | |
528 | */ | |
529 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
530 | void *opaque); | |
dd83b06a | 531 | |
c86f106b AN |
532 | /** |
533 | * cpu_get_crash_info: | |
534 | * @cpu: The CPU to get crash information for | |
535 | * | |
536 | * Gets the previously saved crash information. | |
537 | * Caller is responsible for freeing the data. | |
538 | */ | |
539 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
540 | ||
cfe35d48 PMD |
541 | #endif /* !CONFIG_USER_ONLY */ |
542 | ||
878096ee AF |
543 | /** |
544 | * CPUDumpFlags: | |
545 | * @CPU_DUMP_CODE: | |
546 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
547 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
548 | */ | |
549 | enum CPUDumpFlags { | |
550 | CPU_DUMP_CODE = 0x00010000, | |
551 | CPU_DUMP_FPU = 0x00020000, | |
552 | CPU_DUMP_CCOP = 0x00040000, | |
553 | }; | |
554 | ||
555 | /** | |
556 | * cpu_dump_state: | |
557 | * @cpu: The CPU whose state is to be dumped. | |
90c84c56 | 558 | * @f: If non-null, dump to this stream, else to current print sink. |
878096ee AF |
559 | * |
560 | * Dumps CPU state. | |
561 | */ | |
90c84c56 | 562 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
878096ee | 563 | |
00b941e5 | 564 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
565 | /** |
566 | * cpu_get_phys_page_attrs_debug: | |
567 | * @cpu: The CPU to obtain the physical page address for. | |
568 | * @addr: The virtual address. | |
569 | * @attrs: Updated on return with the memory transaction attributes to use | |
570 | * for this access. | |
571 | * | |
572 | * Obtains the physical page corresponding to a virtual one, together | |
573 | * with the corresponding memory transaction attributes to use for the access. | |
574 | * Use it only for debugging because no protection checks are done. | |
575 | * | |
576 | * Returns: Corresponding physical page address or -1 if no page found. | |
577 | */ | |
a41d3aae PMD |
578 | hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
579 | MemTxAttrs *attrs); | |
1dc6fb1f | 580 | |
00b941e5 AF |
581 | /** |
582 | * cpu_get_phys_page_debug: | |
583 | * @cpu: The CPU to obtain the physical page address for. | |
584 | * @addr: The virtual address. | |
585 | * | |
586 | * Obtains the physical page corresponding to a virtual one. | |
587 | * Use it only for debugging because no protection checks are done. | |
588 | * | |
589 | * Returns: Corresponding physical page address or -1 if no page found. | |
590 | */ | |
a41d3aae | 591 | hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
d7f25a9e PM |
592 | |
593 | /** cpu_asidx_from_attrs: | |
594 | * @cpu: CPU | |
595 | * @attrs: memory transaction attributes | |
596 | * | |
597 | * Returns the address space index specifying the CPU AddressSpace | |
598 | * to use for a memory access with the given transaction attributes. | |
599 | */ | |
a41d3aae | 600 | int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); |
d7f25a9e | 601 | |
cdba7e2f PMD |
602 | /** |
603 | * cpu_virtio_is_big_endian: | |
604 | * @cpu: CPU | |
605 | ||
606 | * Returns %true if a CPU which supports runtime configurable endianness | |
607 | * is currently big-endian. | |
608 | */ | |
609 | bool cpu_virtio_is_big_endian(CPUState *cpu); | |
cfe35d48 PMD |
610 | |
611 | #endif /* CONFIG_USER_ONLY */ | |
00b941e5 | 612 | |
267f685b PB |
613 | /** |
614 | * cpu_list_add: | |
615 | * @cpu: The CPU to be added to the list of CPUs. | |
616 | */ | |
617 | void cpu_list_add(CPUState *cpu); | |
618 | ||
619 | /** | |
620 | * cpu_list_remove: | |
621 | * @cpu: The CPU to be removed from the list of CPUs. | |
622 | */ | |
623 | void cpu_list_remove(CPUState *cpu); | |
624 | ||
dd83b06a AF |
625 | /** |
626 | * cpu_reset: | |
627 | * @cpu: The CPU whose state is to be reset. | |
628 | */ | |
629 | void cpu_reset(CPUState *cpu); | |
630 | ||
2b8c2754 AF |
631 | /** |
632 | * cpu_class_by_name: | |
633 | * @typename: The CPU base type. | |
634 | * @cpu_model: The model string without any parameters. | |
635 | * | |
636 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
637 | * | |
638 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
639 | */ | |
640 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
641 | ||
3c72234c IM |
642 | /** |
643 | * cpu_create: | |
644 | * @typename: The CPU type. | |
645 | * | |
646 | * Instantiates a CPU and realizes the CPU. | |
647 | * | |
648 | * Returns: A #CPUState or %NULL if an error occurred. | |
649 | */ | |
650 | CPUState *cpu_create(const char *typename); | |
651 | ||
652 | /** | |
c1c8cfe5 EH |
653 | * parse_cpu_option: |
654 | * @cpu_option: The -cpu option including optional parameters. | |
3c72234c IM |
655 | * |
656 | * processes optional parameters and registers them as global properties | |
657 | * | |
4482e05c IM |
658 | * Returns: type of CPU to create or prints error and terminates process |
659 | * if an error occurred. | |
3c72234c | 660 | */ |
c1c8cfe5 | 661 | const char *parse_cpu_option(const char *cpu_option); |
9262685b | 662 | |
3993c6bd | 663 | /** |
8c2e1b00 | 664 | * cpu_has_work: |
3993c6bd AF |
665 | * @cpu: The vCPU to check. |
666 | * | |
667 | * Checks whether the CPU has work to do. | |
668 | * | |
669 | * Returns: %true if the CPU has work, %false otherwise. | |
670 | */ | |
8c2e1b00 AF |
671 | static inline bool cpu_has_work(CPUState *cpu) |
672 | { | |
673 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
674 | ||
675 | g_assert(cc->has_work); | |
676 | return cc->has_work(cpu); | |
677 | } | |
3993c6bd | 678 | |
60e82579 AF |
679 | /** |
680 | * qemu_cpu_is_self: | |
681 | * @cpu: The vCPU to check against. | |
682 | * | |
683 | * Checks whether the caller is executing on the vCPU thread. | |
684 | * | |
685 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
686 | */ | |
687 | bool qemu_cpu_is_self(CPUState *cpu); | |
688 | ||
c08d7424 AF |
689 | /** |
690 | * qemu_cpu_kick: | |
691 | * @cpu: The vCPU to kick. | |
692 | * | |
693 | * Kicks @cpu's thread. | |
694 | */ | |
695 | void qemu_cpu_kick(CPUState *cpu); | |
696 | ||
2fa45344 AF |
697 | /** |
698 | * cpu_is_stopped: | |
699 | * @cpu: The CPU to check. | |
700 | * | |
701 | * Checks whether the CPU is stopped. | |
702 | * | |
703 | * Returns: %true if run state is not running or if artificially stopped; | |
704 | * %false otherwise. | |
705 | */ | |
706 | bool cpu_is_stopped(CPUState *cpu); | |
707 | ||
d148d90e SF |
708 | /** |
709 | * do_run_on_cpu: | |
710 | * @cpu: The vCPU to run on. | |
711 | * @func: The function to be executed. | |
712 | * @data: Data to pass to the function. | |
713 | * @mutex: Mutex to release while waiting for @func to run. | |
714 | * | |
715 | * Used internally in the implementation of run_on_cpu. | |
716 | */ | |
14e6fe12 | 717 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
718 | QemuMutex *mutex); |
719 | ||
f100f0b3 AF |
720 | /** |
721 | * run_on_cpu: | |
722 | * @cpu: The vCPU to run on. | |
723 | * @func: The function to be executed. | |
724 | * @data: Data to pass to the function. | |
725 | * | |
726 | * Schedules the function @func for execution on the vCPU @cpu. | |
727 | */ | |
14e6fe12 | 728 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 729 | |
3c02270d CV |
730 | /** |
731 | * async_run_on_cpu: | |
732 | * @cpu: The vCPU to run on. | |
733 | * @func: The function to be executed. | |
734 | * @data: Data to pass to the function. | |
735 | * | |
736 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
737 | */ | |
14e6fe12 | 738 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 739 | |
53f5ed95 PB |
740 | /** |
741 | * async_safe_run_on_cpu: | |
742 | * @cpu: The vCPU to run on. | |
743 | * @func: The function to be executed. | |
744 | * @data: Data to pass to the function. | |
745 | * | |
746 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
747 | * while all other vCPUs are sleeping. | |
748 | * | |
749 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
750 | * BQL. | |
751 | */ | |
14e6fe12 | 752 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 753 | |
cfbc3c60 EC |
754 | /** |
755 | * cpu_in_exclusive_context() | |
756 | * @cpu: The vCPU to check | |
757 | * | |
758 | * Returns true if @cpu is an exclusive context, for example running | |
759 | * something which has previously been queued via async_safe_run_on_cpu(). | |
760 | */ | |
761 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) | |
762 | { | |
df8a6880 | 763 | return cpu->exclusive_context_count; |
cfbc3c60 EC |
764 | } |
765 | ||
38d8f5c8 AF |
766 | /** |
767 | * qemu_get_cpu: | |
768 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
769 | * | |
770 | * Gets a CPU matching @index. | |
771 | * | |
772 | * Returns: The CPU or %NULL if there is no matching CPU. | |
773 | */ | |
774 | CPUState *qemu_get_cpu(int index); | |
775 | ||
69e5ff06 IM |
776 | /** |
777 | * cpu_exists: | |
778 | * @id: Guest-exposed CPU ID to lookup. | |
779 | * | |
780 | * Search for CPU with specified ID. | |
781 | * | |
782 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
783 | */ | |
784 | bool cpu_exists(int64_t id); | |
785 | ||
5ce46cb3 EH |
786 | /** |
787 | * cpu_by_arch_id: | |
788 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
789 | * | |
790 | * Get a CPU with matching @id. | |
791 | * | |
792 | * Returns: The CPU or %NULL if there is no matching CPU. | |
793 | */ | |
794 | CPUState *cpu_by_arch_id(int64_t id); | |
795 | ||
c3affe56 AF |
796 | /** |
797 | * cpu_interrupt: | |
798 | * @cpu: The CPU to set an interrupt on. | |
7e63bc38 | 799 | * @mask: The interrupts to set. |
c3affe56 AF |
800 | * |
801 | * Invokes the interrupt handler. | |
802 | */ | |
c3affe56 AF |
803 | |
804 | void cpu_interrupt(CPUState *cpu, int mask); | |
805 | ||
2991b890 PC |
806 | /** |
807 | * cpu_set_pc: | |
808 | * @cpu: The CPU to set the program counter for. | |
809 | * @addr: Program counter value. | |
810 | * | |
811 | * Sets the program counter for a CPU. | |
812 | */ | |
813 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
814 | { | |
815 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
816 | ||
817 | cc->set_pc(cpu, addr); | |
818 | } | |
819 | ||
d8ed887b AF |
820 | /** |
821 | * cpu_reset_interrupt: | |
822 | * @cpu: The CPU to clear the interrupt on. | |
823 | * @mask: The interrupt mask to clear. | |
824 | * | |
825 | * Resets interrupts on the vCPU @cpu. | |
826 | */ | |
827 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
828 | ||
60a3e17a AF |
829 | /** |
830 | * cpu_exit: | |
831 | * @cpu: The CPU to exit. | |
832 | * | |
833 | * Requests the CPU @cpu to exit execution. | |
834 | */ | |
835 | void cpu_exit(CPUState *cpu); | |
836 | ||
2993683b IM |
837 | /** |
838 | * cpu_resume: | |
839 | * @cpu: The CPU to resume. | |
840 | * | |
841 | * Resumes CPU, i.e. puts CPU into runnable state. | |
842 | */ | |
843 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 844 | |
4c055ab5 | 845 | /** |
2c579042 BR |
846 | * cpu_remove_sync: |
847 | * @cpu: The CPU to remove. | |
848 | * | |
849 | * Requests the CPU to be removed and waits till it is removed. | |
850 | */ | |
851 | void cpu_remove_sync(CPUState *cpu); | |
852 | ||
d148d90e SF |
853 | /** |
854 | * process_queued_cpu_work() - process all items on CPU work queue | |
855 | * @cpu: The CPU which work queue to process. | |
856 | */ | |
857 | void process_queued_cpu_work(CPUState *cpu); | |
858 | ||
ab129972 PB |
859 | /** |
860 | * cpu_exec_start: | |
861 | * @cpu: The CPU for the current thread. | |
862 | * | |
863 | * Record that a CPU has started execution and can be interrupted with | |
864 | * cpu_exit. | |
865 | */ | |
866 | void cpu_exec_start(CPUState *cpu); | |
867 | ||
868 | /** | |
869 | * cpu_exec_end: | |
870 | * @cpu: The CPU for the current thread. | |
871 | * | |
872 | * Record that a CPU has stopped execution and exclusive sections | |
873 | * can be executed without interrupting it. | |
874 | */ | |
875 | void cpu_exec_end(CPUState *cpu); | |
876 | ||
877 | /** | |
878 | * start_exclusive: | |
879 | * | |
880 | * Wait for a concurrent exclusive section to end, and then start | |
881 | * a section of work that is run while other CPUs are not running | |
882 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
883 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
884 | * during the exclusive section go to sleep until this CPU calls | |
885 | * end_exclusive. | |
ab129972 PB |
886 | */ |
887 | void start_exclusive(void); | |
888 | ||
889 | /** | |
890 | * end_exclusive: | |
891 | * | |
892 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
893 | */ |
894 | void end_exclusive(void); | |
895 | ||
c643bed9 AF |
896 | /** |
897 | * qemu_init_vcpu: | |
898 | * @cpu: The vCPU to initialize. | |
899 | * | |
900 | * Initializes a vCPU. | |
901 | */ | |
902 | void qemu_init_vcpu(CPUState *cpu); | |
903 | ||
3825b28f AF |
904 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
905 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
906 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
907 | ||
908 | /** | |
909 | * cpu_single_step: | |
910 | * @cpu: CPU to the flags for. | |
911 | * @enabled: Flags to enable. | |
912 | * | |
913 | * Enables or disables single-stepping for @cpu. | |
914 | */ | |
915 | void cpu_single_step(CPUState *cpu, int enabled); | |
916 | ||
b3310ab3 AF |
917 | /* Breakpoint/watchpoint flags */ |
918 | #define BP_MEM_READ 0x01 | |
919 | #define BP_MEM_WRITE 0x02 | |
920 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
921 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 922 | /* 0x08 currently unused */ |
b3310ab3 AF |
923 | #define BP_GDB 0x10 |
924 | #define BP_CPU 0x20 | |
b933066a | 925 | #define BP_ANY (BP_GDB | BP_CPU) |
019a9808 RH |
926 | #define BP_HIT_SHIFT 6 |
927 | #define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) | |
928 | #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) | |
929 | #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) | |
b3310ab3 AF |
930 | |
931 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
932 | CPUBreakpoint **breakpoint); | |
933 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
934 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
935 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
936 | ||
b933066a RH |
937 | /* Return true if PC matches an installed breakpoint. */ |
938 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
939 | { | |
940 | CPUBreakpoint *bp; | |
941 | ||
942 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
943 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
944 | if (bp->pc == pc && (bp->flags & mask)) { | |
945 | return true; | |
946 | } | |
947 | } | |
948 | } | |
949 | return false; | |
950 | } | |
951 | ||
87e303de | 952 | #if defined(CONFIG_USER_ONLY) |
74841f04 RH |
953 | static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
954 | int flags, CPUWatchpoint **watchpoint) | |
955 | { | |
956 | return -ENOSYS; | |
957 | } | |
958 | ||
959 | static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
960 | vaddr len, int flags) | |
961 | { | |
962 | return -ENOSYS; | |
963 | } | |
964 | ||
965 | static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, | |
966 | CPUWatchpoint *wp) | |
967 | { | |
968 | } | |
969 | ||
970 | static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
971 | { | |
972 | } | |
973 | #else | |
75a34036 AF |
974 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
975 | int flags, CPUWatchpoint **watchpoint); | |
976 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
977 | vaddr len, int flags); | |
978 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
979 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
74841f04 | 980 | #endif |
75a34036 | 981 | |
63c91552 PB |
982 | /** |
983 | * cpu_get_address_space: | |
984 | * @cpu: CPU to get address space from | |
985 | * @asidx: index identifying which address space to get | |
986 | * | |
987 | * Return the requested address space of this CPU. @asidx | |
988 | * specifies which address space to read. | |
989 | */ | |
990 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
991 | ||
8905770b | 992 | G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) |
9edc6313 | 993 | G_GNUC_PRINTF(2, 3); |
7df5e3d6 CF |
994 | |
995 | /* $(top_srcdir)/cpu.c */ | |
995b87de | 996 | void cpu_class_init_props(DeviceClass *dc); |
39e329e3 | 997 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 998 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 999 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1000 | |
c95ac103 TH |
1001 | /** |
1002 | * target_words_bigendian: | |
1003 | * Returns true if the (default) endianness of the target is big endian, | |
1004 | * false otherwise. Note that in target-specific code, you can use | |
ee3eb3a7 | 1005 | * TARGET_BIG_ENDIAN directly instead. On the other hand, common |
c95ac103 TH |
1006 | * code should normally never need to know about the endianness of the |
1007 | * target, so please do *not* use this function unless you know very well | |
1008 | * what you are doing! | |
1009 | */ | |
1010 | bool target_words_bigendian(void); | |
1011 | ||
4e40e893 MAL |
1012 | void page_size_init(void); |
1013 | ||
47507383 TH |
1014 | #ifdef NEED_CPU_H |
1015 | ||
1a1562f5 | 1016 | #ifdef CONFIG_SOFTMMU |
feece4d0 | 1017 | |
8a9358cc | 1018 | extern const VMStateDescription vmstate_cpu_common; |
1a1562f5 AF |
1019 | |
1020 | #define VMSTATE_CPU() { \ | |
1021 | .name = "parent_obj", \ | |
1022 | .size = sizeof(CPUState), \ | |
1023 | .vmsd = &vmstate_cpu_common, \ | |
1024 | .flags = VMS_STRUCT, \ | |
1025 | .offset = 0, \ | |
1026 | } | |
feece4d0 | 1027 | #endif /* CONFIG_SOFTMMU */ |
1a1562f5 | 1028 | |
47507383 TH |
1029 | #endif /* NEED_CPU_H */ |
1030 | ||
a07f953e | 1031 | #define UNASSIGNED_CPU_INDEX -1 |
7ea7b9ad | 1032 | #define UNASSIGNED_CLUSTER_INDEX -1 |
a07f953e | 1033 | |
dd83b06a | 1034 | #endif |