[mirror_qemu.git] / include / hw / cxl / cxl_events.h

/*
 * QEMU CXL Events
 *
 * Copyright (c) 2022 Intel
 *
 * This work is licensed under the terms of the GNU GPL, version 2. See the
 * COPYING file in the top-level directory.
 */

#ifndef CXL_EVENTS_H
#define CXL_EVENTS_H

#include "qemu/uuid.h"

/*
 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
 *
 * Define these as the bit position for the event status register for ease of
 * setting the status.
 */
typedef enum CXLEventLogType {
    CXL_EVENT_TYPE_INFO          = 0,
    CXL_EVENT_TYPE_WARN          = 1,
    CXL_EVENT_TYPE_FAIL          = 2,
    CXL_EVENT_TYPE_FATAL         = 3,
    CXL_EVENT_TYPE_DYNAMIC_CAP   = 4,
    CXL_EVENT_TYPE_MAX
} CXLEventLogType;

/*
 * Common Event Record Format
 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
 */
#define CXL_EVENT_REC_HDR_RES_LEN 0xf
typedef struct CXLEventRecordHdr {
    QemuUUID id;
    uint8_t length;
    uint8_t flags[3];
    uint16_t handle;
    uint16_t related_handle;
    uint64_t timestamp;
    uint8_t maint_op_class;
    uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
} QEMU_PACKED CXLEventRecordHdr;

#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
typedef struct CXLEventRecordRaw {
    CXLEventRecordHdr hdr;
    uint8_t data[CXL_EVENT_RECORD_DATA_LENGTH];
} QEMU_PACKED CXLEventRecordRaw;
#define CXL_EVENT_RECORD_SIZE (sizeof(CXLEventRecordRaw))

/*
 * Get Event Records output payload
 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
 */
#define CXL_GET_EVENT_FLAG_OVERFLOW     BIT(0)
#define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
typedef struct CXLGetEventPayload {
    uint8_t flags;
    uint8_t reserved1;
    uint16_t overflow_err_count;
    uint64_t first_overflow_timestamp;
    uint64_t last_overflow_timestamp;
    uint16_t record_count;
    uint8_t reserved2[0xa];
    CXLEventRecordRaw records[];
} QEMU_PACKED CXLGetEventPayload;
#define CXL_EVENT_PAYLOAD_HDR_SIZE (sizeof(CXLGetEventPayload))

/*
 * Clear Event Records input payload
 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
 */
typedef struct CXLClearEventPayload {
    uint8_t event_log;      /* CXLEventLogType */
    uint8_t clear_flags;
    uint8_t nr_recs;
    uint8_t reserved[3];
    uint16_t handle[];
} CXLClearEventPayload;

/**
 * Event Interrupt Policy
 *
 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
 */
typedef enum CXLEventIntMode {
    CXL_INT_NONE     = 0x00,
    CXL_INT_MSI_MSIX = 0x01,
    CXL_INT_FW       = 0x02,
    CXL_INT_RES      = 0x03,
} CXLEventIntMode;
#define CXL_EVENT_INT_MODE_MASK 0x3
#define CXL_EVENT_INT_SETTING(vector) ((((uint8_t)vector & 0xf) << 4) | CXL_INT_MSI_MSIX)
typedef struct CXLEventInterruptPolicy {
    uint8_t info_settings;
    uint8_t warn_settings;
    uint8_t failure_settings;
    uint8_t fatal_settings;
    uint8_t dyn_cap_settings;
} QEMU_PACKED CXLEventInterruptPolicy;
/* DCD is optional but other fields are not */
#define CXL_EVENT_INT_SETTING_MIN_LEN 4

/*
 * General Media Event Record
 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
 */
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE  0x10
#define CXL_EVENT_GEN_MED_RES_SIZE      0x2e
typedef struct CXLEventGenMedia {
    CXLEventRecordHdr hdr;
    uint64_t phys_addr;
    uint8_t descriptor;
    uint8_t type;
    uint8_t transaction_type;
    uint16_t validity_flags;
    uint8_t channel;
    uint8_t rank;
    uint8_t device[3];
    uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
    uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
} QEMU_PACKED CXLEventGenMedia;

/*
 * DRAM Event Record
 * CXL Rev 3.0 Section 8.2.9.2.1.2: Table 8-44
 * All fields little endian.
 */
typedef struct CXLEventDram {
    CXLEventRecordHdr hdr;
    uint64_t phys_addr;
    uint8_t descriptor;
    uint8_t type;
    uint8_t transaction_type;
    uint16_t validity_flags;
    uint8_t channel;
    uint8_t rank;
    uint8_t nibble_mask[3];
    uint8_t bank_group;
    uint8_t bank;
    uint8_t row[3];
    uint16_t column;
    uint64_t correction_mask[4];
    uint8_t reserved[0x17];
} QEMU_PACKED CXLEventDram;

#endif /* CXL_EVENTS_H */
Commit	Line	Data
d7b84ddc IW	1	/*
	2	* QEMU CXL Events
	3	*
	4	* Copyright (c) 2022 Intel
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2. See the
	7	* COPYING file in the top-level directory.
	8	*/
	9
	10	#ifndef CXL_EVENTS_H
	11	#define CXL_EVENTS_H
	12
22d7e3be IW	13	#include "qemu/uuid.h"
22d7e3be IW	14
d7b84ddc IW	15	/*
	16	* CXL rev 3.0 section 8.2.9.2.2; Table 8-49
	17	*
	18	* Define these as the bit position for the event status register for ease of
	19	* setting the status.
	20	*/
	21	typedef enum CXLEventLogType {
	22	CXL_EVENT_TYPE_INFO = 0,
	23	CXL_EVENT_TYPE_WARN = 1,
	24	CXL_EVENT_TYPE_FAIL = 2,
	25	CXL_EVENT_TYPE_FATAL = 3,
	26	CXL_EVENT_TYPE_DYNAMIC_CAP = 4,
	27	CXL_EVENT_TYPE_MAX
	28	} CXLEventLogType;
	29
22d7e3be IW	30	/*
	31	* Common Event Record Format
	32	* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
	33	*/
	34	#define CXL_EVENT_REC_HDR_RES_LEN 0xf
	35	typedef struct CXLEventRecordHdr {
	36	QemuUUID id;
	37	uint8_t length;
	38	uint8_t flags[3];
	39	uint16_t handle;
	40	uint16_t related_handle;
	41	uint64_t timestamp;
	42	uint8_t maint_op_class;
	43	uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
	44	} QEMU_PACKED CXLEventRecordHdr;
	45
	46	#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
	47	typedef struct CXLEventRecordRaw {
	48	CXLEventRecordHdr hdr;
	49	uint8_t data[CXL_EVENT_RECORD_DATA_LENGTH];
	50	} QEMU_PACKED CXLEventRecordRaw;
	51	#define CXL_EVENT_RECORD_SIZE (sizeof(CXLEventRecordRaw))
	52
	53	/*
	54	* Get Event Records output payload
	55	* CXL rev 3.0 section 8.2.9.2.2; Table 8-50
	56	*/
	57	#define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
	58	#define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
	59	typedef struct CXLGetEventPayload {
	60	uint8_t flags;
	61	uint8_t reserved1;
	62	uint16_t overflow_err_count;
	63	uint64_t first_overflow_timestamp;
	64	uint64_t last_overflow_timestamp;
	65	uint16_t record_count;
	66	uint8_t reserved2[0xa];
	67	CXLEventRecordRaw records[];
	68	} QEMU_PACKED CXLGetEventPayload;
	69	#define CXL_EVENT_PAYLOAD_HDR_SIZE (sizeof(CXLGetEventPayload))
	70
	71	/*
	72	* Clear Event Records input payload
	73	* CXL rev 3.0 section 8.2.9.2.3; Table 8-51
	74	*/
	75	typedef struct CXLClearEventPayload {
	76	uint8_t event_log; /* CXLEventLogType */
	77	uint8_t clear_flags;
	78	uint8_t nr_recs;
	79	uint8_t reserved[3];
	80	uint16_t handle[];
	81	} CXLClearEventPayload;
	82
6676bb97 IW	83	/**
	84	* Event Interrupt Policy
	85	*
	86	* CXL rev 3.0 section 8.2.9.2.4; Table 8-52
	87	*/
	88	typedef enum CXLEventIntMode {
	89	CXL_INT_NONE = 0x00,
	90	CXL_INT_MSI_MSIX = 0x01,
	91	CXL_INT_FW = 0x02,
	92	CXL_INT_RES = 0x03,
	93	} CXLEventIntMode;
	94	#define CXL_EVENT_INT_MODE_MASK 0x3
	95	#define CXL_EVENT_INT_SETTING(vector) ((((uint8_t)vector & 0xf) << 4) \| CXL_INT_MSI_MSIX)
	96	typedef struct CXLEventInterruptPolicy {
	97	uint8_t info_settings;
	98	uint8_t warn_settings;
	99	uint8_t failure_settings;
	100	uint8_t fatal_settings;
	101	uint8_t dyn_cap_settings;
	102	} QEMU_PACKED CXLEventInterruptPolicy;
	103	/* DCD is optional but other fields are not */
	104	#define CXL_EVENT_INT_SETTING_MIN_LEN 4
	105
ea9b6d64 IW	106	/*
	107	* General Media Event Record
	108	* CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
	109	*/
	110	#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
	111	#define CXL_EVENT_GEN_MED_RES_SIZE 0x2e
	112	typedef struct CXLEventGenMedia {
	113	CXLEventRecordHdr hdr;
	114	uint64_t phys_addr;
	115	uint8_t descriptor;
	116	uint8_t type;
	117	uint8_t transaction_type;
	118	uint16_t validity_flags;
	119	uint8_t channel;
	120	uint8_t rank;
	121	uint8_t device[3];
	122	uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
	123	uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
	124	} QEMU_PACKED CXLEventGenMedia;
	125
b90a324e JC	126	/*
	127	* DRAM Event Record
	128	* CXL Rev 3.0 Section 8.2.9.2.1.2: Table 8-44
	129	* All fields little endian.
	130	*/
	131	typedef struct CXLEventDram {
	132	CXLEventRecordHdr hdr;
	133	uint64_t phys_addr;
	134	uint8_t descriptor;
	135	uint8_t type;
	136	uint8_t transaction_type;
	137	uint16_t validity_flags;
	138	uint8_t channel;
	139	uint8_t rank;
	140	uint8_t nibble_mask[3];
	141	uint8_t bank_group;
	142	uint8_t bank;
	143	uint8_t row[3];
	144	uint16_t column;
	145	uint64_t correction_mask[4];
	146	uint8_t reserved[0x17];
	147	} QEMU_PACKED CXLEventDram;
	148
d7b84ddc	149	#endif /* CXL_EVENTS_H */