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1 | /* |
2 | * ASPEED AST2400 I2C Controller | |
3 | * | |
4 | * Copyright (C) 2016 IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
ec150c7e | 20 | |
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21 | #ifndef ASPEED_I2C_H |
22 | #define ASPEED_I2C_H | |
23 | ||
24 | #include "hw/i2c/i2c.h" | |
ec150c7e | 25 | #include "hw/sysbus.h" |
db1015e9 | 26 | #include "qom/object.h" |
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27 | |
28 | #define TYPE_ASPEED_I2C "aspeed.i2c" | |
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29 | #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" |
30 | #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" | |
51dd4923 | 31 | #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" |
a489d195 | 32 | OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) |
16020011 | 33 | |
51dd4923 | 34 | #define ASPEED_I2C_NR_BUSSES 16 |
6054fc73 | 35 | #define ASPEED_I2C_MAX_POOL_SIZE 0x800 |
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36 | |
37 | struct AspeedI2CState; | |
38 | ||
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39 | #define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus" |
40 | OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS) | |
41 | struct AspeedI2CBus { | |
42 | SysBusDevice parent_obj; | |
43 | ||
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44 | struct AspeedI2CState *controller; |
45 | ||
46 | MemoryRegion mr; | |
47 | ||
48 | I2CBus *bus; | |
49 | uint8_t id; | |
51dd4923 | 50 | qemu_irq irq; |
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51 | |
52 | uint32_t ctrl; | |
53 | uint32_t timing[2]; | |
54 | uint32_t intr_ctrl; | |
55 | uint32_t intr_status; | |
56 | uint32_t cmd; | |
57 | uint32_t buf; | |
6054fc73 | 58 | uint32_t pool_ctrl; |
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59 | uint32_t dma_addr; |
60 | uint32_t dma_len; | |
60261038 | 61 | }; |
16020011 | 62 | |
db1015e9 | 63 | struct AspeedI2CState { |
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64 | SysBusDevice parent_obj; |
65 | ||
66 | MemoryRegion iomem; | |
67 | qemu_irq irq; | |
68 | ||
69 | uint32_t intr_status; | |
aab90b1c | 70 | uint32_t ctrl_global; |
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71 | MemoryRegion pool_iomem; |
72 | uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; | |
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73 | |
74 | AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; | |
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75 | MemoryRegion *dram_mr; |
76 | AddressSpace dram_as; | |
db1015e9 | 77 | }; |
16020011 | 78 | |
f7da1aa8 | 79 | |
db1015e9 | 80 | struct AspeedI2CClass { |
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81 | SysBusDeviceClass parent_class; |
82 | ||
83 | uint8_t num_busses; | |
84 | uint8_t reg_size; | |
85 | uint8_t gap; | |
51dd4923 | 86 | qemu_irq (*bus_get_irq)(AspeedI2CBus *); |
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87 | |
88 | uint64_t pool_size; | |
89 | hwaddr pool_base; | |
90 | uint8_t *(*bus_pool_base)(AspeedI2CBus *); | |
aab90b1c | 91 | bool check_sram; |
545d6bef | 92 | bool has_dma; |
aab90b1c | 93 | |
db1015e9 | 94 | }; |
f7da1aa8 | 95 | |
7a204cbd | 96 | I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); |
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97 | |
98 | #endif /* ASPEED_I2C_H */ |