projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 20d0f9cf JCD |
1 | /* |
| 2 | * i.MX I2C Bus Serial Interface registers definition | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 14 | * for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License along | |
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
| 18 | * | |
| 19 | */ | |
| 20 | ||
| 2a6a4076 MA |
21 | #ifndef IMX_I2C_H |
| 22 | #define IMX_I2C_H | |
| 20d0f9cf | 23 | |
| a9c94277 | 24 | #include "hw/sysbus.h" |
| 20d0f9cf JCD |
25 | |
| 26 | #define TYPE_IMX_I2C "imx.i2c" | |
| 27 | #define IMX_I2C(obj) OBJECT_CHECK(IMXI2CState, (obj), TYPE_IMX_I2C) | |
| 28 | ||
| 29 | #define IMX_I2C_MEM_SIZE 0x14 | |
| 30 | ||
| 31 | /* i.MX I2C memory map */ | |
| 32 | #define IADR_ADDR 0x00 /* address register */ | |
| 33 | #define IFDR_ADDR 0x04 /* frequency divider register */ | |
| 34 | #define I2CR_ADDR 0x08 /* control register */ | |
| 35 | #define I2SR_ADDR 0x0c /* status register */ | |
| 36 | #define I2DR_ADDR 0x10 /* data register */ | |
| 37 | ||
| 38 | #define IADR_MASK 0xFE | |
| 39 | #define IADR_RESET 0 | |
| 40 | ||
| 41 | #define IFDR_MASK 0x3F | |
| 42 | #define IFDR_RESET 0 | |
| 43 | ||
| 44 | #define I2CR_IEN (1 << 7) | |
| 45 | #define I2CR_IIEN (1 << 6) | |
| 46 | #define I2CR_MSTA (1 << 5) | |
| 47 | #define I2CR_MTX (1 << 4) | |
| 48 | #define I2CR_TXAK (1 << 3) | |
| 49 | #define I2CR_RSTA (1 << 2) | |
| 50 | #define I2CR_MASK 0xFC | |
| 51 | #define I2CR_RESET 0 | |
| 52 | ||
| 53 | #define I2SR_ICF (1 << 7) | |
| 54 | #define I2SR_IAAF (1 << 6) | |
| 55 | #define I2SR_IBB (1 << 5) | |
| 56 | #define I2SR_IAL (1 << 4) | |
| 57 | #define I2SR_SRW (1 << 2) | |
| 58 | #define I2SR_IIF (1 << 1) | |
| 59 | #define I2SR_RXAK (1 << 0) | |
| 60 | #define I2SR_MASK 0xE9 | |
| 61 | #define I2SR_RESET 0x81 | |
| 62 | ||
| 63 | #define I2DR_MASK 0xFF | |
| 64 | #define I2DR_RESET 0 | |
| 65 | ||
| 66 | #define ADDR_RESET 0xFF00 | |
| 67 | ||
| 68 | typedef struct IMXI2CState { | |
| 69 | /*< private >*/ | |
| 70 | SysBusDevice parent_obj; | |
| 71 | ||
| 72 | /*< public >*/ | |
| 73 | MemoryRegion iomem; | |
| 74 | I2CBus *bus; | |
| 75 | qemu_irq irq; | |
| 76 | ||
| 77 | uint16_t address; | |
| 78 | ||
| 79 | uint16_t iadr; | |
| 80 | uint16_t ifdr; | |
| 81 | uint16_t i2cr; | |
| 82 | uint16_t i2sr; | |
| 83 | uint16_t i2dr_read; | |
| 84 | uint16_t i2dr_write; | |
| 85 | } IMXI2CState; | |
| 86 | ||
| 2a6a4076 | 87 | #endif /* IMX_I2C_H */ |