]>
Commit | Line | Data |
---|---|---|
1da12ec4 LT |
1 | /* |
2 | * QEMU emulation of an Intel IOMMU (VT-d) | |
3 | * (DMA Remapping device) | |
4 | * | |
5 | * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> | |
6 | * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | ||
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | ||
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef INTEL_IOMMU_H | |
23 | #define INTEL_IOMMU_H | |
24 | #include "hw/qdev.h" | |
25 | #include "sysemu/dma.h" | |
26 | ||
27 | #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" | |
28 | #define INTEL_IOMMU_DEVICE(obj) \ | |
29 | OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) | |
30 | ||
31 | /* DMAR Hardware Unit Definition address (IOMMU unit) */ | |
32 | #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL | |
33 | ||
34 | #define VTD_PCI_BUS_MAX 256 | |
35 | #define VTD_PCI_SLOT_MAX 32 | |
36 | #define VTD_PCI_FUNC_MAX 8 | |
37 | #define VTD_PCI_DEVFN_MAX 256 | |
38 | #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
39 | #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) | |
40 | ||
41 | #define DMAR_REG_SIZE 0x230 | |
42 | #define VTD_HOST_ADDRESS_WIDTH 39 | |
43 | #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1) | |
44 | ||
45 | typedef struct IntelIOMMUState IntelIOMMUState; | |
46 | typedef struct VTDAddressSpace VTDAddressSpace; | |
47 | ||
48 | struct VTDAddressSpace { | |
49 | uint8_t bus_num; | |
50 | uint8_t devfn; | |
51 | AddressSpace as; | |
52 | MemoryRegion iommu; | |
53 | IntelIOMMUState *iommu_state; | |
54 | }; | |
55 | ||
56 | /* The iommu (DMAR) device state struct */ | |
57 | struct IntelIOMMUState { | |
58 | SysBusDevice busdev; | |
59 | MemoryRegion csrmem; | |
60 | uint8_t csr[DMAR_REG_SIZE]; /* register values */ | |
61 | uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ | |
62 | uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ | |
63 | uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ | |
64 | uint32_t version; | |
65 | ||
66 | dma_addr_t root; /* Current root table pointer */ | |
67 | bool root_extended; /* Type of root table (extended or not) */ | |
68 | bool dmar_enabled; /* Set if DMA remapping is enabled */ | |
69 | ||
70 | uint16_t iq_head; /* Current invalidation queue head */ | |
71 | uint16_t iq_tail; /* Current invalidation queue tail */ | |
72 | dma_addr_t iq; /* Current invalidation queue pointer */ | |
73 | uint16_t iq_size; /* IQ Size in number of entries */ | |
74 | bool qi_enabled; /* Set if the QI is enabled */ | |
75 | uint8_t iq_last_desc_type; /* The type of last completed descriptor */ | |
76 | ||
77 | /* The index of the Fault Recording Register to be used next. | |
78 | * Wraps around from N-1 to 0, where N is the number of FRCD_REG. | |
79 | */ | |
80 | uint16_t next_frcd_reg; | |
81 | ||
82 | uint64_t cap; /* The value of capability reg */ | |
83 | uint64_t ecap; /* The value of extended capability reg */ | |
84 | ||
85 | MemoryRegionIOMMUOps iommu_ops; | |
86 | VTDAddressSpace **address_spaces[VTD_PCI_BUS_MAX]; | |
87 | }; | |
88 | ||
89 | #endif |