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1da12ec4 LT |
1 | /* |
2 | * QEMU emulation of an Intel IOMMU (VT-d) | |
3 | * (DMA Remapping device) | |
4 | * | |
5 | * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> | |
6 | * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | ||
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | ||
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef INTEL_IOMMU_H | |
23 | #define INTEL_IOMMU_H | |
24 | #include "hw/qdev.h" | |
25 | #include "sysemu/dma.h" | |
26 | ||
27 | #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" | |
28 | #define INTEL_IOMMU_DEVICE(obj) \ | |
29 | OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) | |
30 | ||
31 | /* DMAR Hardware Unit Definition address (IOMMU unit) */ | |
32 | #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL | |
33 | ||
34 | #define VTD_PCI_BUS_MAX 256 | |
35 | #define VTD_PCI_SLOT_MAX 32 | |
36 | #define VTD_PCI_FUNC_MAX 8 | |
37 | #define VTD_PCI_DEVFN_MAX 256 | |
38 | #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
39 | #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) | |
d92fa2dc LT |
40 | #define VTD_SID_TO_BUS(sid) (((sid) >> 8) && 0xff) |
41 | #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) | |
1da12ec4 LT |
42 | |
43 | #define DMAR_REG_SIZE 0x230 | |
44 | #define VTD_HOST_ADDRESS_WIDTH 39 | |
45 | #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1) | |
46 | ||
d92fa2dc LT |
47 | typedef struct VTDContextEntry VTDContextEntry; |
48 | typedef struct VTDContextCacheEntry VTDContextCacheEntry; | |
1da12ec4 LT |
49 | typedef struct IntelIOMMUState IntelIOMMUState; |
50 | typedef struct VTDAddressSpace VTDAddressSpace; | |
b5a280c0 | 51 | typedef struct VTDIOTLBEntry VTDIOTLBEntry; |
d92fa2dc LT |
52 | |
53 | /* Context-Entry */ | |
54 | struct VTDContextEntry { | |
55 | uint64_t lo; | |
56 | uint64_t hi; | |
57 | }; | |
58 | ||
59 | struct VTDContextCacheEntry { | |
60 | /* The cache entry is obsolete if | |
61 | * context_cache_gen!=IntelIOMMUState.context_cache_gen | |
62 | */ | |
63 | uint32_t context_cache_gen; | |
64 | struct VTDContextEntry context_entry; | |
65 | }; | |
66 | ||
1da12ec4 LT |
67 | struct VTDAddressSpace { |
68 | uint8_t bus_num; | |
69 | uint8_t devfn; | |
70 | AddressSpace as; | |
71 | MemoryRegion iommu; | |
72 | IntelIOMMUState *iommu_state; | |
d92fa2dc | 73 | VTDContextCacheEntry context_cache_entry; |
1da12ec4 LT |
74 | }; |
75 | ||
b5a280c0 LT |
76 | struct VTDIOTLBEntry { |
77 | uint64_t gfn; | |
78 | uint16_t domain_id; | |
79 | uint64_t slpte; | |
80 | bool read_flags; | |
81 | bool write_flags; | |
82 | }; | |
83 | ||
1da12ec4 LT |
84 | /* The iommu (DMAR) device state struct */ |
85 | struct IntelIOMMUState { | |
86 | SysBusDevice busdev; | |
87 | MemoryRegion csrmem; | |
88 | uint8_t csr[DMAR_REG_SIZE]; /* register values */ | |
89 | uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ | |
90 | uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ | |
91 | uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ | |
92 | uint32_t version; | |
93 | ||
94 | dma_addr_t root; /* Current root table pointer */ | |
95 | bool root_extended; /* Type of root table (extended or not) */ | |
96 | bool dmar_enabled; /* Set if DMA remapping is enabled */ | |
97 | ||
98 | uint16_t iq_head; /* Current invalidation queue head */ | |
99 | uint16_t iq_tail; /* Current invalidation queue tail */ | |
100 | dma_addr_t iq; /* Current invalidation queue pointer */ | |
101 | uint16_t iq_size; /* IQ Size in number of entries */ | |
102 | bool qi_enabled; /* Set if the QI is enabled */ | |
103 | uint8_t iq_last_desc_type; /* The type of last completed descriptor */ | |
104 | ||
105 | /* The index of the Fault Recording Register to be used next. | |
106 | * Wraps around from N-1 to 0, where N is the number of FRCD_REG. | |
107 | */ | |
108 | uint16_t next_frcd_reg; | |
109 | ||
110 | uint64_t cap; /* The value of capability reg */ | |
111 | uint64_t ecap; /* The value of extended capability reg */ | |
112 | ||
d92fa2dc | 113 | uint32_t context_cache_gen; /* Should be in [1,MAX] */ |
b5a280c0 | 114 | GHashTable *iotlb; /* IOTLB */ |
d92fa2dc | 115 | |
1da12ec4 LT |
116 | MemoryRegionIOMMUOps iommu_ops; |
117 | VTDAddressSpace **address_spaces[VTD_PCI_BUS_MAX]; | |
118 | }; | |
119 | ||
120 | #endif |