[mirror_qemu.git] / include / hw / i386 / intel_iommu.h

/*
 * QEMU emulation of an Intel IOMMU (VT-d)
 *   (DMA Remapping device)
 *
 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef INTEL_IOMMU_H
#define INTEL_IOMMU_H

#include "hw/i386/x86-iommu.h"
#include "qemu/iova-tree.h"
#include "qom/object.h"

#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)

#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"

/* DMAR Hardware Unit Definition address (IOMMU unit) */
#define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL

#define VTD_PCI_BUS_MAX             256
#define VTD_PCI_SLOT_MAX            32
#define VTD_PCI_FUNC_MAX            8
#define VTD_PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
#define VTD_PCI_FUNC(devfn)         ((devfn) & 0x07)
#define VTD_SID_TO_BUS(sid)         (((sid) >> 8) & 0xff)
#define VTD_SID_TO_DEVFN(sid)       ((sid) & 0xff)

#define DMAR_REG_SIZE               0x230
#define VTD_HOST_AW_39BIT           39
#define VTD_HOST_AW_48BIT           48
#define VTD_HOST_ADDRESS_WIDTH      VTD_HOST_AW_39BIT
#define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)

#define DMAR_REPORT_F_INTR          (1)

#define  VTD_MSI_ADDR_HI_MASK        (0xffffffff00000000ULL)
#define  VTD_MSI_ADDR_HI_SHIFT       (32)
#define  VTD_MSI_ADDR_LO_MASK        (0x00000000ffffffffULL)

typedef struct VTDContextEntry VTDContextEntry;
typedef struct VTDContextCacheEntry VTDContextCacheEntry;
typedef struct VTDAddressSpace VTDAddressSpace;
typedef struct VTDIOTLBEntry VTDIOTLBEntry;
typedef struct VTDBus VTDBus;
typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
typedef struct VTDPASIDEntry VTDPASIDEntry;

/* Context-Entry */
struct VTDContextEntry {
    union {
        struct {
            uint64_t lo;
            uint64_t hi;
        };
        struct {
            uint64_t val[4];
        };
    };
};

struct VTDContextCacheEntry {
    /* The cache entry is obsolete if
     * context_cache_gen!=IntelIOMMUState.context_cache_gen
     */
    uint32_t context_cache_gen;
    struct VTDContextEntry context_entry;
};

/* PASID Directory Entry */
struct VTDPASIDDirEntry {
    uint64_t val;
};

/* PASID Table Entry */
struct VTDPASIDEntry {
    uint64_t val[8];
};

struct VTDAddressSpace {
    PCIBus *bus;
    uint8_t devfn;
    AddressSpace as;
    IOMMUMemoryRegion iommu;
    MemoryRegion root;          /* The root container of the device */
    MemoryRegion nodmar;        /* The alias of shared nodmar MR */
    MemoryRegion iommu_ir;      /* Interrupt region: 0xfeeXXXXX */
    IntelIOMMUState *iommu_state;
    VTDContextCacheEntry context_cache_entry;
    QLIST_ENTRY(VTDAddressSpace) next;
    /* Superset of notifier flags that this address space has */
    IOMMUNotifierFlag notifier_flags;
    IOVATree *iova_tree;          /* Traces mapped IOVA ranges */
};

struct VTDBus {
    PCIBus* bus;		/* A reference to the bus to provide translation for */
    /* A table of VTDAddressSpace objects indexed by devfn */
    VTDAddressSpace *dev_as[];
};

struct VTDIOTLBEntry {
    uint64_t gfn;
    uint16_t domain_id;
    uint64_t slpte;
    uint64_t mask;
    uint8_t access_flags;
};

/* VT-d Source-ID Qualifier types */
enum {
    VTD_SQ_FULL = 0x00,     /* Full SID verification */
    VTD_SQ_IGN_3 = 0x01,    /* Ignore bit 3 */
    VTD_SQ_IGN_2_3 = 0x02,  /* Ignore bits 2 & 3 */
    VTD_SQ_IGN_1_3 = 0x03,  /* Ignore bits 1-3 */
    VTD_SQ_MAX,
};

/* VT-d Source Validation Types */
enum {
    VTD_SVT_NONE = 0x00,    /* No validation */
    VTD_SVT_ALL = 0x01,     /* Do full validation */
    VTD_SVT_BUS = 0x02,     /* Validate bus range */
    VTD_SVT_MAX,
};

/* Interrupt Remapping Table Entry Definition */
union VTD_IR_TableEntry {
    struct {
#ifdef HOST_WORDS_BIGENDIAN
        uint32_t __reserved_1:8;     /* Reserved 1 */
        uint32_t vector:8;           /* Interrupt Vector */
        uint32_t irte_mode:1;        /* IRTE Mode */
        uint32_t __reserved_0:3;     /* Reserved 0 */
        uint32_t __avail:4;          /* Available spaces for software */
        uint32_t delivery_mode:3;    /* Delivery Mode */
        uint32_t trigger_mode:1;     /* Trigger Mode */
        uint32_t redir_hint:1;       /* Redirection Hint */
        uint32_t dest_mode:1;        /* Destination Mode */
        uint32_t fault_disable:1;    /* Fault Processing Disable */
        uint32_t present:1;          /* Whether entry present/available */
#else
        uint32_t present:1;          /* Whether entry present/available */
        uint32_t fault_disable:1;    /* Fault Processing Disable */
        uint32_t dest_mode:1;        /* Destination Mode */
        uint32_t redir_hint:1;       /* Redirection Hint */
        uint32_t trigger_mode:1;     /* Trigger Mode */
        uint32_t delivery_mode:3;    /* Delivery Mode */
        uint32_t __avail:4;          /* Available spaces for software */
        uint32_t __reserved_0:3;     /* Reserved 0 */
        uint32_t irte_mode:1;        /* IRTE Mode */
        uint32_t vector:8;           /* Interrupt Vector */
        uint32_t __reserved_1:8;     /* Reserved 1 */
#endif
        uint32_t dest_id;            /* Destination ID */
        uint16_t source_id;          /* Source-ID */
#ifdef HOST_WORDS_BIGENDIAN
        uint64_t __reserved_2:44;    /* Reserved 2 */
        uint64_t sid_vtype:2;        /* Source-ID Validation Type */
        uint64_t sid_q:2;            /* Source-ID Qualifier */
#else
        uint64_t sid_q:2;            /* Source-ID Qualifier */
        uint64_t sid_vtype:2;        /* Source-ID Validation Type */
        uint64_t __reserved_2:44;    /* Reserved 2 */
#endif
    } QEMU_PACKED irte;
    uint64_t data[2];
};

#define VTD_IR_INT_FORMAT_COMPAT     (0) /* Compatible Interrupt */
#define VTD_IR_INT_FORMAT_REMAP      (1) /* Remappable Interrupt */

/* Programming format for MSI/MSI-X addresses */
union VTD_IR_MSIAddress {
    struct {
#ifdef HOST_WORDS_BIGENDIAN
        uint32_t __head:12;          /* Should always be: 0x0fee */
        uint32_t index_l:15;         /* Interrupt index bit 14-0 */
        uint32_t int_mode:1;         /* Interrupt format */
        uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
        uint32_t index_h:1;          /* Interrupt index bit 15 */
        uint32_t __not_care:2;
#else
        uint32_t __not_care:2;
        uint32_t index_h:1;          /* Interrupt index bit 15 */
        uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
        uint32_t int_mode:1;         /* Interrupt format */
        uint32_t index_l:15;         /* Interrupt index bit 14-0 */
        uint32_t __head:12;          /* Should always be: 0x0fee */
#endif
    } QEMU_PACKED addr;
    uint32_t data;
};

/* When IR is enabled, all MSI/MSI-X data bits should be zero */
#define VTD_IR_MSI_DATA          (0)

/* The iommu (DMAR) device state struct */
struct IntelIOMMUState {
    X86IOMMUState x86_iommu;
    MemoryRegion csrmem;
    MemoryRegion mr_nodmar;
    MemoryRegion mr_ir;
    MemoryRegion mr_sys_alias;
    uint8_t csr[DMAR_REG_SIZE];     /* register values */
    uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
    uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
    uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
    uint32_t version;

    bool caching_mode;              /* RO - is cap CM enabled? */
    bool scalable_mode;             /* RO - is Scalable Mode supported? */
    bool snoop_control;             /* RO - is SNP filed supported? */

    dma_addr_t root;                /* Current root table pointer */
    bool root_scalable;             /* Type of root table (scalable or not) */
    bool dmar_enabled;              /* Set if DMA remapping is enabled */

    uint16_t iq_head;               /* Current invalidation queue head */
    uint16_t iq_tail;               /* Current invalidation queue tail */
    dma_addr_t iq;                  /* Current invalidation queue pointer */
    uint16_t iq_size;               /* IQ Size in number of entries */
    bool iq_dw;                     /* IQ descriptor width 256bit or not */
    bool qi_enabled;                /* Set if the QI is enabled */
    uint8_t iq_last_desc_type;      /* The type of last completed descriptor */

    /* The index of the Fault Recording Register to be used next.
     * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
     */
    uint16_t next_frcd_reg;

    uint64_t cap;                   /* The value of capability reg */
    uint64_t ecap;                  /* The value of extended capability reg */

    uint32_t context_cache_gen;     /* Should be in [1,MAX] */
    GHashTable *iotlb;              /* IOTLB */

    GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
    VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
    /* list of registered notifiers */
    QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;

    /* interrupt remapping */
    bool intr_enabled;              /* Whether guest enabled IR */
    dma_addr_t intr_root;           /* Interrupt remapping table pointer */
    uint32_t intr_size;             /* Number of IR table entries */
    bool intr_eime;                 /* Extended interrupt mode enabled */
    OnOffAuto intr_eim;             /* Toggle for EIM cabability */
    bool buggy_eim;                 /* Force buggy EIM unless eim=off */
    uint8_t aw_bits;                /* Host/IOVA address width (in bits) */
    bool dma_drain;                 /* Whether DMA r/w draining enabled */

    /*
     * Protects IOMMU states in general.  Currently it protects the
     * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
     */
    QemuMutex iommu_lock;
};

/* Find the VTD Address space associated with the given bus pointer,
 * create a new one if none exists
 */
VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);

#endif
Commit	Line	Data
1da12ec4 LT	1	/*
	2	* QEMU emulation of an Intel IOMMU (VT-d)
	3	* (DMA Remapping device)
	4	*
	5	* Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
	6	* Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef INTEL_IOMMU_H
	23	#define INTEL_IOMMU_H
a27bd6c7	24
1c7955c4	25	#include "hw/i386/x86-iommu.h"
63b88968	26	#include "qemu/iova-tree.h"
db1015e9	27	#include "qom/object.h"
1da12ec4 LT	28
1da12ec4 LT	29	#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
8063396b	30	OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
1da12ec4	31
1221a474 AK	32	#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
1221a474 AK	33
1da12ec4 LT	34	/* DMAR Hardware Unit Definition address (IOMMU unit) */
	35	#define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
	36
	37	#define VTD_PCI_BUS_MAX 256
	38	#define VTD_PCI_SLOT_MAX 32
	39	#define VTD_PCI_FUNC_MAX 8
1da12ec4 LT	40	#define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
1da12ec4 LT	41	#define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
1e06f131	42	#define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
d92fa2dc	43	#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
1da12ec4 LT	44
1da12ec4 LT	45	#define DMAR_REG_SIZE 0x230
92e5d85e PS	46	#define VTD_HOST_AW_39BIT 39
	47	#define VTD_HOST_AW_48BIT 48
	48	#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
	49	#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
1da12ec4	50
d46114f9 PX	51	#define DMAR_REPORT_F_INTR (1)
d46114f9 PX	52
651e4cef PX	53	#define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
	54	#define VTD_MSI_ADDR_HI_SHIFT (32)
	55	#define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
	56
d92fa2dc LT	57	typedef struct VTDContextEntry VTDContextEntry;
d92fa2dc LT	58	typedef struct VTDContextCacheEntry VTDContextCacheEntry;
1da12ec4	59	typedef struct VTDAddressSpace VTDAddressSpace;
b5a280c0	60	typedef struct VTDIOTLBEntry VTDIOTLBEntry;
7df953bd	61	typedef struct VTDBus VTDBus;
bc38ee10	62	typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
1f91acee	63	typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
fb43cf73 LY	64	typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
fb43cf73 LY	65	typedef struct VTDPASIDEntry VTDPASIDEntry;
d92fa2dc LT	66
	67	/* Context-Entry */
	68	struct VTDContextEntry {
fb43cf73 LY	69	union {
	70	struct {
	71	uint64_t lo;
	72	uint64_t hi;
	73	};
	74	struct {
	75	uint64_t val[4];
	76	};
	77	};
d92fa2dc LT	78	};
	79
	80	struct VTDContextCacheEntry {
	81	/* The cache entry is obsolete if
	82	* context_cache_gen!=IntelIOMMUState.context_cache_gen
	83	*/
	84	uint32_t context_cache_gen;
	85	struct VTDContextEntry context_entry;
	86	};
	87
fb43cf73 LY	88	/* PASID Directory Entry */
	89	struct VTDPASIDDirEntry {
	90	uint64_t val;
	91	};
	92
	93	/* PASID Table Entry */
	94	struct VTDPASIDEntry {
	95	uint64_t val[8];
	96	};
	97
1da12ec4	98	struct VTDAddressSpace {
7df953bd	99	PCIBus *bus;
1da12ec4 LT	100	uint8_t devfn;
1da12ec4 LT	101	AddressSpace as;
3df9d748	102	IOMMUMemoryRegion iommu;
4b519ef1 PX	103	MemoryRegion root; /* The root container of the device */
4b519ef1 PX	104	MemoryRegion nodmar; /* The alias of shared nodmar MR */
651e4cef	105	MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
1da12ec4	106	IntelIOMMUState *iommu_state;
d92fa2dc	107	VTDContextCacheEntry context_cache_entry;
b4a4ba0d	108	QLIST_ENTRY(VTDAddressSpace) next;
4f8a62a9 PX	109	/* Superset of notifier flags that this address space has */
4f8a62a9 PX	110	IOMMUNotifierFlag notifier_flags;
63b88968	111	IOVATree iova_tree; / Traces mapped IOVA ranges */
1da12ec4 LT	112	};
1da12ec4 LT	113
7df953bd KO	114	struct VTDBus {
7df953bd KO	115	PCIBus* bus; /* A reference to the bus to provide translation for */
f7795e40 PMD	116	/* A table of VTDAddressSpace objects indexed by devfn */
f7795e40 PMD	117	VTDAddressSpace *dev_as[];
7df953bd KO	118	};
7df953bd KO	119
b5a280c0 LT	120	struct VTDIOTLBEntry {
	121	uint64_t gfn;
	122	uint16_t domain_id;
	123	uint64_t slpte;
d66b969b	124	uint64_t mask;
07f7b733	125	uint8_t access_flags;
b5a280c0 LT	126	};
b5a280c0 LT	127
ede9c94a PX	128	/* VT-d Source-ID Qualifier types */
	129	enum {
	130	VTD_SQ_FULL = 0x00, /* Full SID verification */
	131	VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */
	132	VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */
	133	VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */
	134	VTD_SQ_MAX,
	135	};
	136
	137	/* VT-d Source Validation Types */
	138	enum {
	139	VTD_SVT_NONE = 0x00, /* No validation */
	140	VTD_SVT_ALL = 0x01, /* Do full validation */
	141	VTD_SVT_BUS = 0x02, /* Validate bus range */
	142	VTD_SVT_MAX,
	143	};
	144
1f91acee	145	/* Interrupt Remapping Table Entry Definition */
bc38ee10	146	union VTD_IR_TableEntry {
1f91acee PX	147	struct {
1f91acee PX	148	#ifdef HOST_WORDS_BIGENDIAN
1f91acee PX	149	uint32_t __reserved_1:8; /* Reserved 1 */
	150	uint32_t vector:8; /* Interrupt Vector */
	151	uint32_t irte_mode:1; /* IRTE Mode */
	152	uint32_t __reserved_0:3; /* Reserved 0 */
	153	uint32_t __avail:4; /* Available spaces for software */
	154	uint32_t delivery_mode:3; /* Delivery Mode */
	155	uint32_t trigger_mode:1; /* Trigger Mode */
	156	uint32_t redir_hint:1; /* Redirection Hint */
	157	uint32_t dest_mode:1; /* Destination Mode */
	158	uint32_t fault_disable:1; /* Fault Processing Disable */
	159	uint32_t present:1; /* Whether entry present/available */
	160	#else
	161	uint32_t present:1; /* Whether entry present/available */
	162	uint32_t fault_disable:1; /* Fault Processing Disable */
	163	uint32_t dest_mode:1; /* Destination Mode */
	164	uint32_t redir_hint:1; /* Redirection Hint */
	165	uint32_t trigger_mode:1; /* Trigger Mode */
	166	uint32_t delivery_mode:3; /* Delivery Mode */
	167	uint32_t __avail:4; /* Available spaces for software */
	168	uint32_t __reserved_0:3; /* Reserved 0 */
	169	uint32_t irte_mode:1; /* IRTE Mode */
	170	uint32_t vector:8; /* Interrupt Vector */
	171	uint32_t __reserved_1:8; /* Reserved 1 */
1f91acee	172	#endif
1a43713b PX	173	uint32_t dest_id; /* Destination ID */
1a43713b PX	174	uint16_t source_id; /* Source-ID */
1f91acee PX	175	#ifdef HOST_WORDS_BIGENDIAN
	176	uint64_t __reserved_2:44; /* Reserved 2 */
	177	uint64_t sid_vtype:2; /* Source-ID Validation Type */
	178	uint64_t sid_q:2; /* Source-ID Qualifier */
	179	#else
	180	uint64_t sid_q:2; /* Source-ID Qualifier */
	181	uint64_t sid_vtype:2; /* Source-ID Validation Type */
	182	uint64_t __reserved_2:44; /* Reserved 2 */
	183	#endif
bc38ee10	184	} QEMU_PACKED irte;
1f91acee PX	185	uint64_t data[2];
	186	};
	187
	188	#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
	189	#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
	190
	191	/* Programming format for MSI/MSI-X addresses */
	192	union VTD_IR_MSIAddress {
	193	struct {
	194	#ifdef HOST_WORDS_BIGENDIAN
	195	uint32_t __head:12; /* Should always be: 0x0fee */
	196	uint32_t index_l:15; /* Interrupt index bit 14-0 */
	197	uint32_t int_mode:1; /* Interrupt format */
	198	uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
	199	uint32_t index_h:1; /* Interrupt index bit 15 */
	200	uint32_t __not_care:2;
	201	#else
	202	uint32_t __not_care:2;
	203	uint32_t index_h:1; /* Interrupt index bit 15 */
	204	uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
	205	uint32_t int_mode:1; /* Interrupt format */
	206	uint32_t index_l:15; /* Interrupt index bit 14-0 */
	207	uint32_t __head:12; /* Should always be: 0x0fee */
	208	#endif
bc38ee10	209	} QEMU_PACKED addr;
1f91acee PX	210	uint32_t data;
	211	};
	212
	213	/* When IR is enabled, all MSI/MSI-X data bits should be zero */
	214	#define VTD_IR_MSI_DATA (0)
	215
1da12ec4 LT	216	/* The iommu (DMAR) device state struct */
1da12ec4 LT	217	struct IntelIOMMUState {
1c7955c4	218	X86IOMMUState x86_iommu;
1da12ec4	219	MemoryRegion csrmem;
4b519ef1 PX	220	MemoryRegion mr_nodmar;
	221	MemoryRegion mr_ir;
	222	MemoryRegion mr_sys_alias;
1da12ec4 LT	223	uint8_t csr[DMAR_REG_SIZE]; /* register values */
	224	uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
	225	uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
	226	uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
	227	uint32_t version;
	228
4a4f219e YS	229	bool caching_mode; /* RO - is cap CM enabled? */
4a4f219e YS	230	bool scalable_mode; /* RO - is Scalable Mode supported? */
b8ffd7d6	231	bool snoop_control; /* RO - is SNP filed supported? */
3b40f0e5	232
1da12ec4	233	dma_addr_t root; /* Current root table pointer */
fb43cf73	234	bool root_scalable; /* Type of root table (scalable or not) */
1da12ec4 LT	235	bool dmar_enabled; /* Set if DMA remapping is enabled */
	236
	237	uint16_t iq_head; /* Current invalidation queue head */
	238	uint16_t iq_tail; /* Current invalidation queue tail */
	239	dma_addr_t iq; /* Current invalidation queue pointer */
	240	uint16_t iq_size; /* IQ Size in number of entries */
c0c1d351	241	bool iq_dw; /* IQ descriptor width 256bit or not */
1da12ec4 LT	242	bool qi_enabled; /* Set if the QI is enabled */
	243	uint8_t iq_last_desc_type; /* The type of last completed descriptor */
	244
	245	/* The index of the Fault Recording Register to be used next.
	246	* Wraps around from N-1 to 0, where N is the number of FRCD_REG.
	247	*/
	248	uint16_t next_frcd_reg;
	249
	250	uint64_t cap; /* The value of capability reg */
	251	uint64_t ecap; /* The value of extended capability reg */
	252
d92fa2dc	253	uint32_t context_cache_gen; /* Should be in [1,MAX] */
b5a280c0	254	GHashTable iotlb; / IOTLB */
d92fa2dc	255
7df953bd KO	256	GHashTable vtd_as_by_busptr; / VTDBus objects indexed by PCIBus* reference */
7df953bd KO	257	VTDBus vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; / VTDBus objects indexed by bus number */
dd4d607e	258	/* list of registered notifiers */
b4a4ba0d	259	QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
a5861439 PX	260
	261	/* interrupt remapping */
	262	bool intr_enabled; /* Whether guest enabled IR */
	263	dma_addr_t intr_root; /* Interrupt remapping table pointer */
	264	uint32_t intr_size; /* Number of IR table entries */
28589311	265	bool intr_eime; /* Extended interrupt mode enabled */
e6b6af05	266	OnOffAuto intr_eim; /* Toggle for EIM cabability */
fb506e70	267	bool buggy_eim; /* Force buggy EIM unless eim=off */
37f51384	268	uint8_t aw_bits; /* Host/IOVA address width (in bits) */
ccc23bb0	269	bool dma_drain; /* Whether DMA r/w draining enabled */
1d9efa73 PX	270
	271	/*
	272	* Protects IOMMU states in general. Currently it protects the
	273	* per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
	274	*/
	275	QemuMutex iommu_lock;
1da12ec4 LT	276	};
1da12ec4 LT	277
7df953bd KO	278	/* Find the VTD Address space associated with the given bus pointer,
	279	* create a new one if none exists
	280	*/
	281	VTDAddressSpace vtd_find_add_as(IntelIOMMUState s, PCIBus *bus, int devfn);
	282
1da12ec4	283	#endif