[mirror_qemu.git] / include / hw / i386 / intel_iommu.h

/*
 * QEMU emulation of an Intel IOMMU (VT-d)
 *   (DMA Remapping device)
 *
 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef INTEL_IOMMU_H
#define INTEL_IOMMU_H
#include "hw/qdev.h"
#include "sysemu/dma.h"
#include "hw/i386/x86-iommu.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/msi.h"
#include "hw/sysbus.h"

#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
#define INTEL_IOMMU_DEVICE(obj) \
     OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)

/* DMAR Hardware Unit Definition address (IOMMU unit) */
#define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL

#define VTD_PCI_BUS_MAX             256
#define VTD_PCI_SLOT_MAX            32
#define VTD_PCI_FUNC_MAX            8
#define VTD_PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
#define VTD_PCI_FUNC(devfn)         ((devfn) & 0x07)
#define VTD_SID_TO_BUS(sid)         (((sid) >> 8) & 0xff)
#define VTD_SID_TO_DEVFN(sid)       ((sid) & 0xff)

#define DMAR_REG_SIZE               0x230
#define VTD_HOST_ADDRESS_WIDTH      39
#define VTD_HAW_MASK                ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)

#define DMAR_REPORT_F_INTR          (1)

#define  VTD_MSI_ADDR_HI_MASK        (0xffffffff00000000ULL)
#define  VTD_MSI_ADDR_HI_SHIFT       (32)
#define  VTD_MSI_ADDR_LO_MASK        (0x00000000ffffffffULL)

typedef struct VTDContextEntry VTDContextEntry;
typedef struct VTDContextCacheEntry VTDContextCacheEntry;
typedef struct IntelIOMMUState IntelIOMMUState;
typedef struct VTDAddressSpace VTDAddressSpace;
typedef struct VTDIOTLBEntry VTDIOTLBEntry;
typedef struct VTDBus VTDBus;
typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
typedef struct VTDIrq VTDIrq;
typedef struct VTD_MSIMessage VTD_MSIMessage;

/* Context-Entry */
struct VTDContextEntry {
    uint64_t lo;
    uint64_t hi;
};

struct VTDContextCacheEntry {
    /* The cache entry is obsolete if
     * context_cache_gen!=IntelIOMMUState.context_cache_gen
     */
    uint32_t context_cache_gen;
    struct VTDContextEntry context_entry;
};

struct VTDAddressSpace {
    PCIBus *bus;
    uint8_t devfn;
    AddressSpace as;
    MemoryRegion iommu;
    MemoryRegion iommu_ir;      /* Interrupt region: 0xfeeXXXXX */
    IntelIOMMUState *iommu_state;
    VTDContextCacheEntry context_cache_entry;
};

struct VTDBus {
    PCIBus* bus;		/* A reference to the bus to provide translation for */
    VTDAddressSpace *dev_as[0];	/* A table of VTDAddressSpace objects indexed by devfn */
};

struct VTDIOTLBEntry {
    uint64_t gfn;
    uint16_t domain_id;
    uint64_t slpte;
    uint64_t mask;
    bool read_flags;
    bool write_flags;
};

/* VT-d Source-ID Qualifier types */
enum {
    VTD_SQ_FULL = 0x00,     /* Full SID verification */
    VTD_SQ_IGN_3 = 0x01,    /* Ignore bit 3 */
    VTD_SQ_IGN_2_3 = 0x02,  /* Ignore bits 2 & 3 */
    VTD_SQ_IGN_1_3 = 0x03,  /* Ignore bits 1-3 */
    VTD_SQ_MAX,
};

/* VT-d Source Validation Types */
enum {
    VTD_SVT_NONE = 0x00,    /* No validation */
    VTD_SVT_ALL = 0x01,     /* Do full validation */
    VTD_SVT_BUS = 0x02,     /* Validate bus range */
    VTD_SVT_MAX,
};

/* Interrupt Remapping Table Entry Definition */
union VTD_IR_TableEntry {
    struct {
#ifdef HOST_WORDS_BIGENDIAN
        uint32_t dest_id:32;         /* Destination ID */
        uint32_t __reserved_1:8;     /* Reserved 1 */
        uint32_t vector:8;           /* Interrupt Vector */
        uint32_t irte_mode:1;        /* IRTE Mode */
        uint32_t __reserved_0:3;     /* Reserved 0 */
        uint32_t __avail:4;          /* Available spaces for software */
        uint32_t delivery_mode:3;    /* Delivery Mode */
        uint32_t trigger_mode:1;     /* Trigger Mode */
        uint32_t redir_hint:1;       /* Redirection Hint */
        uint32_t dest_mode:1;        /* Destination Mode */
        uint32_t fault_disable:1;    /* Fault Processing Disable */
        uint32_t present:1;          /* Whether entry present/available */
#else
        uint32_t present:1;          /* Whether entry present/available */
        uint32_t fault_disable:1;    /* Fault Processing Disable */
        uint32_t dest_mode:1;        /* Destination Mode */
        uint32_t redir_hint:1;       /* Redirection Hint */
        uint32_t trigger_mode:1;     /* Trigger Mode */
        uint32_t delivery_mode:3;    /* Delivery Mode */
        uint32_t __avail:4;          /* Available spaces for software */
        uint32_t __reserved_0:3;     /* Reserved 0 */
        uint32_t irte_mode:1;        /* IRTE Mode */
        uint32_t vector:8;           /* Interrupt Vector */
        uint32_t __reserved_1:8;     /* Reserved 1 */
        uint32_t dest_id:32;         /* Destination ID */
#endif
        uint16_t source_id:16;       /* Source-ID */
#ifdef HOST_WORDS_BIGENDIAN
        uint64_t __reserved_2:44;    /* Reserved 2 */
        uint64_t sid_vtype:2;        /* Source-ID Validation Type */
        uint64_t sid_q:2;            /* Source-ID Qualifier */
#else
        uint64_t sid_q:2;            /* Source-ID Qualifier */
        uint64_t sid_vtype:2;        /* Source-ID Validation Type */
        uint64_t __reserved_2:44;    /* Reserved 2 */
#endif
    } QEMU_PACKED irte;
    uint64_t data[2];
};

#define VTD_IR_INT_FORMAT_COMPAT     (0) /* Compatible Interrupt */
#define VTD_IR_INT_FORMAT_REMAP      (1) /* Remappable Interrupt */

/* Programming format for MSI/MSI-X addresses */
union VTD_IR_MSIAddress {
    struct {
#ifdef HOST_WORDS_BIGENDIAN
        uint32_t __head:12;          /* Should always be: 0x0fee */
        uint32_t index_l:15;         /* Interrupt index bit 14-0 */
        uint32_t int_mode:1;         /* Interrupt format */
        uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
        uint32_t index_h:1;          /* Interrupt index bit 15 */
        uint32_t __not_care:2;
#else
        uint32_t __not_care:2;
        uint32_t index_h:1;          /* Interrupt index bit 15 */
        uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
        uint32_t int_mode:1;         /* Interrupt format */
        uint32_t index_l:15;         /* Interrupt index bit 14-0 */
        uint32_t __head:12;          /* Should always be: 0x0fee */
#endif
    } QEMU_PACKED addr;
    uint32_t data;
};

/* Generic IRQ entry information */
struct VTDIrq {
    /* Used by both IOAPIC/MSI interrupt remapping */
    uint8_t trigger_mode;
    uint8_t vector;
    uint8_t delivery_mode;
    uint32_t dest;
    uint8_t dest_mode;

    /* only used by MSI interrupt remapping */
    uint8_t redir_hint;
    uint8_t msi_addr_last_bits;
};

struct VTD_MSIMessage {
    union {
        struct {
#ifdef HOST_WORDS_BIGENDIAN
            uint32_t __addr_head:12; /* 0xfee */
            uint32_t dest:8;
            uint32_t __reserved:8;
            uint32_t redir_hint:1;
            uint32_t dest_mode:1;
            uint32_t __not_used:2;
#else
            uint32_t __not_used:2;
            uint32_t dest_mode:1;
            uint32_t redir_hint:1;
            uint32_t __reserved:8;
            uint32_t dest:8;
            uint32_t __addr_head:12; /* 0xfee */
#endif
            uint32_t __addr_hi:32;
        } QEMU_PACKED;
        uint64_t msi_addr;
    };
    union {
        struct {
#ifdef HOST_WORDS_BIGENDIAN
            uint16_t trigger_mode:1;
            uint16_t level:1;
            uint16_t __resved:3;
            uint16_t delivery_mode:3;
            uint16_t vector:8;
#else
            uint16_t vector:8;
            uint16_t delivery_mode:3;
            uint16_t __resved:3;
            uint16_t level:1;
            uint16_t trigger_mode:1;
#endif
            uint16_t __resved1:16;
        } QEMU_PACKED;
        uint32_t msi_data;
    };
};

/* When IR is enabled, all MSI/MSI-X data bits should be zero */
#define VTD_IR_MSI_DATA          (0)

/* The iommu (DMAR) device state struct */
struct IntelIOMMUState {
    X86IOMMUState x86_iommu;
    MemoryRegion csrmem;
    uint8_t csr[DMAR_REG_SIZE];     /* register values */
    uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
    uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
    uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
    uint32_t version;

    dma_addr_t root;                /* Current root table pointer */
    bool root_extended;             /* Type of root table (extended or not) */
    bool dmar_enabled;              /* Set if DMA remapping is enabled */

    uint16_t iq_head;               /* Current invalidation queue head */
    uint16_t iq_tail;               /* Current invalidation queue tail */
    dma_addr_t iq;                  /* Current invalidation queue pointer */
    uint16_t iq_size;               /* IQ Size in number of entries */
    bool qi_enabled;                /* Set if the QI is enabled */
    uint8_t iq_last_desc_type;      /* The type of last completed descriptor */

    /* The index of the Fault Recording Register to be used next.
     * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
     */
    uint16_t next_frcd_reg;

    uint64_t cap;                   /* The value of capability reg */
    uint64_t ecap;                  /* The value of extended capability reg */

    uint32_t context_cache_gen;     /* Should be in [1,MAX] */
    GHashTable *iotlb;              /* IOTLB */

    MemoryRegionIOMMUOps iommu_ops;
    GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
    VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */

    /* interrupt remapping */
    bool intr_enabled;              /* Whether guest enabled IR */
    dma_addr_t intr_root;           /* Interrupt remapping table pointer */
    uint32_t intr_size;             /* Number of IR table entries */
    bool intr_eime;                 /* Extended interrupt mode enabled */
};

/* Find the VTD Address space associated with the given bus pointer,
 * create a new one if none exists
 */
VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);

#endif
Commit	Line	Data
1da12ec4 LT	1	/*
	2	* QEMU emulation of an Intel IOMMU (VT-d)
	3	* (DMA Remapping device)
	4	*
	5	* Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
	6	* Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef INTEL_IOMMU_H
	23	#define INTEL_IOMMU_H
	24	#include "hw/qdev.h"
	25	#include "sysemu/dma.h"
1c7955c4	26	#include "hw/i386/x86-iommu.h"
651e4cef PX	27	#include "hw/i386/ioapic.h"
651e4cef PX	28	#include "hw/pci/msi.h"
8b5ed7df	29	#include "hw/sysbus.h"
1da12ec4 LT	30
	31	#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
	32	#define INTEL_IOMMU_DEVICE(obj) \
	33	OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
	34
	35	/* DMAR Hardware Unit Definition address (IOMMU unit) */
	36	#define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
	37
	38	#define VTD_PCI_BUS_MAX 256
	39	#define VTD_PCI_SLOT_MAX 32
	40	#define VTD_PCI_FUNC_MAX 8
1da12ec4 LT	41	#define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
1da12ec4 LT	42	#define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
1e06f131	43	#define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
d92fa2dc	44	#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
1da12ec4 LT	45
	46	#define DMAR_REG_SIZE 0x230
	47	#define VTD_HOST_ADDRESS_WIDTH 39
	48	#define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)
	49
d46114f9 PX	50	#define DMAR_REPORT_F_INTR (1)
d46114f9 PX	51
651e4cef PX	52	#define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
	53	#define VTD_MSI_ADDR_HI_SHIFT (32)
	54	#define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
	55
d92fa2dc LT	56	typedef struct VTDContextEntry VTDContextEntry;
d92fa2dc LT	57	typedef struct VTDContextCacheEntry VTDContextCacheEntry;
1da12ec4 LT	58	typedef struct IntelIOMMUState IntelIOMMUState;
1da12ec4 LT	59	typedef struct VTDAddressSpace VTDAddressSpace;
b5a280c0	60	typedef struct VTDIOTLBEntry VTDIOTLBEntry;
7df953bd	61	typedef struct VTDBus VTDBus;
bc38ee10	62	typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
1f91acee	63	typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
651e4cef PX	64	typedef struct VTDIrq VTDIrq;
651e4cef PX	65	typedef struct VTD_MSIMessage VTD_MSIMessage;
d92fa2dc LT	66
	67	/* Context-Entry */
	68	struct VTDContextEntry {
	69	uint64_t lo;
	70	uint64_t hi;
	71	};
	72
	73	struct VTDContextCacheEntry {
	74	/* The cache entry is obsolete if
	75	* context_cache_gen!=IntelIOMMUState.context_cache_gen
	76	*/
	77	uint32_t context_cache_gen;
	78	struct VTDContextEntry context_entry;
	79	};
	80
1da12ec4	81	struct VTDAddressSpace {
7df953bd	82	PCIBus *bus;
1da12ec4 LT	83	uint8_t devfn;
	84	AddressSpace as;
	85	MemoryRegion iommu;
651e4cef	86	MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
1da12ec4	87	IntelIOMMUState *iommu_state;
d92fa2dc	88	VTDContextCacheEntry context_cache_entry;
1da12ec4 LT	89	};
1da12ec4 LT	90
7df953bd KO	91	struct VTDBus {
	92	PCIBus* bus; /* A reference to the bus to provide translation for */
	93	VTDAddressSpace dev_as[0]; / A table of VTDAddressSpace objects indexed by devfn */
	94	};
	95
b5a280c0 LT	96	struct VTDIOTLBEntry {
	97	uint64_t gfn;
	98	uint16_t domain_id;
	99	uint64_t slpte;
d66b969b	100	uint64_t mask;
b5a280c0 LT	101	bool read_flags;
	102	bool write_flags;
	103	};
	104
ede9c94a PX	105	/* VT-d Source-ID Qualifier types */
	106	enum {
	107	VTD_SQ_FULL = 0x00, /* Full SID verification */
	108	VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */
	109	VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */
	110	VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */
	111	VTD_SQ_MAX,
	112	};
	113
	114	/* VT-d Source Validation Types */
	115	enum {
	116	VTD_SVT_NONE = 0x00, /* No validation */
	117	VTD_SVT_ALL = 0x01, /* Do full validation */
	118	VTD_SVT_BUS = 0x02, /* Validate bus range */
	119	VTD_SVT_MAX,
	120	};
	121
1f91acee	122	/* Interrupt Remapping Table Entry Definition */
bc38ee10	123	union VTD_IR_TableEntry {
1f91acee PX	124	struct {
	125	#ifdef HOST_WORDS_BIGENDIAN
	126	uint32_t dest_id:32; /* Destination ID */
	127	uint32_t __reserved_1:8; /* Reserved 1 */
	128	uint32_t vector:8; /* Interrupt Vector */
	129	uint32_t irte_mode:1; /* IRTE Mode */
	130	uint32_t __reserved_0:3; /* Reserved 0 */
	131	uint32_t __avail:4; /* Available spaces for software */
	132	uint32_t delivery_mode:3; /* Delivery Mode */
	133	uint32_t trigger_mode:1; /* Trigger Mode */
	134	uint32_t redir_hint:1; /* Redirection Hint */
	135	uint32_t dest_mode:1; /* Destination Mode */
	136	uint32_t fault_disable:1; /* Fault Processing Disable */
	137	uint32_t present:1; /* Whether entry present/available */
	138	#else
	139	uint32_t present:1; /* Whether entry present/available */
	140	uint32_t fault_disable:1; /* Fault Processing Disable */
	141	uint32_t dest_mode:1; /* Destination Mode */
	142	uint32_t redir_hint:1; /* Redirection Hint */
	143	uint32_t trigger_mode:1; /* Trigger Mode */
	144	uint32_t delivery_mode:3; /* Delivery Mode */
	145	uint32_t __avail:4; /* Available spaces for software */
	146	uint32_t __reserved_0:3; /* Reserved 0 */
	147	uint32_t irte_mode:1; /* IRTE Mode */
	148	uint32_t vector:8; /* Interrupt Vector */
	149	uint32_t __reserved_1:8; /* Reserved 1 */
	150	uint32_t dest_id:32; /* Destination ID */
	151	#endif
	152	uint16_t source_id:16; /* Source-ID */
	153	#ifdef HOST_WORDS_BIGENDIAN
	154	uint64_t __reserved_2:44; /* Reserved 2 */
	155	uint64_t sid_vtype:2; /* Source-ID Validation Type */
	156	uint64_t sid_q:2; /* Source-ID Qualifier */
	157	#else
	158	uint64_t sid_q:2; /* Source-ID Qualifier */
	159	uint64_t sid_vtype:2; /* Source-ID Validation Type */
	160	uint64_t __reserved_2:44; /* Reserved 2 */
	161	#endif
bc38ee10	162	} QEMU_PACKED irte;
1f91acee PX	163	uint64_t data[2];
	164	};
	165
	166	#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
	167	#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
	168
	169	/* Programming format for MSI/MSI-X addresses */
	170	union VTD_IR_MSIAddress {
	171	struct {
	172	#ifdef HOST_WORDS_BIGENDIAN
	173	uint32_t __head:12; /* Should always be: 0x0fee */
	174	uint32_t index_l:15; /* Interrupt index bit 14-0 */
	175	uint32_t int_mode:1; /* Interrupt format */
	176	uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
	177	uint32_t index_h:1; /* Interrupt index bit 15 */
	178	uint32_t __not_care:2;
	179	#else
	180	uint32_t __not_care:2;
	181	uint32_t index_h:1; /* Interrupt index bit 15 */
	182	uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
	183	uint32_t int_mode:1; /* Interrupt format */
	184	uint32_t index_l:15; /* Interrupt index bit 14-0 */
	185	uint32_t __head:12; /* Should always be: 0x0fee */
	186	#endif
bc38ee10	187	} QEMU_PACKED addr;
1f91acee PX	188	uint32_t data;
	189	};
	190
651e4cef PX	191	/* Generic IRQ entry information */
	192	struct VTDIrq {
	193	/* Used by both IOAPIC/MSI interrupt remapping */
	194	uint8_t trigger_mode;
	195	uint8_t vector;
	196	uint8_t delivery_mode;
	197	uint32_t dest;
	198	uint8_t dest_mode;
	199
	200	/* only used by MSI interrupt remapping */
	201	uint8_t redir_hint;
	202	uint8_t msi_addr_last_bits;
	203	};
	204
	205	struct VTD_MSIMessage {
	206	union {
	207	struct {
	208	#ifdef HOST_WORDS_BIGENDIAN
	209	uint32_t __addr_head:12; /* 0xfee */
	210	uint32_t dest:8;
	211	uint32_t __reserved:8;
	212	uint32_t redir_hint:1;
	213	uint32_t dest_mode:1;
	214	uint32_t __not_used:2;
	215	#else
	216	uint32_t __not_used:2;
	217	uint32_t dest_mode:1;
	218	uint32_t redir_hint:1;
	219	uint32_t __reserved:8;
	220	uint32_t dest:8;
	221	uint32_t __addr_head:12; /* 0xfee */
	222	#endif
	223	uint32_t __addr_hi:32;
	224	} QEMU_PACKED;
	225	uint64_t msi_addr;
	226	};
	227	union {
	228	struct {
	229	#ifdef HOST_WORDS_BIGENDIAN
	230	uint16_t trigger_mode:1;
	231	uint16_t level:1;
	232	uint16_t __resved:3;
	233	uint16_t delivery_mode:3;
	234	uint16_t vector:8;
	235	#else
	236	uint16_t vector:8;
	237	uint16_t delivery_mode:3;
	238	uint16_t __resved:3;
	239	uint16_t level:1;
	240	uint16_t trigger_mode:1;
	241	#endif
	242	uint16_t __resved1:16;
	243	} QEMU_PACKED;
	244	uint32_t msi_data;
	245	};
	246	};
	247
1f91acee PX	248	/* When IR is enabled, all MSI/MSI-X data bits should be zero */
	249	#define VTD_IR_MSI_DATA (0)
	250
1da12ec4 LT	251	/* The iommu (DMAR) device state struct */
1da12ec4 LT	252	struct IntelIOMMUState {
1c7955c4	253	X86IOMMUState x86_iommu;
1da12ec4 LT	254	MemoryRegion csrmem;
	255	uint8_t csr[DMAR_REG_SIZE]; /* register values */
	256	uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
	257	uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
	258	uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
	259	uint32_t version;
	260
	261	dma_addr_t root; /* Current root table pointer */
	262	bool root_extended; /* Type of root table (extended or not) */
	263	bool dmar_enabled; /* Set if DMA remapping is enabled */
	264
	265	uint16_t iq_head; /* Current invalidation queue head */
	266	uint16_t iq_tail; /* Current invalidation queue tail */
	267	dma_addr_t iq; /* Current invalidation queue pointer */
	268	uint16_t iq_size; /* IQ Size in number of entries */
	269	bool qi_enabled; /* Set if the QI is enabled */
	270	uint8_t iq_last_desc_type; /* The type of last completed descriptor */
	271
	272	/* The index of the Fault Recording Register to be used next.
	273	* Wraps around from N-1 to 0, where N is the number of FRCD_REG.
	274	*/
	275	uint16_t next_frcd_reg;
	276
	277	uint64_t cap; /* The value of capability reg */
	278	uint64_t ecap; /* The value of extended capability reg */
	279
d92fa2dc	280	uint32_t context_cache_gen; /* Should be in [1,MAX] */
b5a280c0	281	GHashTable iotlb; / IOTLB */
d92fa2dc	282
1da12ec4	283	MemoryRegionIOMMUOps iommu_ops;
7df953bd KO	284	GHashTable vtd_as_by_busptr; / VTDBus objects indexed by PCIBus* reference */
7df953bd KO	285	VTDBus vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; / VTDBus objects indexed by bus number */
a5861439 PX	286
	287	/* interrupt remapping */
	288	bool intr_enabled; /* Whether guest enabled IR */
	289	dma_addr_t intr_root; /* Interrupt remapping table pointer */
	290	uint32_t intr_size; /* Number of IR table entries */
28589311	291	bool intr_eime; /* Extended interrupt mode enabled */
1da12ec4 LT	292	};
1da12ec4 LT	293
7df953bd KO	294	/* Find the VTD Address space associated with the given bus pointer,
	295	* create a new one if none exists
	296	*/
	297	VTDAddressSpace vtd_find_add_as(IntelIOMMUState s, PCIBus *bus, int devfn);
	298
1da12ec4	299	#endif