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1/*
2 * IOAPIC emulation logic - internal interfaces
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2009 Xiantao Zhang, Intel
6 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef QEMU_IOAPIC_INTERNAL_H
23#define QEMU_IOAPIC_INTERNAL_H
24
83c9f4ca 25#include "hw/hw.h"
022c62cb 26#include "exec/memory.h"
83c9f4ca 27#include "hw/sysbus.h"
e3d9c925 28#include "qemu/notify.h"
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29
30#define MAX_IOAPICS 1
31
244ac3af 32#define IOAPIC_LVT_DEST_SHIFT 56
cb135f59 33#define IOAPIC_LVT_DEST_IDX_SHIFT 48
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34#define IOAPIC_LVT_MASKED_SHIFT 16
35#define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15
36#define IOAPIC_LVT_REMOTE_IRR_SHIFT 14
37#define IOAPIC_LVT_POLARITY_SHIFT 13
38#define IOAPIC_LVT_DELIV_STATUS_SHIFT 12
39#define IOAPIC_LVT_DEST_MODE_SHIFT 11
40#define IOAPIC_LVT_DELIV_MODE_SHIFT 8
41
42#define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
af599407 43#define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
244ac3af 44#define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
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45#define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT)
46#define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
47#define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
48#define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
244ac3af 49
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50/* Bits that are read-only for IOAPIC entry */
51#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \
52 IOAPIC_LVT_DELIV_STATUS)
53#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS)
54
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55#define IOAPIC_TRIGGER_EDGE 0
56#define IOAPIC_TRIGGER_LEVEL 1
57
58/*io{apic,sapic} delivery mode*/
59#define IOAPIC_DM_FIXED 0x0
60#define IOAPIC_DM_LOWEST_PRIORITY 0x1
61#define IOAPIC_DM_PMI 0x2
62#define IOAPIC_DM_NMI 0x4
63#define IOAPIC_DM_INIT 0x5
64#define IOAPIC_DM_SIPI 0x6
65#define IOAPIC_DM_EXTINT 0x7
66#define IOAPIC_DM_MASK 0x7
67
68#define IOAPIC_VECTOR_MASK 0xff
69
70#define IOAPIC_IOREGSEL 0x00
71#define IOAPIC_IOWIN 0x10
20fd4b7b 72#define IOAPIC_EOI 0x40
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73
74#define IOAPIC_REG_ID 0x00
75#define IOAPIC_REG_VER 0x01
76#define IOAPIC_REG_ARB 0x02
77#define IOAPIC_REG_REDTBL_BASE 0x10
78#define IOAPIC_ID 0x00
79
80#define IOAPIC_ID_SHIFT 24
81#define IOAPIC_ID_MASK 0xf
82
83#define IOAPIC_VER_ENTRIES_SHIFT 16
84
85typedef struct IOAPICCommonState IOAPICCommonState;
86
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87#define TYPE_IOAPIC_COMMON "ioapic-common"
88#define IOAPIC_COMMON(obj) \
89 OBJECT_CHECK(IOAPICCommonState, (obj), TYPE_IOAPIC_COMMON)
90#define IOAPIC_COMMON_CLASS(klass) \
91 OBJECT_CLASS_CHECK(IOAPICCommonClass, (klass), TYPE_IOAPIC_COMMON)
92#define IOAPIC_COMMON_GET_CLASS(obj) \
93 OBJECT_GET_CLASS(IOAPICCommonClass, (obj), TYPE_IOAPIC_COMMON)
94
95typedef struct IOAPICCommonClass {
96 SysBusDeviceClass parent_class;
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97
98 DeviceRealize realize;
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99 void (*pre_save)(IOAPICCommonState *s);
100 void (*post_load)(IOAPICCommonState *s);
101} IOAPICCommonClass;
102
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103struct IOAPICCommonState {
104 SysBusDevice busdev;
105 MemoryRegion io_memory;
106 uint8_t id;
107 uint8_t ioregsel;
108 uint32_t irr;
109 uint64_t ioredtbl[IOAPIC_NUM_PINS];
e3d9c925 110 Notifier machine_done;
20fd4b7b 111 uint8_t version;
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112};
113
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114void ioapic_reset_common(DeviceState *dev);
115
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116void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s);
117
175de524 118#endif /* QEMU_IOAPIC_INTERNAL_H */