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247c9de1 EH |
1 | /* |
2 | * x86 CPU topology data structures and functions | |
3 | * | |
4 | * Copyright (c) 2012 Red Hat Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
869b7649 EH |
24 | #ifndef HW_I386_TOPOLOGY_H |
25 | #define HW_I386_TOPOLOGY_H | |
247c9de1 EH |
26 | |
27 | /* This file implements the APIC-ID-based CPU topology enumeration logic, | |
28 | * documented at the following document: | |
29 | * IntelĀ® 64 Architecture Processor Topology Enumeration | |
30 | * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ | |
31 | * | |
32 | * This code should be compatible with AMD's "Extended Method" described at: | |
33 | * AMD CPUID Specification (Publication #25481) | |
34 | * Section 3: Multiple Core Calcuation | |
35 | * as long as: | |
36 | * nr_threads is set to 1; | |
37 | * OFFSET_IDX is assumed to be 0; | |
38 | * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). | |
39 | */ | |
40 | ||
247c9de1 EH |
41 | |
42 | #include "qemu/bitops.h" | |
43 | ||
44 | /* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support | |
45 | */ | |
46 | typedef uint32_t apic_id_t; | |
47 | ||
dcf08bc6 | 48 | typedef struct X86CPUTopoIDs { |
ed256144 | 49 | unsigned pkg_id; |
176d2cda | 50 | unsigned die_id; |
ed256144 CF |
51 | unsigned core_id; |
52 | unsigned smt_id; | |
dcf08bc6 | 53 | } X86CPUTopoIDs; |
ed256144 | 54 | |
53a5e7bd BM |
55 | typedef struct X86CPUTopoInfo { |
56 | unsigned dies_per_pkg; | |
57 | unsigned cores_per_die; | |
58 | unsigned threads_per_core; | |
59 | } X86CPUTopoInfo; | |
60 | ||
247c9de1 EH |
61 | /* Return the bit width needed for 'count' IDs |
62 | */ | |
63 | static unsigned apicid_bitwidth_for_count(unsigned count) | |
64 | { | |
65 | g_assert(count >= 1); | |
14e53426 RH |
66 | count -= 1; |
67 | return count ? 32 - clz32(count) : 0; | |
247c9de1 EH |
68 | } |
69 | ||
70 | /* Bit width of the SMT_ID (thread ID) field on the APIC ID | |
71 | */ | |
f20dec0b | 72 | static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) |
247c9de1 | 73 | { |
f20dec0b | 74 | return apicid_bitwidth_for_count(topo_info->threads_per_core); |
247c9de1 EH |
75 | } |
76 | ||
77 | /* Bit width of the Core_ID field | |
78 | */ | |
f20dec0b | 79 | static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) |
247c9de1 | 80 | { |
f20dec0b | 81 | return apicid_bitwidth_for_count(topo_info->cores_per_die); |
247c9de1 EH |
82 | } |
83 | ||
d65af288 | 84 | /* Bit width of the Die_ID field */ |
f20dec0b | 85 | static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) |
d65af288 | 86 | { |
f20dec0b | 87 | return apicid_bitwidth_for_count(topo_info->dies_per_pkg); |
d65af288 LX |
88 | } |
89 | ||
247c9de1 EH |
90 | /* Bit offset of the Core_ID field |
91 | */ | |
f20dec0b | 92 | static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) |
247c9de1 | 93 | { |
f20dec0b | 94 | return apicid_smt_width(topo_info); |
d65af288 LX |
95 | } |
96 | ||
97 | /* Bit offset of the Die_ID field */ | |
f20dec0b | 98 | static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) |
d65af288 | 99 | { |
f20dec0b | 100 | return apicid_core_offset(topo_info) + apicid_core_width(topo_info); |
247c9de1 EH |
101 | } |
102 | ||
103 | /* Bit offset of the Pkg_ID (socket ID) field | |
104 | */ | |
f20dec0b | 105 | static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) |
247c9de1 | 106 | { |
f20dec0b | 107 | return apicid_die_offset(topo_info) + apicid_die_width(topo_info); |
247c9de1 EH |
108 | } |
109 | ||
110 | /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID | |
111 | * | |
112 | * The caller must make sure core_id < nr_cores and smt_id < nr_threads. | |
113 | */ | |
3c6712ec BM |
114 | static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, |
115 | const X86CPUTopoIDs *topo_ids) | |
247c9de1 | 116 | { |
f20dec0b BM |
117 | return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | |
118 | (topo_ids->die_id << apicid_die_offset(topo_info)) | | |
119 | (topo_ids->core_id << apicid_core_offset(topo_info)) | | |
dcf08bc6 | 120 | topo_ids->smt_id; |
247c9de1 EH |
121 | } |
122 | ||
123 | /* Calculate thread/core/package IDs for a specific topology, | |
124 | * based on (contiguous) CPU index | |
125 | */ | |
53a5e7bd | 126 | static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, |
247c9de1 | 127 | unsigned cpu_index, |
dcf08bc6 | 128 | X86CPUTopoIDs *topo_ids) |
247c9de1 | 129 | { |
53a5e7bd BM |
130 | unsigned nr_dies = topo_info->dies_per_pkg; |
131 | unsigned nr_cores = topo_info->cores_per_die; | |
132 | unsigned nr_threads = topo_info->threads_per_core; | |
133 | ||
dcf08bc6 BM |
134 | topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); |
135 | topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; | |
136 | topo_ids->core_id = cpu_index / nr_threads % nr_cores; | |
137 | topo_ids->smt_id = cpu_index % nr_threads; | |
247c9de1 EH |
138 | } |
139 | ||
9f3aab58 IM |
140 | /* Calculate thread/core/package IDs for a specific topology, |
141 | * based on APIC ID | |
142 | */ | |
143 | static inline void x86_topo_ids_from_apicid(apic_id_t apicid, | |
53a5e7bd | 144 | X86CPUTopoInfo *topo_info, |
dcf08bc6 | 145 | X86CPUTopoIDs *topo_ids) |
9f3aab58 | 146 | { |
dcf08bc6 | 147 | topo_ids->smt_id = apicid & |
f20dec0b | 148 | ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); |
dcf08bc6 | 149 | topo_ids->core_id = |
f20dec0b BM |
150 | (apicid >> apicid_core_offset(topo_info)) & |
151 | ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); | |
dcf08bc6 | 152 | topo_ids->die_id = |
f20dec0b BM |
153 | (apicid >> apicid_die_offset(topo_info)) & |
154 | ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); | |
155 | topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info); | |
9f3aab58 IM |
156 | } |
157 | ||
247c9de1 EH |
158 | /* Make APIC ID for the CPU 'cpu_index' |
159 | * | |
160 | * 'cpu_index' is a sequential, contiguous ID for the CPU. | |
161 | */ | |
53a5e7bd | 162 | static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, |
247c9de1 EH |
163 | unsigned cpu_index) |
164 | { | |
dcf08bc6 | 165 | X86CPUTopoIDs topo_ids; |
53a5e7bd | 166 | x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); |
3c6712ec | 167 | return x86_apicid_from_topo_ids(topo_info, &topo_ids); |
247c9de1 EH |
168 | } |
169 | ||
869b7649 | 170 | #endif /* HW_I386_TOPOLOGY_H */ |