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247c9de1 EH |
1 | /* |
2 | * x86 CPU topology data structures and functions | |
3 | * | |
4 | * Copyright (c) 2012 Red Hat Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
869b7649 EH |
24 | #ifndef HW_I386_TOPOLOGY_H |
25 | #define HW_I386_TOPOLOGY_H | |
247c9de1 EH |
26 | |
27 | /* This file implements the APIC-ID-based CPU topology enumeration logic, | |
28 | * documented at the following document: | |
29 | * IntelĀ® 64 Architecture Processor Topology Enumeration | |
30 | * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ | |
31 | * | |
32 | * This code should be compatible with AMD's "Extended Method" described at: | |
33 | * AMD CPUID Specification (Publication #25481) | |
34 | * Section 3: Multiple Core Calcuation | |
35 | * as long as: | |
36 | * nr_threads is set to 1; | |
37 | * OFFSET_IDX is assumed to be 0; | |
38 | * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). | |
39 | */ | |
40 | ||
247c9de1 EH |
41 | |
42 | #include "qemu/bitops.h" | |
43 | ||
44 | /* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support | |
45 | */ | |
46 | typedef uint32_t apic_id_t; | |
47 | ||
ed256144 CF |
48 | typedef struct X86CPUTopoInfo { |
49 | unsigned pkg_id; | |
176d2cda | 50 | unsigned die_id; |
ed256144 CF |
51 | unsigned core_id; |
52 | unsigned smt_id; | |
53 | } X86CPUTopoInfo; | |
54 | ||
247c9de1 EH |
55 | /* Return the bit width needed for 'count' IDs |
56 | */ | |
57 | static unsigned apicid_bitwidth_for_count(unsigned count) | |
58 | { | |
59 | g_assert(count >= 1); | |
14e53426 RH |
60 | count -= 1; |
61 | return count ? 32 - clz32(count) : 0; | |
247c9de1 EH |
62 | } |
63 | ||
64 | /* Bit width of the SMT_ID (thread ID) field on the APIC ID | |
65 | */ | |
d65af288 LX |
66 | static inline unsigned apicid_smt_width(unsigned nr_dies, |
67 | unsigned nr_cores, | |
68 | unsigned nr_threads) | |
247c9de1 EH |
69 | { |
70 | return apicid_bitwidth_for_count(nr_threads); | |
71 | } | |
72 | ||
73 | /* Bit width of the Core_ID field | |
74 | */ | |
d65af288 LX |
75 | static inline unsigned apicid_core_width(unsigned nr_dies, |
76 | unsigned nr_cores, | |
77 | unsigned nr_threads) | |
247c9de1 EH |
78 | { |
79 | return apicid_bitwidth_for_count(nr_cores); | |
80 | } | |
81 | ||
d65af288 LX |
82 | /* Bit width of the Die_ID field */ |
83 | static inline unsigned apicid_die_width(unsigned nr_dies, | |
84 | unsigned nr_cores, | |
85 | unsigned nr_threads) | |
86 | { | |
87 | return apicid_bitwidth_for_count(nr_dies); | |
88 | } | |
89 | ||
247c9de1 EH |
90 | /* Bit offset of the Core_ID field |
91 | */ | |
d65af288 LX |
92 | static inline unsigned apicid_core_offset(unsigned nr_dies, |
93 | unsigned nr_cores, | |
247c9de1 EH |
94 | unsigned nr_threads) |
95 | { | |
d65af288 LX |
96 | return apicid_smt_width(nr_dies, nr_cores, nr_threads); |
97 | } | |
98 | ||
99 | /* Bit offset of the Die_ID field */ | |
100 | static inline unsigned apicid_die_offset(unsigned nr_dies, | |
101 | unsigned nr_cores, | |
102 | unsigned nr_threads) | |
103 | { | |
104 | return apicid_core_offset(nr_dies, nr_cores, nr_threads) + | |
105 | apicid_core_width(nr_dies, nr_cores, nr_threads); | |
247c9de1 EH |
106 | } |
107 | ||
108 | /* Bit offset of the Pkg_ID (socket ID) field | |
109 | */ | |
d65af288 LX |
110 | static inline unsigned apicid_pkg_offset(unsigned nr_dies, |
111 | unsigned nr_cores, | |
112 | unsigned nr_threads) | |
247c9de1 | 113 | { |
d65af288 LX |
114 | return apicid_die_offset(nr_dies, nr_cores, nr_threads) + |
115 | apicid_die_width(nr_dies, nr_cores, nr_threads); | |
247c9de1 EH |
116 | } |
117 | ||
118 | /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID | |
119 | * | |
120 | * The caller must make sure core_id < nr_cores and smt_id < nr_threads. | |
121 | */ | |
d65af288 LX |
122 | static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, |
123 | unsigned nr_cores, | |
247c9de1 | 124 | unsigned nr_threads, |
ed256144 | 125 | const X86CPUTopoInfo *topo) |
247c9de1 | 126 | { |
d65af288 LX |
127 | return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | |
128 | (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | | |
129 | (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | | |
ed256144 | 130 | topo->smt_id; |
247c9de1 EH |
131 | } |
132 | ||
133 | /* Calculate thread/core/package IDs for a specific topology, | |
134 | * based on (contiguous) CPU index | |
135 | */ | |
d65af288 LX |
136 | static inline void x86_topo_ids_from_idx(unsigned nr_dies, |
137 | unsigned nr_cores, | |
247c9de1 EH |
138 | unsigned nr_threads, |
139 | unsigned cpu_index, | |
ed256144 | 140 | X86CPUTopoInfo *topo) |
247c9de1 | 141 | { |
d65af288 LX |
142 | topo->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); |
143 | topo->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; | |
144 | topo->core_id = cpu_index / nr_threads % nr_cores; | |
ed256144 | 145 | topo->smt_id = cpu_index % nr_threads; |
247c9de1 EH |
146 | } |
147 | ||
9f3aab58 IM |
148 | /* Calculate thread/core/package IDs for a specific topology, |
149 | * based on APIC ID | |
150 | */ | |
151 | static inline void x86_topo_ids_from_apicid(apic_id_t apicid, | |
d65af288 | 152 | unsigned nr_dies, |
9f3aab58 IM |
153 | unsigned nr_cores, |
154 | unsigned nr_threads, | |
155 | X86CPUTopoInfo *topo) | |
156 | { | |
157 | topo->smt_id = apicid & | |
d65af288 LX |
158 | ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); |
159 | topo->core_id = | |
160 | (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & | |
161 | ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads)); | |
162 | topo->die_id = | |
163 | (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & | |
164 | ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads)); | |
165 | topo->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); | |
9f3aab58 IM |
166 | } |
167 | ||
247c9de1 EH |
168 | /* Make APIC ID for the CPU 'cpu_index' |
169 | * | |
170 | * 'cpu_index' is a sequential, contiguous ID for the CPU. | |
171 | */ | |
d65af288 LX |
172 | static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, |
173 | unsigned nr_cores, | |
247c9de1 EH |
174 | unsigned nr_threads, |
175 | unsigned cpu_index) | |
176 | { | |
ed256144 | 177 | X86CPUTopoInfo topo; |
d65af288 LX |
178 | x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo); |
179 | return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo); | |
247c9de1 EH |
180 | } |
181 | ||
869b7649 | 182 | #endif /* HW_I386_TOPOLOGY_H */ |