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1c7955c4 PX |
1 | /* |
2 | * Common IOMMU interface for X86 platform | |
3 | * | |
4 | * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | ||
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
58ea30f5 MA |
20 | #ifndef HW_I386_X86_IOMMU_H |
21 | #define HW_I386_X86_IOMMU_H | |
1c7955c4 PX |
22 | |
23 | #include "hw/sysbus.h" | |
35c24501 | 24 | #include "hw/pci/msi.h" |
db1015e9 | 25 | #include "qom/object.h" |
1c7955c4 PX |
26 | |
27 | #define TYPE_X86_IOMMU_DEVICE ("x86-iommu") | |
a489d195 | 28 | OBJECT_DECLARE_TYPE(X86IOMMUState, X86IOMMUClass, X86_IOMMU_DEVICE) |
1c7955c4 | 29 | |
8b5ed7df | 30 | #define X86_IOMMU_SID_INVALID (0xffff) |
04af0e18 | 31 | |
35c24501 BS |
32 | typedef struct X86IOMMUIrq X86IOMMUIrq; |
33 | typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage; | |
1c7955c4 PX |
34 | |
35 | struct X86IOMMUClass { | |
36 | SysBusDeviceClass parent; | |
37 | /* Intel/AMD specific realize() hook */ | |
38 | DeviceRealize realize; | |
8b5ed7df PX |
39 | /* MSI-based interrupt remapping */ |
40 | int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src, | |
41 | MSIMessage *dst, uint16_t sid); | |
1c7955c4 PX |
42 | }; |
43 | ||
02a2cbc8 PX |
44 | /** |
45 | * iec_notify_fn - IEC (Interrupt Entry Cache) notifier hook, | |
46 | * triggered when IR invalidation happens. | |
47 | * @private: private data | |
48 | * @global: whether this is a global IEC invalidation | |
49 | * @index: IRTE index to invalidate (start from) | |
50 | * @mask: invalidation mask | |
51 | */ | |
52 | typedef void (*iec_notify_fn)(void *private, bool global, | |
53 | uint32_t index, uint32_t mask); | |
54 | ||
55 | struct IEC_Notifier { | |
56 | iec_notify_fn iec_notify; | |
57 | void *private; | |
58 | QLIST_ENTRY(IEC_Notifier) list; | |
59 | }; | |
60 | typedef struct IEC_Notifier IEC_Notifier; | |
61 | ||
1c7955c4 PX |
62 | struct X86IOMMUState { |
63 | SysBusDevice busdev; | |
a924b3d8 | 64 | OnOffAuto intr_supported; /* Whether vIOMMU supports IR */ |
554f5e16 | 65 | bool dt_supported; /* Whether vIOMMU supports DT */ |
dbaabb25 | 66 | bool pt_supported; /* Whether vIOMMU supports pass-through */ |
02a2cbc8 | 67 | QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */ |
1c7955c4 PX |
68 | }; |
69 | ||
a924b3d8 PX |
70 | bool x86_iommu_ir_supported(X86IOMMUState *s); |
71 | ||
35c24501 BS |
72 | /* Generic IRQ entry information when interrupt remapping is enabled */ |
73 | struct X86IOMMUIrq { | |
74 | /* Used by both IOAPIC/MSI interrupt remapping */ | |
75 | uint8_t trigger_mode; | |
76 | uint8_t vector; | |
77 | uint8_t delivery_mode; | |
78 | uint32_t dest; | |
79 | uint8_t dest_mode; | |
80 | ||
81 | /* only used by MSI interrupt remapping */ | |
82 | uint8_t redir_hint; | |
83 | uint8_t msi_addr_last_bits; | |
84 | }; | |
85 | ||
86 | struct X86IOMMU_MSIMessage { | |
87 | union { | |
88 | struct { | |
e03b5686 | 89 | #if HOST_BIG_ENDIAN |
35c24501 BS |
90 | uint32_t __addr_head:12; /* 0xfee */ |
91 | uint32_t dest:8; | |
92 | uint32_t __reserved:8; | |
93 | uint32_t redir_hint:1; | |
94 | uint32_t dest_mode:1; | |
95 | uint32_t __not_used:2; | |
96 | #else | |
97 | uint32_t __not_used:2; | |
98 | uint32_t dest_mode:1; | |
99 | uint32_t redir_hint:1; | |
100 | uint32_t __reserved:8; | |
101 | uint32_t dest:8; | |
102 | uint32_t __addr_head:12; /* 0xfee */ | |
103 | #endif | |
104 | uint32_t __addr_hi; | |
105 | } QEMU_PACKED; | |
106 | uint64_t msi_addr; | |
107 | }; | |
108 | union { | |
109 | struct { | |
e03b5686 | 110 | #if HOST_BIG_ENDIAN |
35c24501 BS |
111 | uint16_t trigger_mode:1; |
112 | uint16_t level:1; | |
113 | uint16_t __resved:3; | |
114 | uint16_t delivery_mode:3; | |
115 | uint16_t vector:8; | |
116 | #else | |
117 | uint16_t vector:8; | |
118 | uint16_t delivery_mode:3; | |
119 | uint16_t __resved:3; | |
120 | uint16_t level:1; | |
121 | uint16_t trigger_mode:1; | |
122 | #endif | |
123 | uint16_t __resved1; | |
124 | } QEMU_PACKED; | |
125 | uint32_t msi_data; | |
126 | }; | |
127 | }; | |
128 | ||
1cf5fd57 PX |
129 | /** |
130 | * x86_iommu_get_default - get default IOMMU device | |
131 | * @return: pointer to default IOMMU device | |
132 | */ | |
133 | X86IOMMUState *x86_iommu_get_default(void); | |
134 | ||
02a2cbc8 PX |
135 | /** |
136 | * x86_iommu_iec_register_notifier - register IEC (Interrupt Entry | |
137 | * Cache) notifiers | |
138 | * @iommu: IOMMU device to register | |
139 | * @fn: IEC notifier hook function | |
140 | * @data: notifier private data | |
141 | */ | |
142 | void x86_iommu_iec_register_notifier(X86IOMMUState *iommu, | |
143 | iec_notify_fn fn, void *data); | |
144 | ||
145 | /** | |
146 | * x86_iommu_iec_notify_all - Notify IEC invalidations | |
147 | * @iommu: IOMMU device that sends the notification | |
148 | * @global: whether this is a global invalidation. If true, @index | |
149 | * and @mask are undefined. | |
150 | * @index: starting index of interrupt entry to invalidate | |
151 | * @mask: index mask for the invalidation | |
152 | */ | |
153 | void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global, | |
154 | uint32_t index, uint32_t mask); | |
155 | ||
35c24501 BS |
156 | /** |
157 | * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq | |
158 | * @X86IOMMUIrq: The IRQ information | |
159 | * @out: Output MSI message | |
160 | */ | |
161 | void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out); | |
1c7955c4 | 162 | #endif |