projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| cc28296d AB |
1 | /* |
| 2 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | |
| 3 | * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous | |
| 4 | * | |
| 5 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | |
| 6 | * Written by Andrew Baumann | |
| 7 | * | |
| 67d80321 ZB |
8 | * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti |
| 9 | * Added basic IRQ_TIMER interrupt support | |
| 10 | * | |
| 6111a0c0 PMD |
11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 12 | * See the COPYING file in the top-level directory. | |
| cc28296d AB |
13 | */ |
| 14 | ||
| 15 | #ifndef BCM2836_CONTROL_H | |
| 16 | #define BCM2836_CONTROL_H | |
| 17 | ||
| 18 | #include "hw/sysbus.h" | |
| 67d80321 | 19 | #include "qemu/timer.h" |
| db1015e9 | 20 | #include "qom/object.h" |
| cc28296d AB |
21 | |
| 22 | /* 4 mailboxes per core, for 16 total */ | |
| 23 | #define BCM2836_NCORES 4 | |
| 24 | #define BCM2836_MBPERCORE 4 | |
| 25 | ||
| 26 | #define TYPE_BCM2836_CONTROL "bcm2836-control" | |
| db1015e9 | 27 | typedef struct BCM2836ControlState BCM2836ControlState; |
| 8110fa1d EH |
28 | DECLARE_INSTANCE_CHECKER(BCM2836ControlState, BCM2836_CONTROL, |
| 29 | TYPE_BCM2836_CONTROL) | |
| cc28296d | 30 | |
| db1015e9 | 31 | struct BCM2836ControlState { |
| cc28296d AB |
32 | /*< private >*/ |
| 33 | SysBusDevice busdev; | |
| 34 | /*< public >*/ | |
| 35 | MemoryRegion iomem; | |
| 36 | ||
| 37 | /* mailbox state */ | |
| 38 | uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE]; | |
| 39 | ||
| 40 | /* interrupt routing/control registers */ | |
| 41 | uint8_t route_gpu_irq, route_gpu_fiq; | |
| 42 | uint32_t timercontrol[BCM2836_NCORES]; | |
| 43 | uint32_t mailboxcontrol[BCM2836_NCORES]; | |
| 44 | ||
| 45 | /* interrupt status regs (derived from input pins; not visible to user) */ | |
| 46 | bool gpu_irq, gpu_fiq; | |
| 47 | uint8_t timerirqs[BCM2836_NCORES]; | |
| 48 | ||
| 67d80321 ZB |
49 | /* local timer */ |
| 50 | QEMUTimer timer; | |
| 51 | uint32_t local_timer_control; | |
| 52 | uint8_t route_localtimer; | |
| 53 | ||
| cc28296d AB |
54 | /* interrupt source registers, post-routing (also input-derived; visible) */ |
| 55 | uint32_t irqsrc[BCM2836_NCORES]; | |
| 56 | uint32_t fiqsrc[BCM2836_NCORES]; | |
| 57 | ||
| 58 | /* outputs to CPU cores */ | |
| 59 | qemu_irq irq[BCM2836_NCORES]; | |
| 60 | qemu_irq fiq[BCM2836_NCORES]; | |
| db1015e9 | 61 | }; |
| cc28296d AB |
62 | |
| 63 | #endif |