projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 512709f5 JK |
1 | /* |
| 2 | * QEMU 8259 - internal interfaces | |
| 3 | * | |
| 4 | * Copyright (c) 2011 Jan Kiszka, Siemens AG | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 7 | * of this software and associated documentation files (the "Software"), to deal | |
| 8 | * in the Software without restriction, including without limitation the rights | |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 10 | * copies of the Software, and to permit persons to whom the Software is | |
| 11 | * furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 22 | * THE SOFTWARE. | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef QEMU_I8259_INTERNAL_H | |
| 26 | #define QEMU_I8259_INTERNAL_H | |
| 27 | ||
| 0d09e41a | 28 | #include "hw/isa/isa.h" |
| 1b23190a | 29 | #include "hw/intc/intc.h" |
| 852c27e2 | 30 | #include "hw/intc/i8259.h" |
| db1015e9 | 31 | #include "qom/object.h" |
| 512709f5 JK |
32 | |
| 33 | typedef struct PICCommonState PICCommonState; | |
| 34 | ||
| 8f04ee08 | 35 | #define TYPE_PIC_COMMON "pic-common" |
| db1015e9 | 36 | typedef struct PICCommonClass PICCommonClass; |
| 8110fa1d EH |
37 | DECLARE_OBJ_CHECKERS(PICCommonState, PICCommonClass, |
| 38 | PIC_COMMON, TYPE_PIC_COMMON) | |
| 8f04ee08 | 39 | |
| db1015e9 | 40 | struct PICCommonClass { |
| 8f04ee08 | 41 | ISADeviceClass parent_class; |
| d2628b7d | 42 | |
| 8f04ee08 AL |
43 | void (*pre_save)(PICCommonState *s); |
| 44 | void (*post_load)(PICCommonState *s); | |
| db1015e9 | 45 | }; |
| 8f04ee08 | 46 | |
| 512709f5 | 47 | struct PICCommonState { |
| 29bb5317 AF |
48 | ISADevice parent_obj; |
| 49 | ||
| 512709f5 JK |
50 | uint8_t last_irr; /* edge detection */ |
| 51 | uint8_t irr; /* interrupt request register */ | |
| 52 | uint8_t imr; /* interrupt mask register */ | |
| 53 | uint8_t isr; /* interrupt service register */ | |
| 54 | uint8_t priority_add; /* highest irq priority */ | |
| 55 | uint8_t irq_base; | |
| 56 | uint8_t read_reg_select; | |
| 57 | uint8_t poll; | |
| 58 | uint8_t special_mask; | |
| 59 | uint8_t init_state; | |
| 60 | uint8_t auto_eoi; | |
| 61 | uint8_t rotate_on_auto_eoi; | |
| 62 | uint8_t special_fully_nested_mode; | |
| 63 | uint8_t init4; /* true if 4 byte init */ | |
| 64 | uint8_t single_mode; /* true if slave pic is not initialized */ | |
| 65 | uint8_t elcr; /* PIIX edge/trigger selection*/ | |
| 66 | uint8_t elcr_mask; | |
| 67 | qemu_irq int_out[1]; | |
| 68 | uint32_t master; /* reflects /SP input pin */ | |
| 69 | uint32_t iobase; | |
| 70 | uint32_t elcr_addr; | |
| 71 | MemoryRegion base_io; | |
| 72 | MemoryRegion elcr_io; | |
| 73 | }; | |
| 74 | ||
| 512709f5 | 75 | void pic_reset_common(PICCommonState *s); |
| 512709f5 | 76 | ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master); |
| 1b23190a PX |
77 | void pic_stat_update_irq(int irq, int level); |
| 78 | bool pic_get_statistics(InterruptStatsProvider *obj, | |
| 79 | uint64_t **irq_counts, unsigned int *nb_irqs); | |
| 80 | void pic_print_info(InterruptStatsProvider *obj, Monitor *mon); | |
| 512709f5 | 81 | |
| 175de524 | 82 | #endif /* QEMU_I8259_INTERNAL_H */ |