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1 | /* |
2 | * ARM SSE-200 Message Handling Unit (MHU) | |
3 | * | |
4 | * Copyright (c) 2019 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * This is a model of the Message Handling Unit (MHU) which is part of the | |
14 | * Arm SSE-200 and documented in | |
15 | * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf | |
16 | * | |
17 | * QEMU interface: | |
18 | * + sysbus MMIO region 0: the system information register bank | |
19 | * + sysbus IRQ 0: interrupt for CPU 0 | |
20 | * + sysbus IRQ 1: interrupt for CPU 1 | |
21 | */ | |
22 | ||
58ea30f5 MA |
23 | #ifndef HW_MISC_ARMSSE_MHU_H |
24 | #define HW_MISC_ARMSSE_MHU_H | |
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25 | |
26 | #include "hw/sysbus.h" | |
db1015e9 | 27 | #include "qom/object.h" |
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28 | |
29 | #define TYPE_ARMSSE_MHU "armsse-mhu" | |
db1015e9 | 30 | typedef struct ARMSSEMHU ARMSSEMHU; |
8110fa1d EH |
31 | DECLARE_INSTANCE_CHECKER(ARMSSEMHU, ARMSSE_MHU, |
32 | TYPE_ARMSSE_MHU) | |
cdf63440 | 33 | |
db1015e9 | 34 | struct ARMSSEMHU { |
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35 | /*< private >*/ |
36 | SysBusDevice parent_obj; | |
37 | ||
38 | /*< public >*/ | |
39 | MemoryRegion iomem; | |
40 | qemu_irq cpu0irq; | |
41 | qemu_irq cpu1irq; | |
42 | ||
43 | uint32_t cpu0intr; | |
44 | uint32_t cpu1intr; | |
db1015e9 | 45 | }; |
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46 | |
47 | #endif |