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c2da8a8b CLG |
1 | /* |
2 | * ASPEED SDRAM Memory Controller | |
3 | * | |
4 | * Copyright (C) 2016 IBM Corp. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See the | |
7 | * COPYING file in the top-level directory. | |
8 | */ | |
9 | #ifndef ASPEED_SDMC_H | |
10 | #define ASPEED_SDMC_H | |
11 | ||
12 | #include "hw/sysbus.h" | |
db1015e9 | 13 | #include "qom/object.h" |
c2da8a8b CLG |
14 | |
15 | #define TYPE_ASPEED_SDMC "aspeed.sdmc" | |
db1015e9 EH |
16 | typedef struct AspeedSDMCClass AspeedSDMCClass; |
17 | typedef struct AspeedSDMCState AspeedSDMCState; | |
8110fa1d EH |
18 | DECLARE_OBJ_CHECKERS(AspeedSDMCState, AspeedSDMCClass, |
19 | ASPEED_SDMC, TYPE_ASPEED_SDMC) | |
8e00d1a9 CLG |
20 | #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" |
21 | #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" | |
1550d726 | 22 | #define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" |
c2da8a8b | 23 | |
14c17954 JS |
24 | /* |
25 | * SDMC has 174 documented registers. In addition the u-boot device tree | |
26 | * describes the following regions: | |
27 | * - PHY status regs at offset 0x400, length 0x200 | |
28 | * - PHY setting regs at offset 0x100, length 0x300 | |
29 | * | |
30 | * There are two sets of MRS (Mode Registers) configuration in ast2600 memory | |
31 | * system: one is in the SDRAM MC (memory controller) which is used in run | |
32 | * time, and the other is in the DDR-PHY IP which is used during DDR-PHY | |
33 | * training. | |
34 | */ | |
35 | #define ASPEED_SDMC_NR_REGS (0x500 >> 2) | |
c2da8a8b | 36 | |
db1015e9 | 37 | struct AspeedSDMCState { |
c2da8a8b CLG |
38 | /*< private >*/ |
39 | SysBusDevice parent_obj; | |
40 | ||
41 | /*< public >*/ | |
42 | MemoryRegion iomem; | |
43 | ||
44 | uint32_t regs[ASPEED_SDMC_NR_REGS]; | |
c6c7cfb0 | 45 | uint64_t ram_size; |
ebe31c0a | 46 | uint64_t max_ram_size; |
db1015e9 | 47 | }; |
c2da8a8b | 48 | |
8e00d1a9 | 49 | |
db1015e9 | 50 | struct AspeedSDMCClass { |
8e00d1a9 CLG |
51 | SysBusDeviceClass parent_class; |
52 | ||
53 | uint64_t max_ram_size; | |
533eb415 | 54 | const uint64_t *valid_ram_sizes; |
8e00d1a9 CLG |
55 | uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data); |
56 | void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data); | |
db1015e9 | 57 | }; |
8e00d1a9 | 58 | |
c2da8a8b | 59 | #endif /* ASPEED_SDMC_H */ |