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1 | /* |
2 | * ARM IoT Kit security controller | |
3 | * | |
4 | * Copyright (c) 2018 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* This is a model of the security controller which is part of the | |
13 | * Arm IoT Kit and documented in | |
14 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | |
15 | * | |
16 | * QEMU interface: | |
17 | * + sysbus MMIO region 0 is the "secure privilege control block" registers | |
18 | * + sysbus MMIO region 1 is the "non-secure privilege control block" registers | |
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19 | * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses |
20 | * should RAZ/WI or bus error | |
b1ce38e1 | 21 | * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value |
81a75deb | 22 | * + named GPIO output "msc_irq" for the combined IRQ line from the MSCs |
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23 | * Controlling the 2 APB PPCs in the IoTKit: |
24 | * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec | |
25 | * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap | |
26 | * + named GPIO outputs apb_ppc{0,1}_irq_enable | |
27 | * + named GPIO outputs apb_ppc{0,1}_irq_clear | |
28 | * + named GPIO inputs apb_ppc{0,1}_irq_status | |
29 | * Controlling each of the 4 expansion APB PPCs which a system using the IoTKit | |
30 | * might provide: | |
31 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] | |
32 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] | |
33 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable | |
34 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear | |
35 | * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status | |
36 | * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit | |
37 | * might provide: | |
38 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] | |
39 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] | |
40 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable | |
41 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear | |
42 | * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status | |
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43 | * Controlling the (up to) 4 MPCs in the IoTKit/SSE: |
44 | * + named GPIO inputs mpc_status[0..3] | |
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45 | * Controlling each of the 16 expansion MPCs which a system using the IoTKit |
46 | * might provide: | |
47 | * + named GPIO inputs mpcexp_status[0..15] | |
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48 | * Controlling each of the 16 expansion MSCs which a system using the IoTKit |
49 | * might provide: | |
50 | * + named GPIO inputs mscexp_status[0..15] | |
51 | * + named GPIO outputs mscexp_clear[0..15] | |
52 | * + named GPIO outputs mscexp_ns[0..15] | |
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53 | */ |
54 | ||
55 | #ifndef IOTKIT_SECCTL_H | |
56 | #define IOTKIT_SECCTL_H | |
57 | ||
58 | #include "hw/sysbus.h" | |
db1015e9 | 59 | #include "qom/object.h" |
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60 | |
61 | #define TYPE_IOTKIT_SECCTL "iotkit-secctl" | |
db1015e9 | 62 | typedef struct IoTKitSecCtl IoTKitSecCtl; |
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63 | DECLARE_INSTANCE_CHECKER(IoTKitSecCtl, IOTKIT_SECCTL, |
64 | TYPE_IOTKIT_SECCTL) | |
de343bb6 | 65 | |
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66 | #define IOTS_APB_PPC0_NUM_PORTS 3 |
67 | #define IOTS_APB_PPC1_NUM_PORTS 1 | |
68 | #define IOTS_PPC_NUM_PORTS 16 | |
69 | #define IOTS_NUM_APB_PPC 2 | |
70 | #define IOTS_NUM_APB_EXP_PPC 4 | |
71 | #define IOTS_NUM_AHB_EXP_PPC 4 | |
3fd3cb2f | 72 | #define IOTS_NUM_EXP_MPC 16 |
0a78d7eb | 73 | #define IOTS_NUM_MPC 4 |
81a75deb | 74 | #define IOTS_NUM_EXP_MSC 16 |
b3717c23 | 75 | |
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76 | |
77 | /* State and IRQ lines relating to a PPC. For the | |
78 | * PPCs in the IoTKit not all the IRQ lines are used. | |
79 | */ | |
80 | typedef struct IoTKitSecCtlPPC { | |
81 | qemu_irq nonsec[IOTS_PPC_NUM_PORTS]; | |
82 | qemu_irq ap[IOTS_PPC_NUM_PORTS]; | |
83 | qemu_irq irq_enable; | |
84 | qemu_irq irq_clear; | |
85 | ||
86 | uint32_t ns; | |
87 | uint32_t sp; | |
88 | uint32_t nsp; | |
89 | ||
90 | /* Number of ports actually present */ | |
91 | int numports; | |
92 | /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */ | |
93 | int irq_bit_offset; | |
94 | IoTKitSecCtl *parent; | |
95 | } IoTKitSecCtlPPC; | |
96 | ||
97 | struct IoTKitSecCtl { | |
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98 | /*< private >*/ |
99 | SysBusDevice parent_obj; | |
100 | ||
101 | /*< public >*/ | |
b3717c23 | 102 | qemu_irq sec_resp_cfg; |
b1ce38e1 | 103 | qemu_irq nsc_cfg_irq; |
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104 | |
105 | MemoryRegion s_regs; | |
106 | MemoryRegion ns_regs; | |
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107 | |
108 | uint32_t secppcintstat; | |
109 | uint32_t secppcinten; | |
110 | uint32_t secrespcfg; | |
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111 | uint32_t nsccfg; |
112 | uint32_t brginten; | |
3fd3cb2f | 113 | uint32_t mpcintstatus; |
b3717c23 | 114 | |
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115 | uint32_t secmscintstat; |
116 | uint32_t secmscinten; | |
117 | uint32_t nsmscexp; | |
118 | qemu_irq mscexp_clear[IOTS_NUM_EXP_MSC]; | |
119 | qemu_irq mscexp_ns[IOTS_NUM_EXP_MSC]; | |
120 | qemu_irq msc_irq; | |
121 | ||
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122 | IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC]; |
123 | IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC]; | |
124 | IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC]; | |
125 | }; | |
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126 | |
127 | #endif |