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3994215d YK |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2015 Imagination Technologies | |
7 | * | |
8 | */ | |
9 | ||
10 | #ifndef _MIPS_GCR_H | |
11 | #define _MIPS_GCR_H | |
12 | ||
13 | #define TYPE_MIPS_GCR "mips-gcr" | |
14 | #define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR) | |
15 | ||
16 | #define GCR_BASE_ADDR 0x1fbf8000ULL | |
17 | #define GCR_ADDRSPACE_SZ 0x8000 | |
18 | ||
19 | /* Offsets to register blocks */ | |
20 | #define MIPS_GCB_OFS 0x0000 /* Global Control Block */ | |
21 | #define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */ | |
22 | #define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */ | |
23 | #define MIPS_GDB_OFS 0x6000 /* Global Debug Block */ | |
24 | ||
25 | /* Global Control Block Register Map */ | |
26 | #define GCR_CONFIG_OFS 0x0000 | |
27 | #define GCR_BASE_OFS 0x0008 | |
28 | #define GCR_REV_OFS 0x0030 | |
19494f81 | 29 | #define GCR_GIC_BASE_OFS 0x0080 |
2edd5261 | 30 | #define GCR_CPC_BASE_OFS 0x0088 |
19494f81 | 31 | #define GCR_GIC_STATUS_OFS 0x00D0 |
2edd5261 | 32 | #define GCR_CPC_STATUS_OFS 0x00F0 |
3994215d YK |
33 | #define GCR_L2_CONFIG_OFS 0x0130 |
34 | ||
35 | /* Core Local and Core Other Block Register Map */ | |
36 | #define GCR_CL_CONFIG_OFS 0x0010 | |
37 | #define GCR_CL_OTHER_OFS 0x0018 | |
38 | ||
39 | /* GCR_L2_CONFIG register fields */ | |
40 | #define GCR_L2_CONFIG_BYPASS_SHF 20 | |
41 | #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) | |
42 | ||
19494f81 LA |
43 | /* GCR_GIC_BASE register fields */ |
44 | #define GCR_GIC_BASE_GICEN_MSK 1 | |
45 | #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL | |
46 | #define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK) | |
47 | ||
2edd5261 LA |
48 | /* GCR_CPC_BASE register fields */ |
49 | #define GCR_CPC_BASE_CPCEN_MSK 1 | |
50 | #define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL | |
51 | #define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK) | |
52 | ||
3994215d YK |
53 | typedef struct MIPSGCRState MIPSGCRState; |
54 | struct MIPSGCRState { | |
55 | SysBusDevice parent_obj; | |
56 | ||
57 | int32_t gcr_rev; | |
58 | int32_t num_vps; | |
59 | hwaddr gcr_base; | |
60 | MemoryRegion iomem; | |
2edd5261 | 61 | MemoryRegion *cpc_mr; |
19494f81 | 62 | MemoryRegion *gic_mr; |
2edd5261 LA |
63 | |
64 | uint64_t cpc_base; | |
19494f81 | 65 | uint64_t gic_base; |
3994215d YK |
66 | }; |
67 | ||
68 | #endif /* _MIPS_GCR_H */ |