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1 | /* |
2 | * ARM AHB5 TrustZone Memory Protection Controller emulation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* This is a model of the TrustZone memory protection controller (MPC). | |
13 | * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM | |
14 | * (DDI 0571G): | |
15 | * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g | |
16 | * | |
17 | * The MPC sits in front of memory and allows secure software to | |
18 | * configure it to either pass through or reject transactions. | |
19 | * Rejected transactions may be configured to either be aborted, or to | |
20 | * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction. | |
21 | * | |
22 | * The MPC has a register interface which the guest uses to configure it. | |
23 | * | |
24 | * QEMU interface: | |
25 | * + sysbus MMIO region 0: MemoryRegion for the MPC's config registers | |
26 | * + sysbus MMIO region 1: MemoryRegion for the upstream end of the MPC | |
27 | * + Property "downstream": MemoryRegion defining the downstream memory | |
28 | * + Named GPIO output "irq": set for a transaction-failed interrupt | |
29 | */ | |
30 | ||
31 | #ifndef TZ_MPC_H | |
32 | #define TZ_MPC_H | |
33 | ||
34 | #include "hw/sysbus.h" | |
db1015e9 | 35 | #include "qom/object.h" |
344f4b15 PM |
36 | |
37 | #define TYPE_TZ_MPC "tz-mpc" | |
db1015e9 | 38 | typedef struct TZMPC TZMPC; |
344f4b15 PM |
39 | #define TZ_MPC(obj) OBJECT_CHECK(TZMPC, (obj), TYPE_TZ_MPC) |
40 | ||
41 | #define TZ_NUM_PORTS 16 | |
42 | ||
43 | #define TYPE_TZ_MPC_IOMMU_MEMORY_REGION "tz-mpc-iommu-memory-region" | |
44 | ||
344f4b15 PM |
45 | |
46 | struct TZMPC { | |
47 | /*< private >*/ | |
48 | SysBusDevice parent_obj; | |
49 | ||
50 | /*< public >*/ | |
51 | ||
cdb60998 PM |
52 | /* State */ |
53 | uint32_t ctrl; | |
54 | uint32_t blk_idx; | |
55 | uint32_t int_stat; | |
56 | uint32_t int_en; | |
57 | uint32_t int_info1; | |
58 | uint32_t int_info2; | |
59 | ||
60 | uint32_t *blk_lut; | |
61 | ||
344f4b15 PM |
62 | qemu_irq irq; |
63 | ||
64 | /* Properties */ | |
65 | MemoryRegion *downstream; | |
66 | ||
67 | hwaddr blocksize; | |
68 | uint32_t blk_max; | |
69 | ||
70 | /* MemoryRegions exposed to user */ | |
71 | MemoryRegion regmr; | |
72 | IOMMUMemoryRegion upstream; | |
73 | ||
74 | /* MemoryRegion used internally */ | |
75 | MemoryRegion blocked_io; | |
76 | ||
77 | AddressSpace downstream_as; | |
78 | AddressSpace blocked_io_as; | |
79 | }; | |
80 | ||
81 | #endif |