[mirror_qemu.git] / include / hw / net / imx_fec.h

/*
 * i.MX FEC/ENET Ethernet Controller emulation.
 *
 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
 *
 * Based on Coldfire Fast Ethernet Controller emulation.
 *
 * Copyright (c) 2007 CodeSourcery.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef IMX_FEC_H
#define IMX_FEC_H
#include "qom/object.h"

#define TYPE_IMX_FEC "imx.fec"
typedef struct IMXFECState IMXFECState;
DECLARE_INSTANCE_CHECKER(IMXFECState, IMX_FEC,
                         TYPE_IMX_FEC)

#define TYPE_IMX_ENET "imx.enet"

#include "hw/sysbus.h"
#include "net/net.h"

#define ENET_EIR               1
#define ENET_EIMR              2
#define ENET_RDAR              4
#define ENET_TDAR              5
#define ENET_ECR               9
#define ENET_MMFR              16
#define ENET_MSCR              17
#define ENET_MIBC              25
#define ENET_RCR               33
#define ENET_TCR               49
#define ENET_PALR              57
#define ENET_PAUR              58
#define ENET_OPD               59
#define ENET_IAUR              70
#define ENET_IALR              71
#define ENET_GAUR              72
#define ENET_GALR              73
#define ENET_TFWR              81
#define ENET_FRBR              83
#define ENET_FRSR              84
#define ENET_TDSR1             89
#define ENET_TDSR2             92
#define ENET_RDSR              96
#define ENET_TDSR              97
#define ENET_MRBR              98
#define ENET_RSFL              100
#define ENET_RSEM              101
#define ENET_RAEM              102
#define ENET_RAFL              103
#define ENET_TSEM              104
#define ENET_TAEM              105
#define ENET_TAFL              106
#define ENET_TIPG              107
#define ENET_FTRL              108
#define ENET_TACC              112
#define ENET_RACC              113
#define ENET_TDAR1             121
#define ENET_TDAR2             123
#define ENET_MIIGSK_CFGR       192
#define ENET_MIIGSK_ENR        194
#define ENET_ATCR              256
#define ENET_ATVR              257
#define ENET_ATOFF             258
#define ENET_ATPER             259
#define ENET_ATCOR             260
#define ENET_ATINC             261
#define ENET_ATSTMP            262
#define ENET_TGSR              385
#define ENET_TCSR0             386
#define ENET_TCCR0             387
#define ENET_TCSR1             388
#define ENET_TCCR1             389
#define ENET_TCSR2             390
#define ENET_TCCR2             391
#define ENET_TCSR3             392
#define ENET_TCCR3             393
#define ENET_MAX               400


/* EIR and EIMR */
#define ENET_INT_HB            (1 << 31)
#define ENET_INT_BABR          (1 << 30)
#define ENET_INT_BABT          (1 << 29)
#define ENET_INT_GRA           (1 << 28)
#define ENET_INT_TXF           (1 << 27)
#define ENET_INT_TXB           (1 << 26)
#define ENET_INT_RXF           (1 << 25)
#define ENET_INT_RXB           (1 << 24)
#define ENET_INT_MII           (1 << 23)
#define ENET_INT_EBERR         (1 << 22)
#define ENET_INT_LC            (1 << 21)
#define ENET_INT_RL            (1 << 20)
#define ENET_INT_UN            (1 << 19)
#define ENET_INT_PLR           (1 << 18)
#define ENET_INT_WAKEUP        (1 << 17)
#define ENET_INT_TS_AVAIL      (1 << 16)
#define ENET_INT_TS_TIMER      (1 << 15)
#define ENET_INT_TXF2          (1 <<  7)
#define ENET_INT_TXB2          (1 <<  6)
#define ENET_INT_TXF1          (1 <<  3)
#define ENET_INT_TXB1          (1 <<  2)

#define ENET_INT_MAC           (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \
                                ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \
                                ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \
                                ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \
                                ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \
                                ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \
                                ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2)

/* RDAR */
#define ENET_RDAR_RDAR         (1 << 24)

/* TDAR */
#define ENET_TDAR_TDAR         (1 << 24)

/* ECR */
#define ENET_ECR_RESET         (1 << 0)
#define ENET_ECR_ETHEREN       (1 << 1)
#define ENET_ECR_MAGICEN       (1 << 2)
#define ENET_ECR_SLEEP         (1 << 3)
#define ENET_ECR_EN1588        (1 << 4)
#define ENET_ECR_SPEED         (1 << 5)
#define ENET_ECR_DBGEN         (1 << 6)
#define ENET_ECR_STOPEN        (1 << 7)
#define ENET_ECR_DSBWP         (1 << 8)

/* MIBC */
#define ENET_MIBC_MIB_DIS      (1 << 31)
#define ENET_MIBC_MIB_IDLE     (1 << 30)
#define ENET_MIBC_MIB_CLEAR    (1 << 29)

/* RCR */
#define ENET_RCR_LOOP          (1 << 0)
#define ENET_RCR_DRT           (1 << 1)
#define ENET_RCR_MII_MODE      (1 << 2)
#define ENET_RCR_PROM          (1 << 3)
#define ENET_RCR_BC_REJ        (1 << 4)
#define ENET_RCR_FCE           (1 << 5)
#define ENET_RCR_RGMII_EN      (1 << 6)
#define ENET_RCR_RMII_MODE     (1 << 8)
#define ENET_RCR_RMII_10T      (1 << 9)
#define ENET_RCR_PADEN         (1 << 12)
#define ENET_RCR_PAUFWD        (1 << 13)
#define ENET_RCR_CRCFWD        (1 << 14)
#define ENET_RCR_CFEN          (1 << 15)
#define ENET_RCR_MAX_FL_SHIFT  (16)
#define ENET_RCR_MAX_FL_LENGTH (14)
#define ENET_RCR_NLC           (1 << 30)
#define ENET_RCR_GRS           (1 << 31)

#define ENET_MAX_FRAME_SIZE    (1 << ENET_RCR_MAX_FL_LENGTH)

/* TCR */
#define ENET_TCR_GTS           (1 << 0)
#define ENET_TCR_FDEN          (1 << 2)
#define ENET_TCR_TFC_PAUSE     (1 << 3)
#define ENET_TCR_RFC_PAUSE     (1 << 4)
#define ENET_TCR_ADDSEL_SHIFT  (5)
#define ENET_TCR_ADDSEL_LENGTH (3)
#define ENET_TCR_CRCFWD        (1 << 9)

/* RDSR */
#define ENET_TWFR_TFWR_SHIFT   (0)
#define ENET_TWFR_TFWR_LENGTH  (6)
#define ENET_TWFR_STRFWD       (1 << 8)

#define ENET_RACC_SHIFT16      BIT(7)

/* Buffer Descriptor.  */
typedef struct {
    uint16_t length;
    uint16_t flags;
    uint32_t data;
} IMXFECBufDesc;

#define ENET_BD_R              (1 << 15)
#define ENET_BD_E              (1 << 15)
#define ENET_BD_O1             (1 << 14)
#define ENET_BD_W              (1 << 13)
#define ENET_BD_O2             (1 << 12)
#define ENET_BD_L              (1 << 11)
#define ENET_BD_TC             (1 << 10)
#define ENET_BD_ABC            (1 << 9)
#define ENET_BD_M              (1 << 8)
#define ENET_BD_BC             (1 << 7)
#define ENET_BD_MC             (1 << 6)
#define ENET_BD_LG             (1 << 5)
#define ENET_BD_NO             (1 << 4)
#define ENET_BD_CR             (1 << 2)
#define ENET_BD_OV             (1 << 1)
#define ENET_BD_TR             (1 << 0)

typedef struct {
    uint16_t length;
    uint16_t flags;
    uint32_t data;
    uint16_t status;
    uint16_t option;
    uint16_t checksum;
    uint16_t head_proto;
    uint32_t last_buffer;
    uint32_t timestamp;
    uint32_t reserved[2];
} IMXENETBufDesc;

#define ENET_BD_ME             (1 << 15)
#define ENET_BD_TX_INT         (1 << 14)
#define ENET_BD_TS             (1 << 13)
#define ENET_BD_PINS           (1 << 12)
#define ENET_BD_IINS           (1 << 11)
#define ENET_BD_PE             (1 << 10)
#define ENET_BD_CE             (1 << 9)
#define ENET_BD_UC             (1 << 8)
#define ENET_BD_RX_INT         (1 << 7)

#define ENET_BD_TXE            (1 << 15)
#define ENET_BD_UE             (1 << 13)
#define ENET_BD_EE             (1 << 12)
#define ENET_BD_FE             (1 << 11)
#define ENET_BD_LCE            (1 << 10)
#define ENET_BD_OE             (1 << 9)
#define ENET_BD_TSE            (1 << 8)
#define ENET_BD_ICE            (1 << 5)
#define ENET_BD_PCR            (1 << 4)
#define ENET_BD_VLAN           (1 << 2)
#define ENET_BD_IPV6           (1 << 1)
#define ENET_BD_FRAG           (1 << 0)

#define ENET_BD_BDU            (1 << 31)

#define ENET_TX_RING_NUM       3

#define FSL_IMX25_FEC_SIZE      0x4000

struct IMXFECState {
    /*< private >*/
    SysBusDevice parent_obj;

    /*< public >*/
    NICState *nic;
    NICConf conf;
    qemu_irq irq[2];
    MemoryRegion iomem;

    uint32_t regs[ENET_MAX];
    uint32_t rx_descriptor;

    uint32_t tx_descriptor[ENET_TX_RING_NUM];
    uint32_t tx_ring_num;

    uint32_t phy_status;
    uint32_t phy_control;
    uint32_t phy_advertise;
    uint32_t phy_int;
    uint32_t phy_int_mask;
    uint32_t phy_num;

    bool is_fec;

    /* Buffer used to assemble a Tx frame */
    uint8_t frame[ENET_MAX_FRAME_SIZE];
};

#endif
Commit	Line	Data
fcbd8018	1	/*
a699b410	2	* i.MX FEC/ENET Ethernet Controller emulation.
fcbd8018 JCD	3	*
	4	* Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
	5	*
	6	* Based on Coldfire Fast Ethernet Controller emulation.
	7	*
	8	* Copyright (c) 2007 CodeSourcery.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful, but WITHOUT
	16	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	17	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	18	* for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along
	21	* with this program; if not, see <http://www.gnu.org/licenses/>.
	22	*/
	23
	24	#ifndef IMX_FEC_H
	25	#define IMX_FEC_H
db1015e9	26	#include "qom/object.h"
fcbd8018 JCD	27
fcbd8018 JCD	28	#define TYPE_IMX_FEC "imx.fec"
db1015e9	29	typedef struct IMXFECState IMXFECState;
8110fa1d EH	30	DECLARE_INSTANCE_CHECKER(IMXFECState, IMX_FEC,
8110fa1d EH	31	TYPE_IMX_FEC)
fcbd8018	32
a699b410 JCD	33	#define TYPE_IMX_ENET "imx.enet"
a699b410 JCD	34
fcbd8018 JCD	35	#include "hw/sysbus.h"
	36	#include "net/net.h"
	37
db0de352 JCD	38	#define ENET_EIR 1
	39	#define ENET_EIMR 2
	40	#define ENET_RDAR 4
	41	#define ENET_TDAR 5
	42	#define ENET_ECR 9
	43	#define ENET_MMFR 16
	44	#define ENET_MSCR 17
	45	#define ENET_MIBC 25
	46	#define ENET_RCR 33
	47	#define ENET_TCR 49
	48	#define ENET_PALR 57
	49	#define ENET_PAUR 58
	50	#define ENET_OPD 59
	51	#define ENET_IAUR 70
	52	#define ENET_IALR 71
	53	#define ENET_GAUR 72
	54	#define ENET_GALR 73
	55	#define ENET_TFWR 81
	56	#define ENET_FRBR 83
	57	#define ENET_FRSR 84
f93f961c AS	58	#define ENET_TDSR1 89
f93f961c AS	59	#define ENET_TDSR2 92
db0de352 JCD	60	#define ENET_RDSR 96
	61	#define ENET_TDSR 97
	62	#define ENET_MRBR 98
a699b410 JCD	63	#define ENET_RSFL 100
	64	#define ENET_RSEM 101
	65	#define ENET_RAEM 102
	66	#define ENET_RAFL 103
	67	#define ENET_TSEM 104
	68	#define ENET_TAEM 105
	69	#define ENET_TAFL 106
	70	#define ENET_TIPG 107
	71	#define ENET_FTRL 108
	72	#define ENET_TACC 112
	73	#define ENET_RACC 113
f93f961c AS	74	#define ENET_TDAR1 121
f93f961c AS	75	#define ENET_TDAR2 123
db0de352 JCD	76	#define ENET_MIIGSK_CFGR 192
db0de352 JCD	77	#define ENET_MIIGSK_ENR 194
a699b410 JCD	78	#define ENET_ATCR 256
	79	#define ENET_ATVR 257
	80	#define ENET_ATOFF 258
	81	#define ENET_ATPER 259
	82	#define ENET_ATCOR 260
	83	#define ENET_ATINC 261
	84	#define ENET_ATSTMP 262
	85	#define ENET_TGSR 385
	86	#define ENET_TCSR0 386
	87	#define ENET_TCCR0 387
	88	#define ENET_TCSR1 388
	89	#define ENET_TCCR1 389
	90	#define ENET_TCSR2 390
	91	#define ENET_TCCR2 391
	92	#define ENET_TCSR3 392
	93	#define ENET_TCCR3 393
db0de352 JCD	94	#define ENET_MAX 400
db0de352 JCD	95
fcbd8018	96
a699b410	97	/* EIR and EIMR */
1bb3c371 JCD	98	#define ENET_INT_HB (1 << 31)
	99	#define ENET_INT_BABR (1 << 30)
	100	#define ENET_INT_BABT (1 << 29)
	101	#define ENET_INT_GRA (1 << 28)
	102	#define ENET_INT_TXF (1 << 27)
	103	#define ENET_INT_TXB (1 << 26)
	104	#define ENET_INT_RXF (1 << 25)
	105	#define ENET_INT_RXB (1 << 24)
	106	#define ENET_INT_MII (1 << 23)
	107	#define ENET_INT_EBERR (1 << 22)
	108	#define ENET_INT_LC (1 << 21)
	109	#define ENET_INT_RL (1 << 20)
	110	#define ENET_INT_UN (1 << 19)
a699b410 JCD	111	#define ENET_INT_PLR (1 << 18)
	112	#define ENET_INT_WAKEUP (1 << 17)
	113	#define ENET_INT_TS_AVAIL (1 << 16)
	114	#define ENET_INT_TS_TIMER (1 << 15)
f93f961c AS	115	#define ENET_INT_TXF2 (1 << 7)
	116	#define ENET_INT_TXB2 (1 << 6)
	117	#define ENET_INT_TXF1 (1 << 3)
	118	#define ENET_INT_TXB1 (1 << 2)
a699b410 JCD	119
	120	#define ENET_INT_MAC (ENET_INT_HB \| ENET_INT_BABR \| ENET_INT_BABT \| \
	121	ENET_INT_GRA \| ENET_INT_TXF \| ENET_INT_TXB \| \
	122	ENET_INT_RXF \| ENET_INT_RXB \| ENET_INT_MII \| \
	123	ENET_INT_EBERR \| ENET_INT_LC \| ENET_INT_RL \| \
	124	ENET_INT_UN \| ENET_INT_PLR \| ENET_INT_WAKEUP \| \
f93f961c AS	125	ENET_INT_TS_AVAIL \| ENET_INT_TXF1 \| \
f93f961c AS	126	ENET_INT_TXB1 \| ENET_INT_TXF2 \| ENET_INT_TXB2)
fcbd8018	127
db0de352 JCD	128	/* RDAR */
	129	#define ENET_RDAR_RDAR (1 << 24)
	130
	131	/* TDAR */
	132	#define ENET_TDAR_TDAR (1 << 24)
	133
a699b410	134	/* ECR */
1bb3c371 JCD	135	#define ENET_ECR_RESET (1 << 0)
1bb3c371 JCD	136	#define ENET_ECR_ETHEREN (1 << 1)
a699b410 JCD	137	#define ENET_ECR_MAGICEN (1 << 2)
	138	#define ENET_ECR_SLEEP (1 << 3)
	139	#define ENET_ECR_EN1588 (1 << 4)
	140	#define ENET_ECR_SPEED (1 << 5)
	141	#define ENET_ECR_DBGEN (1 << 6)
	142	#define ENET_ECR_STOPEN (1 << 7)
	143	#define ENET_ECR_DSBWP (1 << 8)
	144
	145	/* MIBC */
	146	#define ENET_MIBC_MIB_DIS (1 << 31)
	147	#define ENET_MIBC_MIB_IDLE (1 << 30)
	148	#define ENET_MIBC_MIB_CLEAR (1 << 29)
	149
	150	/* RCR */
	151	#define ENET_RCR_LOOP (1 << 0)
	152	#define ENET_RCR_DRT (1 << 1)
	153	#define ENET_RCR_MII_MODE (1 << 2)
	154	#define ENET_RCR_PROM (1 << 3)
	155	#define ENET_RCR_BC_REJ (1 << 4)
	156	#define ENET_RCR_FCE (1 << 5)
	157	#define ENET_RCR_RGMII_EN (1 << 6)
	158	#define ENET_RCR_RMII_MODE (1 << 8)
	159	#define ENET_RCR_RMII_10T (1 << 9)
	160	#define ENET_RCR_PADEN (1 << 12)
	161	#define ENET_RCR_PAUFWD (1 << 13)
	162	#define ENET_RCR_CRCFWD (1 << 14)
	163	#define ENET_RCR_CFEN (1 << 15)
	164	#define ENET_RCR_MAX_FL_SHIFT (16)
	165	#define ENET_RCR_MAX_FL_LENGTH (14)
	166	#define ENET_RCR_NLC (1 << 30)
	167	#define ENET_RCR_GRS (1 << 31)
	168
ff9a7fee AS	169	#define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH)
ff9a7fee AS	170
a699b410 JCD	171	/* TCR */
	172	#define ENET_TCR_GTS (1 << 0)
	173	#define ENET_TCR_FDEN (1 << 2)
	174	#define ENET_TCR_TFC_PAUSE (1 << 3)
	175	#define ENET_TCR_RFC_PAUSE (1 << 4)
	176	#define ENET_TCR_ADDSEL_SHIFT (5)
	177	#define ENET_TCR_ADDSEL_LENGTH (3)
	178	#define ENET_TCR_CRCFWD (1 << 9)
	179
	180	/* RDSR */
	181	#define ENET_TWFR_TFWR_SHIFT (0)
	182	#define ENET_TWFR_TFWR_LENGTH (6)
	183	#define ENET_TWFR_STRFWD (1 << 8)
fcbd8018	184
ebdd8cdd AS	185	#define ENET_RACC_SHIFT16 BIT(7)
ebdd8cdd AS	186
fcbd8018 JCD	187	/* Buffer Descriptor. */
	188	typedef struct {
	189	uint16_t length;
	190	uint16_t flags;
	191	uint32_t data;
	192	} IMXFECBufDesc;
	193
1bb3c371 JCD	194	#define ENET_BD_R (1 << 15)
	195	#define ENET_BD_E (1 << 15)
	196	#define ENET_BD_O1 (1 << 14)
	197	#define ENET_BD_W (1 << 13)
	198	#define ENET_BD_O2 (1 << 12)
	199	#define ENET_BD_L (1 << 11)
	200	#define ENET_BD_TC (1 << 10)
	201	#define ENET_BD_ABC (1 << 9)
	202	#define ENET_BD_M (1 << 8)
	203	#define ENET_BD_BC (1 << 7)
	204	#define ENET_BD_MC (1 << 6)
	205	#define ENET_BD_LG (1 << 5)
	206	#define ENET_BD_NO (1 << 4)
	207	#define ENET_BD_CR (1 << 2)
	208	#define ENET_BD_OV (1 << 1)
	209	#define ENET_BD_TR (1 << 0)
fcbd8018	210
a699b410 JCD	211	typedef struct {
	212	uint16_t length;
	213	uint16_t flags;
	214	uint32_t data;
	215	uint16_t status;
	216	uint16_t option;
	217	uint16_t checksum;
	218	uint16_t head_proto;
	219	uint32_t last_buffer;
	220	uint32_t timestamp;
	221	uint32_t reserved[2];
	222	} IMXENETBufDesc;
	223
	224	#define ENET_BD_ME (1 << 15)
	225	#define ENET_BD_TX_INT (1 << 14)
	226	#define ENET_BD_TS (1 << 13)
	227	#define ENET_BD_PINS (1 << 12)
	228	#define ENET_BD_IINS (1 << 11)
	229	#define ENET_BD_PE (1 << 10)
	230	#define ENET_BD_CE (1 << 9)
	231	#define ENET_BD_UC (1 << 8)
	232	#define ENET_BD_RX_INT (1 << 7)
	233
	234	#define ENET_BD_TXE (1 << 15)
	235	#define ENET_BD_UE (1 << 13)
	236	#define ENET_BD_EE (1 << 12)
	237	#define ENET_BD_FE (1 << 11)
	238	#define ENET_BD_LCE (1 << 10)
	239	#define ENET_BD_OE (1 << 9)
	240	#define ENET_BD_TSE (1 << 8)
	241	#define ENET_BD_ICE (1 << 5)
	242	#define ENET_BD_PCR (1 << 4)
	243	#define ENET_BD_VLAN (1 << 2)
	244	#define ENET_BD_IPV6 (1 << 1)
	245	#define ENET_BD_FRAG (1 << 0)
	246
	247	#define ENET_BD_BDU (1 << 31)
	248
f93f961c AS	249	#define ENET_TX_RING_NUM 3
f93f961c AS	250
831858ad	251	#define FSL_IMX25_FEC_SIZE 0x4000
f93f961c	252
db1015e9	253	struct IMXFECState {
fcbd8018 JCD	254	/< private >/
	255	SysBusDevice parent_obj;
	256
	257	/< public >/
	258	NICState *nic;
	259	NICConf conf;
a699b410	260	qemu_irq irq[2];
fcbd8018 JCD	261	MemoryRegion iomem;
fcbd8018 JCD	262
db0de352	263	uint32_t regs[ENET_MAX];
fcbd8018	264	uint32_t rx_descriptor;
f93f961c AS	265
	266	uint32_t tx_descriptor[ENET_TX_RING_NUM];
	267	uint32_t tx_ring_num;
fcbd8018 JCD	268
	269	uint32_t phy_status;
	270	uint32_t phy_control;
	271	uint32_t phy_advertise;
	272	uint32_t phy_int;
	273	uint32_t phy_int_mask;
461c51ad	274	uint32_t phy_num;
a699b410 JCD	275
a699b410 JCD	276	bool is_fec;
7bac20dc AS	277
	278	/* Buffer used to assemble a Tx frame */
	279	uint8_t frame[ENET_MAX_FRAME_SIZE];
db1015e9	280	};
fcbd8018 JCD	281
fcbd8018 JCD	282	#endif