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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
376253ec AL |
4 | #include "qemu-common.h" |
5 | ||
c759b24f | 6 | #include "hw/qdev.h" |
022c62cb | 7 | #include "exec/memory.h" |
9c17d615 | 8 | #include "sysemu/dma.h" |
cd9aa33e | 9 | #include "qapi/error.h" |
6b1b92d3 | 10 | |
87ecb68b | 11 | /* PCI includes legacy ISA access. */ |
0d09e41a | 12 | #include "hw/isa/isa.h" |
87ecb68b | 13 | |
c759b24f | 14 | #include "hw/pci/pcie.h" |
0428527c | 15 | |
87ecb68b PB |
16 | /* PCI bus */ |
17 | ||
3ae80618 AL |
18 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
19 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
20 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
90a20dbb | 21 | #define PCI_SLOT_MAX 32 |
6fa84913 | 22 | #define PCI_FUNC_MAX 8 |
3ae80618 | 23 | |
a770dc7e | 24 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
c759b24f | 25 | #include "hw/pci/pci_ids.h" |
173a543b | 26 | |
a770dc7e | 27 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 28 | |
a770dc7e AL |
29 | /* IBM (0x1014) */ |
30 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 31 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 32 | |
a770dc7e | 33 | /* Hitachi (0x1054) */ |
deb54399 | 34 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 35 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 36 | |
a770dc7e | 37 | /* Apple (0x106b) */ |
4ebcf884 BS |
38 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
39 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
40 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 41 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 42 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 43 | |
a770dc7e AL |
44 | /* Realtek (0x10ec) */ |
45 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 46 | |
a770dc7e AL |
47 | /* Xilinx (0x10ee) */ |
48 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 49 | |
a770dc7e AL |
50 | /* Marvell (0x11ab) */ |
51 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 52 | |
a770dc7e | 53 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
54 | #define PCI_VENDOR_ID_QEMU 0x1234 |
55 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
56 | ||
a770dc7e | 57 | /* VMWare (0x15ad) */ |
deb54399 AL |
58 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
59 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
60 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
61 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
62 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
881d588a | 63 | #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 |
deb54399 | 64 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
786fd2b0 | 65 | #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 |
deb54399 | 66 | |
cef3017c | 67 | /* Intel (0x8086) */ |
a770dc7e | 68 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
d6fd1e66 | 69 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
1a5a86fb | 70 | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
74c62ba8 | 71 | |
deb54399 | 72 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
73 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
74 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
75 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
76 | ||
77 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
78 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
79 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 80 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
973abc7f | 81 | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
16c915ba | 82 | #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
13744bd0 | 83 | #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 |
d350d97d | 84 | |
5c03a254 PB |
85 | #define PCI_VENDOR_ID_REDHAT 0x1b36 |
86 | #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 | |
87 | #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 | |
88 | #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 | |
89 | #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 | |
22773d60 | 90 | #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 |
5aa81360 | 91 | #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 |
bf439db4 | 92 | #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 |
5c03a254 PB |
93 | #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 |
94 | ||
4f8589e1 | 95 | #define FMT_PCIBUS PRIx64 |
6e355d90 | 96 | |
87ecb68b PB |
97 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
98 | uint32_t address, uint32_t data, int len); | |
99 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
100 | uint32_t address, int len); | |
101 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 102 | pcibus_t addr, pcibus_t size, int type); |
f90c2bcd | 103 | typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b | 104 | |
87ecb68b | 105 | typedef struct PCIIORegion { |
6e355d90 IY |
106 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
107 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) | |
108 | pcibus_t size; | |
87ecb68b | 109 | uint8_t type; |
79ff8cb0 | 110 | MemoryRegion *memory; |
5968eca3 | 111 | MemoryRegion *address_space; |
87ecb68b PB |
112 | } PCIIORegion; |
113 | ||
114 | #define PCI_ROM_SLOT 6 | |
115 | #define PCI_NUM_REGIONS 7 | |
116 | ||
e01fd687 AW |
117 | enum { |
118 | QEMU_PCI_VGA_MEM, | |
119 | QEMU_PCI_VGA_IO_LO, | |
120 | QEMU_PCI_VGA_IO_HI, | |
121 | QEMU_PCI_VGA_NUM_REGIONS, | |
122 | }; | |
123 | ||
124 | #define QEMU_PCI_VGA_MEM_BASE 0xa0000 | |
125 | #define QEMU_PCI_VGA_MEM_SIZE 0x20000 | |
126 | #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 | |
127 | #define QEMU_PCI_VGA_IO_LO_SIZE 0xc | |
128 | #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 | |
129 | #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 | |
130 | ||
c759b24f | 131 | #include "hw/pci/pci_regs.h" |
fb58a897 IY |
132 | |
133 | /* PCI HEADER_TYPE */ | |
6407f373 | 134 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
8098ed41 | 135 | |
b7ee1603 MT |
136 | /* Size of the standard PCI config header */ |
137 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
138 | /* Size of the standard PCI config space */ | |
139 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
a9f49946 IY |
140 | /* Size of the standart PCIe config space: 4KB */ |
141 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 | |
b7ee1603 | 142 | |
e369cad7 IY |
143 | #define PCI_NUM_PINS 4 /* A-D */ |
144 | ||
02eb84d0 MT |
145 | /* Bits in cap_present field. */ |
146 | enum { | |
e4c7d2ae IY |
147 | QEMU_PCI_CAP_MSI = 0x1, |
148 | QEMU_PCI_CAP_MSIX = 0x2, | |
149 | QEMU_PCI_CAP_EXPRESS = 0x4, | |
49823868 IY |
150 | |
151 | /* multifunction capable device */ | |
e4c7d2ae | 152 | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
49823868 | 153 | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), |
b1aeb926 IY |
154 | |
155 | /* command register SERR bit enabled */ | |
156 | #define QEMU_PCI_CAP_SERR_BITNR 4 | |
157 | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), | |
1dc324d2 MT |
158 | /* Standard hot plug controller. */ |
159 | #define QEMU_PCI_SHPC_BITNR 5 | |
160 | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), | |
762833b3 MT |
161 | #define QEMU_PCI_SLOTID_BITNR 6 |
162 | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), | |
f23b6bdc MA |
163 | /* PCI Express capability - Power Controller Present */ |
164 | #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 | |
165 | QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), | |
02eb84d0 MT |
166 | }; |
167 | ||
40021f08 AL |
168 | #define TYPE_PCI_DEVICE "pci-device" |
169 | #define PCI_DEVICE(obj) \ | |
170 | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) | |
171 | #define PCI_DEVICE_CLASS(klass) \ | |
172 | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) | |
173 | #define PCI_DEVICE_GET_CLASS(obj) \ | |
174 | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) | |
175 | ||
3afa9bb4 MT |
176 | typedef struct PCIINTxRoute { |
177 | enum { | |
178 | PCI_INTX_ENABLED, | |
179 | PCI_INTX_INVERTED, | |
180 | PCI_INTX_DISABLED, | |
181 | } mode; | |
182 | int irq; | |
183 | } PCIINTxRoute; | |
184 | ||
40021f08 AL |
185 | typedef struct PCIDeviceClass { |
186 | DeviceClass parent_class; | |
187 | ||
188 | int (*init)(PCIDevice *dev); | |
189 | PCIUnregisterFunc *exit; | |
190 | PCIConfigReadFunc *config_read; | |
191 | PCIConfigWriteFunc *config_write; | |
192 | ||
193 | uint16_t vendor_id; | |
194 | uint16_t device_id; | |
195 | uint8_t revision; | |
196 | uint16_t class_id; | |
197 | uint16_t subsystem_vendor_id; /* only for header type = 0 */ | |
198 | uint16_t subsystem_id; /* only for header type = 0 */ | |
199 | ||
200 | /* | |
201 | * pci-to-pci bridge or normal device. | |
202 | * This doesn't mean pci host switch. | |
203 | * When card bus bridge is supported, this would be enhanced. | |
204 | */ | |
205 | int is_bridge; | |
206 | ||
207 | /* pcie stuff */ | |
208 | int is_express; /* is this device pci express? */ | |
209 | ||
40021f08 AL |
210 | /* rom bar */ |
211 | const char *romfile; | |
212 | } PCIDeviceClass; | |
213 | ||
0ae16251 | 214 | typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
2cdfe53c JK |
215 | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
216 | MSIMessage msg); | |
217 | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); | |
bbef882c MT |
218 | typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, |
219 | unsigned int vector_start, | |
220 | unsigned int vector_end); | |
2cdfe53c | 221 | |
87ecb68b | 222 | struct PCIDevice { |
6b1b92d3 | 223 | DeviceState qdev; |
5fa45de5 | 224 | |
87ecb68b | 225 | /* PCI config space */ |
a9f49946 | 226 | uint8_t *config; |
b7ee1603 | 227 | |
ebabb67a | 228 | /* Used to enable config checks on load. Note that writable bits are |
bd4b65ee | 229 | * never checked even if set in cmask. */ |
a9f49946 | 230 | uint8_t *cmask; |
bd4b65ee | 231 | |
b7ee1603 | 232 | /* Used to implement R/W bytes */ |
a9f49946 | 233 | uint8_t *wmask; |
87ecb68b | 234 | |
92ba5f51 IY |
235 | /* Used to implement RW1C(Write 1 to Clear) bytes */ |
236 | uint8_t *w1cmask; | |
237 | ||
6f4cbd39 | 238 | /* Used to allocate config space for capabilities. */ |
a9f49946 | 239 | uint8_t *used; |
6f4cbd39 | 240 | |
87ecb68b PB |
241 | /* the following fields are read only */ |
242 | PCIBus *bus; | |
09f1bbcd | 243 | int32_t devfn; |
87ecb68b PB |
244 | char name[64]; |
245 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
817dcc53 | 246 | AddressSpace bus_master_as; |
1c380f94 | 247 | MemoryRegion bus_master_enable_region; |
87ecb68b PB |
248 | |
249 | /* do not access the following fields */ | |
250 | PCIConfigReadFunc *config_read; | |
251 | PCIConfigWriteFunc *config_write; | |
87ecb68b | 252 | |
e01fd687 AW |
253 | /* Legacy PCI VGA regions */ |
254 | MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; | |
255 | bool has_vga; | |
256 | ||
87ecb68b | 257 | /* Current IRQ levels. Used internally by the generic PCI code. */ |
d036bb21 | 258 | uint8_t irq_state; |
02eb84d0 MT |
259 | |
260 | /* Capability bits */ | |
261 | uint32_t cap_present; | |
262 | ||
263 | /* Offset of MSI-X capability in config space */ | |
264 | uint8_t msix_cap; | |
265 | ||
266 | /* MSI-X entries */ | |
267 | int msix_entries_nr; | |
268 | ||
d35e428c AW |
269 | /* Space to store MSIX table & pending bit array */ |
270 | uint8_t *msix_table; | |
271 | uint8_t *msix_pba; | |
53f94925 AW |
272 | /* MemoryRegion container for msix exclusive BAR setup */ |
273 | MemoryRegion msix_exclusive_bar; | |
d35e428c AW |
274 | /* Memory Regions for MSIX table and pending bit entries. */ |
275 | MemoryRegion msix_table_mmio; | |
276 | MemoryRegion msix_pba_mmio; | |
02eb84d0 MT |
277 | /* Reference-count for entries actually in use by driver. */ |
278 | unsigned *msix_entry_used; | |
50322249 MT |
279 | /* MSIX function mask set or MSIX disabled */ |
280 | bool msix_function_masked; | |
f16c4abf JQ |
281 | /* Version id needed for VMState */ |
282 | int32_t version_id; | |
c2039bd0 | 283 | |
e4c7d2ae IY |
284 | /* Offset of MSI capability in config space */ |
285 | uint8_t msi_cap; | |
286 | ||
0428527c IY |
287 | /* PCI Express */ |
288 | PCIExpressDevice exp; | |
289 | ||
1dc324d2 MT |
290 | /* SHPC */ |
291 | SHPCDevice *shpc; | |
292 | ||
c2039bd0 | 293 | /* Location of option rom */ |
8c52c8f3 | 294 | char *romfile; |
14caaf7f AK |
295 | bool has_rom; |
296 | MemoryRegion rom; | |
88169ddf | 297 | uint32_t rom_bar; |
2cdfe53c | 298 | |
0ae16251 JK |
299 | /* INTx routing notifier */ |
300 | PCIINTxRoutingNotifier intx_routing_notifier; | |
301 | ||
2cdfe53c JK |
302 | /* MSI-X notifiers */ |
303 | MSIVectorUseNotifier msix_vector_use_notifier; | |
304 | MSIVectorReleaseNotifier msix_vector_release_notifier; | |
bbef882c | 305 | MSIVectorPollNotifier msix_vector_poll_notifier; |
87ecb68b PB |
306 | }; |
307 | ||
e824b2cc AK |
308 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
309 | uint8_t attr, MemoryRegion *memory); | |
e01fd687 AW |
310 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, |
311 | MemoryRegion *io_lo, MemoryRegion *io_hi); | |
312 | void pci_unregister_vga(PCIDevice *pci_dev); | |
16a96f28 | 313 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); |
87ecb68b | 314 | |
ca77089d IY |
315 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
316 | uint8_t offset, uint8_t size); | |
cd9aa33e LE |
317 | int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, |
318 | uint8_t offset, uint8_t size, | |
319 | Error **errp); | |
6f4cbd39 MT |
320 | |
321 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
322 | ||
6f4cbd39 MT |
323 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
324 | ||
325 | ||
87ecb68b PB |
326 | uint32_t pci_default_read_config(PCIDevice *d, |
327 | uint32_t address, int len); | |
328 | void pci_default_write_config(PCIDevice *d, | |
329 | uint32_t address, uint32_t val, int len); | |
330 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
331 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
f5e6fed8 | 332 | MemoryRegion *pci_address_space(PCIDevice *dev); |
e11d6439 | 333 | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
87ecb68b | 334 | |
5d4e84c8 | 335 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
87ecb68b | 336 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
3afa9bb4 | 337 | typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
e927d487 | 338 | |
cf09458d AW |
339 | #define TYPE_PCI_BUS "PCI" |
340 | #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) | |
341 | #define TYPE_PCIE_BUS "PCIE" | |
342 | ||
8c0bf9e2 | 343 | bool pci_bus_is_express(PCIBus *bus); |
0889464a | 344 | bool pci_bus_is_root(PCIBus *bus); |
dd301ca6 | 345 | void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, |
1e39101c | 346 | const char *name, |
aee97b84 AK |
347 | MemoryRegion *address_space_mem, |
348 | MemoryRegion *address_space_io, | |
60a0e443 | 349 | uint8_t devfn_min, const char *typename); |
1e39101c | 350 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
aee97b84 AK |
351 | MemoryRegion *address_space_mem, |
352 | MemoryRegion *address_space_io, | |
60a0e443 | 353 | uint8_t devfn_min, const char *typename); |
21eea4b3 GH |
354 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
355 | void *irq_opaque, int nirq); | |
9ddf8437 | 356 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
91e56159 IY |
357 | /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ |
358 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); | |
02e2da45 PB |
359 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
360 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 361 | void *irq_opaque, |
aee97b84 AK |
362 | MemoryRegion *address_space_mem, |
363 | MemoryRegion *address_space_io, | |
60a0e443 | 364 | uint8_t devfn_min, int nirq, const char *typename); |
3afa9bb4 MT |
365 | void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); |
366 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); | |
d6e65d54 | 367 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); |
0ae16251 JK |
368 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus); |
369 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
370 | PCIINTxRoutingNotifier notifier); | |
0ead87c8 | 371 | void pci_device_reset(PCIDevice *dev); |
87ecb68b | 372 | |
29b358f9 DG |
373 | PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, |
374 | const char *default_model, | |
5607c388 | 375 | const char *default_devaddr); |
29b358f9 DG |
376 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
377 | const char *default_model, | |
07caea31 | 378 | const char *default_devaddr); |
129d42fb AJ |
379 | |
380 | PCIDevice *pci_vga_init(PCIBus *bus); | |
381 | ||
87ecb68b | 382 | int pci_bus_num(PCIBus *s); |
7aa8cbb9 AP |
383 | void pci_for_each_device(PCIBus *bus, int bus_num, |
384 | void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), | |
385 | void *opaque); | |
eb0acfdd MT |
386 | void pci_for_each_bus_depth_first(PCIBus *bus, |
387 | void *(*begin)(PCIBus *bus, void *parent_state), | |
388 | void (*end)(PCIBus *bus, void *state), | |
389 | void *parent_state); | |
390 | ||
391 | /* Use this wrapper when specific scan order is not required. */ | |
392 | static inline | |
393 | void pci_for_each_bus(PCIBus *bus, | |
394 | void (*fn)(PCIBus *bus, void *opaque), | |
395 | void *opaque) | |
396 | { | |
397 | pci_for_each_bus_depth_first(bus, NULL, fn, opaque); | |
398 | } | |
399 | ||
1ef7a2a2 | 400 | PCIBus *pci_find_primary_bus(void); |
c473d18d | 401 | PCIBus *pci_device_root_bus(const PCIDevice *d); |
568f0690 | 402 | const char *pci_root_bus_path(PCIDevice *dev); |
5256d8bf | 403 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); |
f3006dd1 | 404 | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
85c6e4fa | 405 | PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr); |
43864069 | 406 | void pci_bus_get_w64_range(PCIBus *bus, Range *range); |
87ecb68b | 407 | |
6ac363b5 DG |
408 | int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
409 | unsigned int *slotp, unsigned int *funcp); | |
880345c4 | 410 | |
4c92325b IY |
411 | void pci_device_deassert_intx(PCIDevice *dev); |
412 | ||
e00387d5 | 413 | typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); |
5fa45de5 | 414 | |
9eda7d37 | 415 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); |
e00387d5 | 416 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); |
5fa45de5 | 417 | |
64d50b8b MT |
418 | static inline void |
419 | pci_set_byte(uint8_t *config, uint8_t val) | |
420 | { | |
421 | *config = val; | |
422 | } | |
423 | ||
424 | static inline uint8_t | |
cb95c2e4 | 425 | pci_get_byte(const uint8_t *config) |
64d50b8b MT |
426 | { |
427 | return *config; | |
428 | } | |
429 | ||
14e12559 MT |
430 | static inline void |
431 | pci_set_word(uint8_t *config, uint16_t val) | |
432 | { | |
587ae227 | 433 | stw_le_p(config, val); |
14e12559 MT |
434 | } |
435 | ||
436 | static inline uint16_t | |
cb95c2e4 | 437 | pci_get_word(const uint8_t *config) |
14e12559 | 438 | { |
c65e5de9 | 439 | return lduw_le_p(config); |
14e12559 MT |
440 | } |
441 | ||
442 | static inline void | |
443 | pci_set_long(uint8_t *config, uint32_t val) | |
444 | { | |
6e931878 | 445 | stl_le_p(config, val); |
14e12559 MT |
446 | } |
447 | ||
448 | static inline uint32_t | |
cb95c2e4 | 449 | pci_get_long(const uint8_t *config) |
14e12559 | 450 | { |
f567656a | 451 | return ldl_le_p(config); |
14e12559 MT |
452 | } |
453 | ||
fb5ce7d2 IY |
454 | static inline void |
455 | pci_set_quad(uint8_t *config, uint64_t val) | |
456 | { | |
457 | cpu_to_le64w((uint64_t *)config, val); | |
458 | } | |
459 | ||
460 | static inline uint64_t | |
cb95c2e4 | 461 | pci_get_quad(const uint8_t *config) |
fb5ce7d2 | 462 | { |
cb95c2e4 | 463 | return le64_to_cpup((const uint64_t *)config); |
fb5ce7d2 IY |
464 | } |
465 | ||
deb54399 AL |
466 | static inline void |
467 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
468 | { | |
14e12559 | 469 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
470 | } |
471 | ||
472 | static inline void | |
473 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
474 | { | |
14e12559 | 475 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
476 | } |
477 | ||
cf602c7b IE |
478 | static inline void |
479 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) | |
480 | { | |
481 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); | |
482 | } | |
483 | ||
173a543b BS |
484 | static inline void |
485 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
486 | { | |
14e12559 | 487 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
488 | } |
489 | ||
cf602c7b IE |
490 | static inline void |
491 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) | |
492 | { | |
493 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); | |
494 | } | |
495 | ||
496 | static inline void | |
497 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) | |
498 | { | |
499 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); | |
500 | } | |
501 | ||
aabcf526 IY |
502 | /* |
503 | * helper functions to do bit mask operation on configuration space. | |
504 | * Just to set bit, use test-and-set and discard returned value. | |
505 | * Just to clear bit, use test-and-clear and discard returned value. | |
506 | * NOTE: They aren't atomic. | |
507 | */ | |
508 | static inline uint8_t | |
509 | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) | |
510 | { | |
511 | uint8_t val = pci_get_byte(config); | |
512 | pci_set_byte(config, val & ~mask); | |
513 | return val & mask; | |
514 | } | |
515 | ||
516 | static inline uint8_t | |
517 | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) | |
518 | { | |
519 | uint8_t val = pci_get_byte(config); | |
520 | pci_set_byte(config, val | mask); | |
521 | return val & mask; | |
522 | } | |
523 | ||
524 | static inline uint16_t | |
525 | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) | |
526 | { | |
527 | uint16_t val = pci_get_word(config); | |
528 | pci_set_word(config, val & ~mask); | |
529 | return val & mask; | |
530 | } | |
531 | ||
532 | static inline uint16_t | |
533 | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) | |
534 | { | |
535 | uint16_t val = pci_get_word(config); | |
536 | pci_set_word(config, val | mask); | |
537 | return val & mask; | |
538 | } | |
539 | ||
540 | static inline uint32_t | |
541 | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) | |
542 | { | |
543 | uint32_t val = pci_get_long(config); | |
544 | pci_set_long(config, val & ~mask); | |
545 | return val & mask; | |
546 | } | |
547 | ||
548 | static inline uint32_t | |
549 | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) | |
550 | { | |
551 | uint32_t val = pci_get_long(config); | |
552 | pci_set_long(config, val | mask); | |
553 | return val & mask; | |
554 | } | |
555 | ||
556 | static inline uint64_t | |
557 | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) | |
558 | { | |
559 | uint64_t val = pci_get_quad(config); | |
560 | pci_set_quad(config, val & ~mask); | |
561 | return val & mask; | |
562 | } | |
563 | ||
564 | static inline uint64_t | |
565 | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) | |
566 | { | |
567 | uint64_t val = pci_get_quad(config); | |
568 | pci_set_quad(config, val | mask); | |
569 | return val & mask; | |
570 | } | |
571 | ||
c9f50cea MT |
572 | /* Access a register specified by a mask */ |
573 | static inline void | |
574 | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) | |
575 | { | |
576 | uint8_t val = pci_get_byte(config); | |
577 | uint8_t rval = reg << (ffs(mask) - 1); | |
578 | pci_set_byte(config, (~mask & val) | (mask & rval)); | |
579 | } | |
580 | ||
581 | static inline uint8_t | |
582 | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) | |
583 | { | |
584 | uint8_t val = pci_get_byte(config); | |
585 | return (val & mask) >> (ffs(mask) - 1); | |
586 | } | |
587 | ||
588 | static inline void | |
589 | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) | |
590 | { | |
591 | uint16_t val = pci_get_word(config); | |
592 | uint16_t rval = reg << (ffs(mask) - 1); | |
593 | pci_set_word(config, (~mask & val) | (mask & rval)); | |
594 | } | |
595 | ||
596 | static inline uint16_t | |
597 | pci_get_word_by_mask(uint8_t *config, uint16_t mask) | |
598 | { | |
599 | uint16_t val = pci_get_word(config); | |
600 | return (val & mask) >> (ffs(mask) - 1); | |
601 | } | |
602 | ||
603 | static inline void | |
604 | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) | |
605 | { | |
606 | uint32_t val = pci_get_long(config); | |
607 | uint32_t rval = reg << (ffs(mask) - 1); | |
608 | pci_set_long(config, (~mask & val) | (mask & rval)); | |
609 | } | |
610 | ||
611 | static inline uint32_t | |
612 | pci_get_long_by_mask(uint8_t *config, uint32_t mask) | |
613 | { | |
614 | uint32_t val = pci_get_long(config); | |
615 | return (val & mask) >> (ffs(mask) - 1); | |
616 | } | |
617 | ||
618 | static inline void | |
619 | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) | |
620 | { | |
621 | uint64_t val = pci_get_quad(config); | |
622 | uint64_t rval = reg << (ffs(mask) - 1); | |
623 | pci_set_quad(config, (~mask & val) | (mask & rval)); | |
624 | } | |
625 | ||
626 | static inline uint64_t | |
627 | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) | |
628 | { | |
629 | uint64_t val = pci_get_quad(config); | |
630 | return (val & mask) >> (ffs(mask) - 1); | |
631 | } | |
632 | ||
49823868 IY |
633 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
634 | const char *name); | |
635 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, | |
636 | bool multifunction, | |
637 | const char *name); | |
499cf102 | 638 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
6b1b92d3 PB |
639 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
640 | ||
d98f08f5 MA |
641 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev); |
642 | void pci_set_irq(PCIDevice *pci_dev, int level); | |
643 | ||
644 | static inline void pci_irq_assert(PCIDevice *pci_dev) | |
645 | { | |
646 | pci_set_irq(pci_dev, 1); | |
647 | } | |
648 | ||
649 | static inline void pci_irq_deassert(PCIDevice *pci_dev) | |
650 | { | |
651 | pci_set_irq(pci_dev, 0); | |
652 | } | |
653 | ||
654 | /* | |
655 | * FIXME: PCI does not work this way. | |
656 | * All the callers to this method should be fixed. | |
657 | */ | |
658 | static inline void pci_irq_pulse(PCIDevice *pci_dev) | |
659 | { | |
660 | pci_irq_assert(pci_dev); | |
661 | pci_irq_deassert(pci_dev); | |
662 | } | |
663 | ||
3c18685f | 664 | static inline int pci_is_express(const PCIDevice *d) |
a9f49946 IY |
665 | { |
666 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; | |
667 | } | |
668 | ||
3c18685f | 669 | static inline uint32_t pci_config_size(const PCIDevice *d) |
a9f49946 IY |
670 | { |
671 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; | |
672 | } | |
673 | ||
ec174575 | 674 | /* DMA access functions */ |
df32fd1c | 675 | static inline AddressSpace *pci_get_address_space(PCIDevice *dev) |
d86a77f8 | 676 | { |
df32fd1c | 677 | return &dev->bus_master_as; |
d86a77f8 DG |
678 | } |
679 | ||
ec174575 DG |
680 | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
681 | void *buf, dma_addr_t len, DMADirection dir) | |
682 | { | |
df32fd1c | 683 | dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); |
ec174575 DG |
684 | return 0; |
685 | } | |
686 | ||
687 | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, | |
688 | void *buf, dma_addr_t len) | |
689 | { | |
690 | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); | |
691 | } | |
692 | ||
693 | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, | |
694 | const void *buf, dma_addr_t len) | |
695 | { | |
696 | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); | |
697 | } | |
698 | ||
699 | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ | |
700 | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ | |
701 | dma_addr_t addr) \ | |
702 | { \ | |
df32fd1c | 703 | return ld##_l##_dma(pci_get_address_space(dev), addr); \ |
ec174575 DG |
704 | } \ |
705 | static inline void st##_s##_pci_dma(PCIDevice *dev, \ | |
d86a77f8 | 706 | dma_addr_t addr, uint##_bits##_t val) \ |
ec174575 | 707 | { \ |
df32fd1c | 708 | st##_s##_dma(pci_get_address_space(dev), addr, val); \ |
ec174575 DG |
709 | } |
710 | ||
711 | PCI_DMA_DEFINE_LDST(ub, b, 8); | |
712 | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) | |
713 | PCI_DMA_DEFINE_LDST(l_le, l_le, 32); | |
714 | PCI_DMA_DEFINE_LDST(q_le, q_le, 64); | |
715 | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) | |
716 | PCI_DMA_DEFINE_LDST(l_be, l_be, 32); | |
717 | PCI_DMA_DEFINE_LDST(q_be, q_be, 64); | |
718 | ||
719 | #undef PCI_DMA_DEFINE_LDST | |
720 | ||
721 | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, | |
722 | dma_addr_t *plen, DMADirection dir) | |
723 | { | |
ec174575 DG |
724 | void *buf; |
725 | ||
df32fd1c | 726 | buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); |
ec174575 DG |
727 | return buf; |
728 | } | |
729 | ||
730 | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, | |
731 | DMADirection dir, dma_addr_t access_len) | |
732 | { | |
df32fd1c | 733 | dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); |
ec174575 DG |
734 | } |
735 | ||
736 | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, | |
737 | int alloc_hint) | |
738 | { | |
f487b677 | 739 | qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); |
ec174575 DG |
740 | } |
741 | ||
701a8f76 PB |
742 | extern const VMStateDescription vmstate_pci_device; |
743 | ||
744 | #define VMSTATE_PCI_DEVICE(_field, _state) { \ | |
745 | .name = (stringify(_field)), \ | |
746 | .size = sizeof(PCIDevice), \ | |
747 | .vmsd = &vmstate_pci_device, \ | |
748 | .flags = VMS_STRUCT, \ | |
749 | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ | |
750 | } | |
751 | ||
752 | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ | |
753 | .name = (stringify(_field)), \ | |
754 | .size = sizeof(PCIDevice), \ | |
755 | .vmsd = &vmstate_pci_device, \ | |
756 | .flags = VMS_STRUCT|VMS_POINTER, \ | |
757 | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ | |
758 | } | |
759 | ||
87ecb68b | 760 | #endif |