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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
376253ec AL |
4 | #include "qemu-common.h" |
5 | ||
c759b24f | 6 | #include "hw/qdev.h" |
022c62cb | 7 | #include "exec/memory.h" |
9c17d615 | 8 | #include "sysemu/dma.h" |
6b1b92d3 | 9 | |
87ecb68b | 10 | /* PCI includes legacy ISA access. */ |
0d09e41a | 11 | #include "hw/isa/isa.h" |
87ecb68b | 12 | |
c759b24f | 13 | #include "hw/pci/pcie.h" |
0428527c | 14 | |
87ecb68b PB |
15 | /* PCI bus */ |
16 | ||
3ae80618 AL |
17 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
18 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
19 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
90a20dbb | 20 | #define PCI_SLOT_MAX 32 |
6fa84913 | 21 | #define PCI_FUNC_MAX 8 |
3ae80618 | 22 | |
a770dc7e | 23 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
c759b24f | 24 | #include "hw/pci/pci_ids.h" |
173a543b | 25 | |
a770dc7e | 26 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 27 | |
a770dc7e AL |
28 | /* IBM (0x1014) */ |
29 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 30 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 31 | |
a770dc7e | 32 | /* Hitachi (0x1054) */ |
deb54399 | 33 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 34 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 35 | |
a770dc7e | 36 | /* Apple (0x106b) */ |
4ebcf884 BS |
37 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
38 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
39 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 40 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 41 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 42 | |
a770dc7e AL |
43 | /* Realtek (0x10ec) */ |
44 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 45 | |
a770dc7e AL |
46 | /* Xilinx (0x10ee) */ |
47 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 48 | |
a770dc7e AL |
49 | /* Marvell (0x11ab) */ |
50 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 51 | |
a770dc7e | 52 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
53 | #define PCI_VENDOR_ID_QEMU 0x1234 |
54 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
55 | ||
a770dc7e | 56 | /* VMWare (0x15ad) */ |
deb54399 AL |
57 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
58 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
59 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
60 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
61 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
881d588a | 62 | #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 |
deb54399 | 63 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
786fd2b0 | 64 | #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 |
deb54399 | 65 | |
cef3017c | 66 | /* Intel (0x8086) */ |
a770dc7e | 67 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
d6fd1e66 | 68 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
1a5a86fb | 69 | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
74c62ba8 | 70 | |
deb54399 | 71 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
72 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
73 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
74 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
75 | ||
76 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
77 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
78 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 79 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
973abc7f | 80 | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
16c915ba | 81 | #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
13744bd0 | 82 | #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 |
d350d97d | 83 | |
5c03a254 PB |
84 | #define PCI_VENDOR_ID_REDHAT 0x1b36 |
85 | #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 | |
86 | #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 | |
87 | #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 | |
88 | #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 | |
22773d60 | 89 | #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 |
5c03a254 PB |
90 | #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 |
91 | ||
4f8589e1 | 92 | #define FMT_PCIBUS PRIx64 |
6e355d90 | 93 | |
87ecb68b PB |
94 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
95 | uint32_t address, uint32_t data, int len); | |
96 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
97 | uint32_t address, int len); | |
98 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 99 | pcibus_t addr, pcibus_t size, int type); |
f90c2bcd | 100 | typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b | 101 | |
87ecb68b | 102 | typedef struct PCIIORegion { |
6e355d90 IY |
103 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
104 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) | |
105 | pcibus_t size; | |
87ecb68b | 106 | uint8_t type; |
79ff8cb0 | 107 | MemoryRegion *memory; |
5968eca3 | 108 | MemoryRegion *address_space; |
87ecb68b PB |
109 | } PCIIORegion; |
110 | ||
111 | #define PCI_ROM_SLOT 6 | |
112 | #define PCI_NUM_REGIONS 7 | |
113 | ||
e01fd687 AW |
114 | enum { |
115 | QEMU_PCI_VGA_MEM, | |
116 | QEMU_PCI_VGA_IO_LO, | |
117 | QEMU_PCI_VGA_IO_HI, | |
118 | QEMU_PCI_VGA_NUM_REGIONS, | |
119 | }; | |
120 | ||
121 | #define QEMU_PCI_VGA_MEM_BASE 0xa0000 | |
122 | #define QEMU_PCI_VGA_MEM_SIZE 0x20000 | |
123 | #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 | |
124 | #define QEMU_PCI_VGA_IO_LO_SIZE 0xc | |
125 | #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 | |
126 | #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 | |
127 | ||
c759b24f | 128 | #include "hw/pci/pci_regs.h" |
fb58a897 IY |
129 | |
130 | /* PCI HEADER_TYPE */ | |
6407f373 | 131 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
8098ed41 | 132 | |
b7ee1603 MT |
133 | /* Size of the standard PCI config header */ |
134 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
135 | /* Size of the standard PCI config space */ | |
136 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
a9f49946 IY |
137 | /* Size of the standart PCIe config space: 4KB */ |
138 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 | |
b7ee1603 | 139 | |
e369cad7 IY |
140 | #define PCI_NUM_PINS 4 /* A-D */ |
141 | ||
02eb84d0 MT |
142 | /* Bits in cap_present field. */ |
143 | enum { | |
e4c7d2ae IY |
144 | QEMU_PCI_CAP_MSI = 0x1, |
145 | QEMU_PCI_CAP_MSIX = 0x2, | |
146 | QEMU_PCI_CAP_EXPRESS = 0x4, | |
49823868 IY |
147 | |
148 | /* multifunction capable device */ | |
e4c7d2ae | 149 | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
49823868 | 150 | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), |
b1aeb926 IY |
151 | |
152 | /* command register SERR bit enabled */ | |
153 | #define QEMU_PCI_CAP_SERR_BITNR 4 | |
154 | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), | |
1dc324d2 MT |
155 | /* Standard hot plug controller. */ |
156 | #define QEMU_PCI_SHPC_BITNR 5 | |
157 | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), | |
762833b3 MT |
158 | #define QEMU_PCI_SLOTID_BITNR 6 |
159 | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), | |
02eb84d0 MT |
160 | }; |
161 | ||
40021f08 AL |
162 | #define TYPE_PCI_DEVICE "pci-device" |
163 | #define PCI_DEVICE(obj) \ | |
164 | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) | |
165 | #define PCI_DEVICE_CLASS(klass) \ | |
166 | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) | |
167 | #define PCI_DEVICE_GET_CLASS(obj) \ | |
168 | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) | |
169 | ||
3afa9bb4 MT |
170 | typedef struct PCIINTxRoute { |
171 | enum { | |
172 | PCI_INTX_ENABLED, | |
173 | PCI_INTX_INVERTED, | |
174 | PCI_INTX_DISABLED, | |
175 | } mode; | |
176 | int irq; | |
177 | } PCIINTxRoute; | |
178 | ||
40021f08 AL |
179 | typedef struct PCIDeviceClass { |
180 | DeviceClass parent_class; | |
181 | ||
182 | int (*init)(PCIDevice *dev); | |
183 | PCIUnregisterFunc *exit; | |
184 | PCIConfigReadFunc *config_read; | |
185 | PCIConfigWriteFunc *config_write; | |
186 | ||
187 | uint16_t vendor_id; | |
188 | uint16_t device_id; | |
189 | uint8_t revision; | |
190 | uint16_t class_id; | |
191 | uint16_t subsystem_vendor_id; /* only for header type = 0 */ | |
192 | uint16_t subsystem_id; /* only for header type = 0 */ | |
193 | ||
194 | /* | |
195 | * pci-to-pci bridge or normal device. | |
196 | * This doesn't mean pci host switch. | |
197 | * When card bus bridge is supported, this would be enhanced. | |
198 | */ | |
199 | int is_bridge; | |
200 | ||
201 | /* pcie stuff */ | |
202 | int is_express; /* is this device pci express? */ | |
203 | ||
204 | /* device isn't hot-pluggable */ | |
205 | int no_hotplug; | |
206 | ||
207 | /* rom bar */ | |
208 | const char *romfile; | |
209 | } PCIDeviceClass; | |
210 | ||
0ae16251 | 211 | typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
2cdfe53c JK |
212 | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
213 | MSIMessage msg); | |
214 | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); | |
bbef882c MT |
215 | typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, |
216 | unsigned int vector_start, | |
217 | unsigned int vector_end); | |
2cdfe53c | 218 | |
87ecb68b | 219 | struct PCIDevice { |
6b1b92d3 | 220 | DeviceState qdev; |
5fa45de5 | 221 | |
87ecb68b | 222 | /* PCI config space */ |
a9f49946 | 223 | uint8_t *config; |
b7ee1603 | 224 | |
ebabb67a | 225 | /* Used to enable config checks on load. Note that writable bits are |
bd4b65ee | 226 | * never checked even if set in cmask. */ |
a9f49946 | 227 | uint8_t *cmask; |
bd4b65ee | 228 | |
b7ee1603 | 229 | /* Used to implement R/W bytes */ |
a9f49946 | 230 | uint8_t *wmask; |
87ecb68b | 231 | |
92ba5f51 IY |
232 | /* Used to implement RW1C(Write 1 to Clear) bytes */ |
233 | uint8_t *w1cmask; | |
234 | ||
6f4cbd39 | 235 | /* Used to allocate config space for capabilities. */ |
a9f49946 | 236 | uint8_t *used; |
6f4cbd39 | 237 | |
87ecb68b PB |
238 | /* the following fields are read only */ |
239 | PCIBus *bus; | |
09f1bbcd | 240 | int32_t devfn; |
87ecb68b PB |
241 | char name[64]; |
242 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
817dcc53 | 243 | AddressSpace bus_master_as; |
1c380f94 | 244 | MemoryRegion bus_master_enable_region; |
87ecb68b PB |
245 | |
246 | /* do not access the following fields */ | |
247 | PCIConfigReadFunc *config_read; | |
248 | PCIConfigWriteFunc *config_write; | |
87ecb68b PB |
249 | |
250 | /* IRQ objects for the INTA-INTD pins. */ | |
251 | qemu_irq *irq; | |
252 | ||
e01fd687 AW |
253 | /* Legacy PCI VGA regions */ |
254 | MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; | |
255 | bool has_vga; | |
256 | ||
87ecb68b | 257 | /* Current IRQ levels. Used internally by the generic PCI code. */ |
d036bb21 | 258 | uint8_t irq_state; |
02eb84d0 MT |
259 | |
260 | /* Capability bits */ | |
261 | uint32_t cap_present; | |
262 | ||
263 | /* Offset of MSI-X capability in config space */ | |
264 | uint8_t msix_cap; | |
265 | ||
266 | /* MSI-X entries */ | |
267 | int msix_entries_nr; | |
268 | ||
d35e428c AW |
269 | /* Space to store MSIX table & pending bit array */ |
270 | uint8_t *msix_table; | |
271 | uint8_t *msix_pba; | |
53f94925 AW |
272 | /* MemoryRegion container for msix exclusive BAR setup */ |
273 | MemoryRegion msix_exclusive_bar; | |
d35e428c AW |
274 | /* Memory Regions for MSIX table and pending bit entries. */ |
275 | MemoryRegion msix_table_mmio; | |
276 | MemoryRegion msix_pba_mmio; | |
02eb84d0 MT |
277 | /* Reference-count for entries actually in use by driver. */ |
278 | unsigned *msix_entry_used; | |
50322249 MT |
279 | /* MSIX function mask set or MSIX disabled */ |
280 | bool msix_function_masked; | |
f16c4abf JQ |
281 | /* Version id needed for VMState */ |
282 | int32_t version_id; | |
c2039bd0 | 283 | |
e4c7d2ae IY |
284 | /* Offset of MSI capability in config space */ |
285 | uint8_t msi_cap; | |
286 | ||
0428527c IY |
287 | /* PCI Express */ |
288 | PCIExpressDevice exp; | |
289 | ||
1dc324d2 MT |
290 | /* SHPC */ |
291 | SHPCDevice *shpc; | |
292 | ||
c2039bd0 | 293 | /* Location of option rom */ |
8c52c8f3 | 294 | char *romfile; |
14caaf7f AK |
295 | bool has_rom; |
296 | MemoryRegion rom; | |
88169ddf | 297 | uint32_t rom_bar; |
2cdfe53c | 298 | |
0ae16251 JK |
299 | /* INTx routing notifier */ |
300 | PCIINTxRoutingNotifier intx_routing_notifier; | |
301 | ||
2cdfe53c JK |
302 | /* MSI-X notifiers */ |
303 | MSIVectorUseNotifier msix_vector_use_notifier; | |
304 | MSIVectorReleaseNotifier msix_vector_release_notifier; | |
bbef882c | 305 | MSIVectorPollNotifier msix_vector_poll_notifier; |
87ecb68b PB |
306 | }; |
307 | ||
e824b2cc AK |
308 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
309 | uint8_t attr, MemoryRegion *memory); | |
e01fd687 AW |
310 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, |
311 | MemoryRegion *io_lo, MemoryRegion *io_hi); | |
312 | void pci_unregister_vga(PCIDevice *pci_dev); | |
16a96f28 | 313 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); |
87ecb68b | 314 | |
ca77089d IY |
315 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
316 | uint8_t offset, uint8_t size); | |
6f4cbd39 MT |
317 | |
318 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
319 | ||
6f4cbd39 MT |
320 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
321 | ||
322 | ||
87ecb68b PB |
323 | uint32_t pci_default_read_config(PCIDevice *d, |
324 | uint32_t address, int len); | |
325 | void pci_default_write_config(PCIDevice *d, | |
326 | uint32_t address, uint32_t val, int len); | |
327 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
328 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
f5e6fed8 | 329 | MemoryRegion *pci_address_space(PCIDevice *dev); |
e11d6439 | 330 | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
87ecb68b | 331 | |
5d4e84c8 | 332 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
87ecb68b | 333 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
3afa9bb4 | 334 | typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
e927d487 MT |
335 | |
336 | typedef enum { | |
337 | PCI_HOTPLUG_DISABLED, | |
338 | PCI_HOTPLUG_ENABLED, | |
339 | PCI_COLDPLUG_ENABLED, | |
340 | } PCIHotplugState; | |
341 | ||
342 | typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, | |
343 | PCIHotplugState state); | |
cf09458d AW |
344 | |
345 | #define TYPE_PCI_BUS "PCI" | |
346 | #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) | |
347 | #define TYPE_PCIE_BUS "PCIE" | |
348 | ||
8c0bf9e2 | 349 | bool pci_bus_is_express(PCIBus *bus); |
0889464a | 350 | bool pci_bus_is_root(PCIBus *bus); |
21eea4b3 | 351 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
1e39101c | 352 | const char *name, |
aee97b84 AK |
353 | MemoryRegion *address_space_mem, |
354 | MemoryRegion *address_space_io, | |
60a0e443 | 355 | uint8_t devfn_min, const char *typename); |
1e39101c | 356 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
aee97b84 AK |
357 | MemoryRegion *address_space_mem, |
358 | MemoryRegion *address_space_io, | |
60a0e443 | 359 | uint8_t devfn_min, const char *typename); |
21eea4b3 GH |
360 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
361 | void *irq_opaque, int nirq); | |
9ddf8437 | 362 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
87c30546 | 363 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); |
91e56159 IY |
364 | /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ |
365 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); | |
02e2da45 PB |
366 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
367 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 368 | void *irq_opaque, |
aee97b84 AK |
369 | MemoryRegion *address_space_mem, |
370 | MemoryRegion *address_space_io, | |
60a0e443 | 371 | uint8_t devfn_min, int nirq, const char *typename); |
3afa9bb4 MT |
372 | void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); |
373 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); | |
d6e65d54 | 374 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); |
0ae16251 JK |
375 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus); |
376 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
377 | PCIINTxRoutingNotifier notifier); | |
0ead87c8 | 378 | void pci_device_reset(PCIDevice *dev); |
9bb33586 | 379 | void pci_bus_reset(PCIBus *bus); |
87ecb68b | 380 | |
29b358f9 DG |
381 | PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, |
382 | const char *default_model, | |
5607c388 | 383 | const char *default_devaddr); |
29b358f9 DG |
384 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
385 | const char *default_model, | |
07caea31 | 386 | const char *default_devaddr); |
129d42fb AJ |
387 | |
388 | PCIDevice *pci_vga_init(PCIBus *bus); | |
389 | ||
87ecb68b | 390 | int pci_bus_num(PCIBus *s); |
7aa8cbb9 AP |
391 | void pci_for_each_device(PCIBus *bus, int bus_num, |
392 | void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), | |
393 | void *opaque); | |
1ef7a2a2 | 394 | PCIBus *pci_find_primary_bus(void); |
c473d18d | 395 | PCIBus *pci_device_root_bus(const PCIDevice *d); |
568f0690 | 396 | const char *pci_root_bus_path(PCIDevice *dev); |
5256d8bf | 397 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); |
f3006dd1 | 398 | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
85c6e4fa | 399 | PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr); |
87ecb68b | 400 | |
6ac363b5 DG |
401 | int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
402 | unsigned int *slotp, unsigned int *funcp); | |
880345c4 | 403 | |
4c92325b IY |
404 | void pci_device_deassert_intx(PCIDevice *dev); |
405 | ||
e00387d5 | 406 | typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); |
5fa45de5 | 407 | |
e00387d5 | 408 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); |
5fa45de5 | 409 | |
64d50b8b MT |
410 | static inline void |
411 | pci_set_byte(uint8_t *config, uint8_t val) | |
412 | { | |
413 | *config = val; | |
414 | } | |
415 | ||
416 | static inline uint8_t | |
cb95c2e4 | 417 | pci_get_byte(const uint8_t *config) |
64d50b8b MT |
418 | { |
419 | return *config; | |
420 | } | |
421 | ||
14e12559 MT |
422 | static inline void |
423 | pci_set_word(uint8_t *config, uint16_t val) | |
424 | { | |
425 | cpu_to_le16wu((uint16_t *)config, val); | |
426 | } | |
427 | ||
428 | static inline uint16_t | |
cb95c2e4 | 429 | pci_get_word(const uint8_t *config) |
14e12559 | 430 | { |
cb95c2e4 | 431 | return le16_to_cpupu((const uint16_t *)config); |
14e12559 MT |
432 | } |
433 | ||
434 | static inline void | |
435 | pci_set_long(uint8_t *config, uint32_t val) | |
436 | { | |
437 | cpu_to_le32wu((uint32_t *)config, val); | |
438 | } | |
439 | ||
440 | static inline uint32_t | |
cb95c2e4 | 441 | pci_get_long(const uint8_t *config) |
14e12559 | 442 | { |
cb95c2e4 | 443 | return le32_to_cpupu((const uint32_t *)config); |
14e12559 MT |
444 | } |
445 | ||
fb5ce7d2 IY |
446 | static inline void |
447 | pci_set_quad(uint8_t *config, uint64_t val) | |
448 | { | |
449 | cpu_to_le64w((uint64_t *)config, val); | |
450 | } | |
451 | ||
452 | static inline uint64_t | |
cb95c2e4 | 453 | pci_get_quad(const uint8_t *config) |
fb5ce7d2 | 454 | { |
cb95c2e4 | 455 | return le64_to_cpup((const uint64_t *)config); |
fb5ce7d2 IY |
456 | } |
457 | ||
deb54399 AL |
458 | static inline void |
459 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
460 | { | |
14e12559 | 461 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
462 | } |
463 | ||
464 | static inline void | |
465 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
466 | { | |
14e12559 | 467 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
468 | } |
469 | ||
cf602c7b IE |
470 | static inline void |
471 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) | |
472 | { | |
473 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); | |
474 | } | |
475 | ||
173a543b BS |
476 | static inline void |
477 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
478 | { | |
14e12559 | 479 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
480 | } |
481 | ||
cf602c7b IE |
482 | static inline void |
483 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) | |
484 | { | |
485 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); | |
486 | } | |
487 | ||
488 | static inline void | |
489 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) | |
490 | { | |
491 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); | |
492 | } | |
493 | ||
aabcf526 IY |
494 | /* |
495 | * helper functions to do bit mask operation on configuration space. | |
496 | * Just to set bit, use test-and-set and discard returned value. | |
497 | * Just to clear bit, use test-and-clear and discard returned value. | |
498 | * NOTE: They aren't atomic. | |
499 | */ | |
500 | static inline uint8_t | |
501 | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) | |
502 | { | |
503 | uint8_t val = pci_get_byte(config); | |
504 | pci_set_byte(config, val & ~mask); | |
505 | return val & mask; | |
506 | } | |
507 | ||
508 | static inline uint8_t | |
509 | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) | |
510 | { | |
511 | uint8_t val = pci_get_byte(config); | |
512 | pci_set_byte(config, val | mask); | |
513 | return val & mask; | |
514 | } | |
515 | ||
516 | static inline uint16_t | |
517 | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) | |
518 | { | |
519 | uint16_t val = pci_get_word(config); | |
520 | pci_set_word(config, val & ~mask); | |
521 | return val & mask; | |
522 | } | |
523 | ||
524 | static inline uint16_t | |
525 | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) | |
526 | { | |
527 | uint16_t val = pci_get_word(config); | |
528 | pci_set_word(config, val | mask); | |
529 | return val & mask; | |
530 | } | |
531 | ||
532 | static inline uint32_t | |
533 | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) | |
534 | { | |
535 | uint32_t val = pci_get_long(config); | |
536 | pci_set_long(config, val & ~mask); | |
537 | return val & mask; | |
538 | } | |
539 | ||
540 | static inline uint32_t | |
541 | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) | |
542 | { | |
543 | uint32_t val = pci_get_long(config); | |
544 | pci_set_long(config, val | mask); | |
545 | return val & mask; | |
546 | } | |
547 | ||
548 | static inline uint64_t | |
549 | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) | |
550 | { | |
551 | uint64_t val = pci_get_quad(config); | |
552 | pci_set_quad(config, val & ~mask); | |
553 | return val & mask; | |
554 | } | |
555 | ||
556 | static inline uint64_t | |
557 | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) | |
558 | { | |
559 | uint64_t val = pci_get_quad(config); | |
560 | pci_set_quad(config, val | mask); | |
561 | return val & mask; | |
562 | } | |
563 | ||
c9f50cea MT |
564 | /* Access a register specified by a mask */ |
565 | static inline void | |
566 | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) | |
567 | { | |
568 | uint8_t val = pci_get_byte(config); | |
569 | uint8_t rval = reg << (ffs(mask) - 1); | |
570 | pci_set_byte(config, (~mask & val) | (mask & rval)); | |
571 | } | |
572 | ||
573 | static inline uint8_t | |
574 | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) | |
575 | { | |
576 | uint8_t val = pci_get_byte(config); | |
577 | return (val & mask) >> (ffs(mask) - 1); | |
578 | } | |
579 | ||
580 | static inline void | |
581 | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) | |
582 | { | |
583 | uint16_t val = pci_get_word(config); | |
584 | uint16_t rval = reg << (ffs(mask) - 1); | |
585 | pci_set_word(config, (~mask & val) | (mask & rval)); | |
586 | } | |
587 | ||
588 | static inline uint16_t | |
589 | pci_get_word_by_mask(uint8_t *config, uint16_t mask) | |
590 | { | |
591 | uint16_t val = pci_get_word(config); | |
592 | return (val & mask) >> (ffs(mask) - 1); | |
593 | } | |
594 | ||
595 | static inline void | |
596 | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) | |
597 | { | |
598 | uint32_t val = pci_get_long(config); | |
599 | uint32_t rval = reg << (ffs(mask) - 1); | |
600 | pci_set_long(config, (~mask & val) | (mask & rval)); | |
601 | } | |
602 | ||
603 | static inline uint32_t | |
604 | pci_get_long_by_mask(uint8_t *config, uint32_t mask) | |
605 | { | |
606 | uint32_t val = pci_get_long(config); | |
607 | return (val & mask) >> (ffs(mask) - 1); | |
608 | } | |
609 | ||
610 | static inline void | |
611 | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) | |
612 | { | |
613 | uint64_t val = pci_get_quad(config); | |
614 | uint64_t rval = reg << (ffs(mask) - 1); | |
615 | pci_set_quad(config, (~mask & val) | (mask & rval)); | |
616 | } | |
617 | ||
618 | static inline uint64_t | |
619 | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) | |
620 | { | |
621 | uint64_t val = pci_get_quad(config); | |
622 | return (val & mask) >> (ffs(mask) - 1); | |
623 | } | |
624 | ||
49823868 IY |
625 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
626 | const char *name); | |
627 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, | |
628 | bool multifunction, | |
629 | const char *name); | |
499cf102 | 630 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
6b1b92d3 PB |
631 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
632 | ||
3c18685f | 633 | static inline int pci_is_express(const PCIDevice *d) |
a9f49946 IY |
634 | { |
635 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; | |
636 | } | |
637 | ||
3c18685f | 638 | static inline uint32_t pci_config_size(const PCIDevice *d) |
a9f49946 IY |
639 | { |
640 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; | |
641 | } | |
642 | ||
ec174575 | 643 | /* DMA access functions */ |
df32fd1c | 644 | static inline AddressSpace *pci_get_address_space(PCIDevice *dev) |
d86a77f8 | 645 | { |
df32fd1c | 646 | return &dev->bus_master_as; |
d86a77f8 DG |
647 | } |
648 | ||
ec174575 DG |
649 | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
650 | void *buf, dma_addr_t len, DMADirection dir) | |
651 | { | |
df32fd1c | 652 | dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); |
ec174575 DG |
653 | return 0; |
654 | } | |
655 | ||
656 | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, | |
657 | void *buf, dma_addr_t len) | |
658 | { | |
659 | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); | |
660 | } | |
661 | ||
662 | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, | |
663 | const void *buf, dma_addr_t len) | |
664 | { | |
665 | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); | |
666 | } | |
667 | ||
668 | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ | |
669 | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ | |
670 | dma_addr_t addr) \ | |
671 | { \ | |
df32fd1c | 672 | return ld##_l##_dma(pci_get_address_space(dev), addr); \ |
ec174575 DG |
673 | } \ |
674 | static inline void st##_s##_pci_dma(PCIDevice *dev, \ | |
d86a77f8 | 675 | dma_addr_t addr, uint##_bits##_t val) \ |
ec174575 | 676 | { \ |
df32fd1c | 677 | st##_s##_dma(pci_get_address_space(dev), addr, val); \ |
ec174575 DG |
678 | } |
679 | ||
680 | PCI_DMA_DEFINE_LDST(ub, b, 8); | |
681 | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) | |
682 | PCI_DMA_DEFINE_LDST(l_le, l_le, 32); | |
683 | PCI_DMA_DEFINE_LDST(q_le, q_le, 64); | |
684 | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) | |
685 | PCI_DMA_DEFINE_LDST(l_be, l_be, 32); | |
686 | PCI_DMA_DEFINE_LDST(q_be, q_be, 64); | |
687 | ||
688 | #undef PCI_DMA_DEFINE_LDST | |
689 | ||
690 | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, | |
691 | dma_addr_t *plen, DMADirection dir) | |
692 | { | |
ec174575 DG |
693 | void *buf; |
694 | ||
df32fd1c | 695 | buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); |
ec174575 DG |
696 | return buf; |
697 | } | |
698 | ||
699 | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, | |
700 | DMADirection dir, dma_addr_t access_len) | |
701 | { | |
df32fd1c | 702 | dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); |
ec174575 DG |
703 | } |
704 | ||
705 | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, | |
706 | int alloc_hint) | |
707 | { | |
f487b677 | 708 | qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); |
ec174575 DG |
709 | } |
710 | ||
701a8f76 PB |
711 | extern const VMStateDescription vmstate_pci_device; |
712 | ||
713 | #define VMSTATE_PCI_DEVICE(_field, _state) { \ | |
714 | .name = (stringify(_field)), \ | |
715 | .size = sizeof(PCIDevice), \ | |
716 | .vmsd = &vmstate_pci_device, \ | |
717 | .flags = VMS_STRUCT, \ | |
718 | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ | |
719 | } | |
720 | ||
721 | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ | |
722 | .name = (stringify(_field)), \ | |
723 | .size = sizeof(PCIDevice), \ | |
724 | .vmsd = &vmstate_pci_device, \ | |
725 | .flags = VMS_STRUCT|VMS_POINTER, \ | |
726 | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ | |
727 | } | |
728 | ||
87ecb68b | 729 | #endif |