]>
Commit | Line | Data |
---|---|---|
20599463 MT |
1 | #ifndef QEMU_PCI_BUS_H |
2 | #define QEMU_PCI_BUS_H | |
cfb0a50a IY |
3 | |
4 | /* | |
952deab6 | 5 | * PCI Bus and Bridge datastructures. |
68f79994 | 6 | * |
952deab6 MT |
7 | * Do not access the following members directly; |
8 | * use accessor functions in pci.h, pci_bridge.h | |
cfb0a50a IY |
9 | */ |
10 | ||
cfb0a50a IY |
11 | struct PCIBus { |
12 | BusState qbus; | |
e00387d5 AK |
13 | PCIIOMMUFunc iommu_fn; |
14 | void *iommu_opaque; | |
6f3279b5 | 15 | uint8_t devfn_min; |
cfb0a50a IY |
16 | pci_set_irq_fn set_irq; |
17 | pci_map_irq_fn map_irq; | |
3afa9bb4 | 18 | pci_route_irq_fn route_intx_to_irq; |
cfb0a50a | 19 | void *irq_opaque; |
90a20dbb | 20 | PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX]; |
cfb0a50a | 21 | PCIDevice *parent_dev; |
5968eca3 AK |
22 | MemoryRegion *address_space_mem; |
23 | MemoryRegion *address_space_io; | |
cfb0a50a IY |
24 | |
25 | QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ | |
26 | QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ | |
27 | ||
28 | /* The bus IRQ state is the logical OR of the connected devices. | |
29 | Keep a count of the number of devices with raised IRQs. */ | |
30 | int nirq; | |
31 | int *irq_count; | |
32 | }; | |
33 | ||
b308c82c AK |
34 | typedef struct PCIBridgeWindows PCIBridgeWindows; |
35 | ||
36 | /* | |
37 | * Aliases for each of the address space windows that the bridge | |
38 | * can forward. Mapped into the bridge's parent's address space, | |
39 | * as subregions. | |
40 | */ | |
41 | struct PCIBridgeWindows { | |
42 | MemoryRegion alias_pref_mem; | |
43 | MemoryRegion alias_mem; | |
44 | MemoryRegion alias_io; | |
ba7d8515 AW |
45 | /* |
46 | * When bridge control VGA forwarding is enabled, bridges will | |
47 | * provide positive decode on the PCI VGA defined I/O port and | |
48 | * MMIO ranges. When enabled forwarding is only qualified on the | |
49 | * I/O and memory enable bits in the bridge command register. | |
50 | */ | |
51 | MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS]; | |
b308c82c AK |
52 | }; |
53 | ||
f055e96b AF |
54 | #define TYPE_PCI_BRIDGE "base-pci-bridge" |
55 | #define PCI_BRIDGE(obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE) | |
56 | ||
68f79994 | 57 | struct PCIBridge { |
f055e96b AF |
58 | /*< private >*/ |
59 | PCIDevice parent_obj; | |
60 | /*< public >*/ | |
68f79994 IY |
61 | |
62 | /* private member */ | |
7e98e3af | 63 | PCIBus sec_bus; |
336411ca MT |
64 | /* |
65 | * Memory regions for the bridge's address spaces. These regions are not | |
66 | * directly added to system_memory/system_io or its descendants. | |
67 | * Bridge's secondary bus points to these, so that devices | |
68 | * under the bridge see these regions as its address spaces. | |
69 | * The regions are as large as the entire address space - | |
70 | * they don't take into account any windows. | |
71 | */ | |
72 | MemoryRegion address_space_mem; | |
73 | MemoryRegion address_space_io; | |
b308c82c AK |
74 | |
75 | PCIBridgeWindows *windows; | |
76 | ||
68f79994 IY |
77 | pci_map_irq_fn map_irq; |
78 | const char *bus_name; | |
79 | }; | |
cfb0a50a | 80 | |
20599463 | 81 | #endif /* QEMU_PCI_BUS_H */ |